Abstract: A light-guiding cover structure includes a top cover unit and a light-guiding unit. The top cover unit has a plurality of receiving spaces formed therein. The light-guiding unit includes a plurality of light-guiding groups, wherein each light-guiding group includes a plurality of optical fiber cables received in the corresponding receiving space, and each optical fiber cable has two opposite ends exposed from the bottom surface of the top cover unit and respectively facing at least one light-emitting device and at least one light-sensing device that have been disposed under the top cover unit. Therefore, the optical fiber cables received in the corresponding receiving space, thus when the light-guiding cover structure is applied to the LED package chip classification system, the aspect of the LED package chip classification system can be enhanced.

Abstract: A method of manufacturing a semiconductor device which solves a problem with a burn-in process where current and voltage are applied to finished semiconductor devices at high-temperature. The method uses an organic multilayer wiring substrate for a burn-in board in which power supply/grounding wiring is formed with microscopic openings formed at least almost all over the areas around sockets over the front or back surface of the substrate. For increasing the supply voltage and reference voltage for the burn-in board and other purposes, whenever possible, signal wires are disposed in inner wiring layers of the board. The related-art burn-in board which has a solid or blanket-type conductor pattern in an outermost layer as wiring for supply or reference voltage may cause an insulating protective film over the metal wiring to peel due to weak adhesion between the wiring and film when thermal cycles are repeated. The method solves the problem.

Abstract: A TFT substrate (20) forming a part of a liquid crystal display panel includes: respective pixels having mutually adjacent first sub-pixels and second sub-pixels; first source electrodes (14aba) that branch towards the first sub-pixels and form a portion of respective first TFTs (5a) after respective source lines (14a) between the respective pixels continue along respective gate lines (11a) extending between the first sub-pixels and second sub-pixels of the respective pixels; and a second source electrode (14abb) that branches towards the second sub-pixel and forms a portion of the respective second TFTs (5b). The respective gate lines (11a) have openings where the respective source lines (14a) have branched.

Abstract: A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

Abstract: A display apparatus includes a sealing portion. A method for fabricating the sealing portion includes: irradiating a pulse laser beam onto a deposition target to form the sealing portion at an edge where a substrate and an encapsulation face each, wherein a display unit is formed on the substrate, and the encapsulation is configured to seal the substrate; bonding the substrate and the encapsulation to each other; hardening the sealing portion; and monitoring the sealing portion. Thus, structural strength of the sealing portion is improved.

Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.

Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Abstract: A method for manufacturing an LED module includes following steps: providing a SMT (Surface Mount Technology) apparatus having a CCD (Charge-Coupled Device) image sensor and a nozzle, and providing a PCB and fixing the PCB in the SMT apparatus; providing a plurality of LEDs and mounting the LEDs on the PCB by the SMT apparatus; providing a plurality of lenses each having a plurality of patterned portions formed on an outer face of the lens, and the CCD image sensor imaging the lens and identifying the patterned portions, and then the SMT apparatus obtaining a location of the lens relative to the LED; positioning the lens on the PCB to cover the LED by the SMT apparatus; and fixing the lens on the PCB.

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Abstract: An embodiment of the invention provide a liquid crystal panel comprising a driving chip assembly comprising: a chip lead wiring and a chip repair line, which are overlapped but insulated from each other; an array substrate comprising an array substrate lead wiring and an array substrate repair line, which are overlapped but insulated from each other; wherein the driving chip assembly is mounted on the array substrate which is electrically connected with the corresponding chip lead wiring connection, and the two ends of the chip repair line is electrically connected with the corresponding two ends of the array substrate repair line respectively.

Abstract: Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate. An alignment mark formed over the wiring substrate is aligned with an alignment mark formed on a front surface of the logic chip, whereby the logic chip is mounted over the wiring substrate. An alignment mark formed on a back surface of the logic chip is aligned with an alignment mark formed on a front surface of the laminated body, whereby the laminated body is mounted over the back surface of the logic chip LG.

Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: A flexible film comprising a wavelength converting material is positioned over a light source. The flexible film is conformed to a predetermined shape. In some embodiments, the light source is a light emitting diode mounted on a support substrate. The diode is aligned with an indentation in a mold such that the flexible film is disposed between the support substrate and the mold. Transparent molding material is disposed between the support substrate and the mold. The support substrate and the mold are pressed together to cause the molding material to fill the indentation. The flexible film conforms to the shape of the light source or the mold.

Abstract: A method of manufacturing an organic light emitting display apparatus, and an organic light emitting display apparatus manufactured by the method, the method being suitable for mass producing a large substrate, enabling high-definition patterning, and allowing controlling of a distance between a patterning slit sheet and a substrate which are moved relative to each other.

Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.

Abstract: Various technologies pertaining to characterizing a component of a large surface area array electronic device, such as a focal plane array (FPA), are described. A first semiconductor chip is reversibly hybridized with a second semiconductor chip through use of a conductive layer. Responsive to being reversibly hybridized, at least one of the first semiconductor chip or the second semiconductor chip is characterized as being defective or suitable for deployment. Thereafter, the conductive layer is removed, and the first semiconductor chip is separated from the second semiconductor chip without damaging either of the first semiconductor chip or the second semiconductor chip.

Abstract: A method for encapsulating solar cells includes a curing step that renders CIGS or other types of solar cell absorber layers resistant to degradation by high-temperature lamination processes. The curing process takes place after IV test and prior to the lamination of an encapsulant film. The curing step is carried out in conjunction with a light soaking step that takes place prior to the IV test. The curing process takes place for a time that may range from 10 minutes to two days and at a high relative humidity, RH. Relative humidities of 20-90% are used and have been effective in passivating selenium vacancy defects associated with the absorber layers. The cured absorber layers are resistant to degradation and produce a solar cell with a high solar cell efficiency.

Abstract: A method for testing a plurality of semiconductor devices arranged on a strip may include forming an array of semiconductor devices on a frame, wherein contact pads of adjacent semiconductor devices are shorted, partially cutting the strip to electrically isolate individual semiconductor devices in the array, placing the strip on an adhesive tape configured to withstand low temperatures (e.g., below ?20° C. or below ?50° C.), arranging the strip and tape on a test chuck, exposing the test chuck, strip, and tape to temperatures below an ambient temperature and testing the plurality of semiconductor devices while exposed to a low temperature. In one embodiment a KAPTON™ film is used as the adhesive tape.

Abstract: Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask.

Abstract: A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device package are disclosed. A method of manufacturing a semiconductor device comprises the steps of testing the semiconductor device using at least a first monitoring pad connected to an internal circuit of the semiconductor device via at least a first fuse circuit; after testing the semiconductor device, electrically disconnecting the first monitoring pad from the internal circuit by opening the first fuse circuit; and after testing of the semiconductor device, electrically connecting at least a first auxiliary pad to the first monitoring pad with at least a first connecting terminal, wherein the first auxiliary pad is connected, through at least a first conductive line, to at least a first power pad of the semiconductor device.

Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes, in a silicon substrate of the semiconductor chip, providing two TSVs (Through-Silicon-Vias) that are formed such that interfaces with the silicon substrate are covered with insulating films and bottom surface sides thereof do not penetrate through the silicon substrate, providing a high concentration impurity region in a peripheral region of the bottom surface sides of the TSVs in the silicon substrate, connecting a test circuit to the TSVs, inputting a test signal from one of the TSVs and detecting the test signal output via the high concentration impurity region and the other TSV, thereby evaluating a failure of the semiconductor chip, thinning a bottom surface of the semiconductor chip and removing the high concentration impurity region.

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.

Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a scattering layer. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a first bonding material. The first bonding material integrates the fluorescent materials. The scattering layer is provided on the fluorescent material layer and includes scattering materials and a second bonding material. The scattering materials are configured to scatter radiated light of the light emitting layer. The second bonding material integrates the scattering materials.

Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.

Abstract: The method for filling a liquid material, and the apparatus and the program make it possible, without changing a moving speed of an ejection device, to correct a change in ejection amount and to stabilize an application shape. The method fills a liquid material into a gap between a substrate and a work by using the capillary action. The method includes the steps of: generating an application pattern consisting of a plurality of application areas continuous to one another; assigning a plurality of ejection cycles, each obtained by combining the number of ejection pulses and the number of pause pulses at a predetermined ratio therebetween, to each of the application areas; and measuring an ejection amount at correction intervals and calculating a correction amount for the ejection amount.

Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.

Abstract: There are provided a susceptor having a recessed wafer mounting section, in which a semiconductor wafer is mounted and which is configured to include a circular bottom portion and a side wall portion, on an upper surface, a reaction chamber in which the susceptor is provided, an imaging unit that is provided above the reaction chamber and images the semiconductor wafer and the wafer mounting section, and an image analysis unit that analyzes the deviation of the semiconductor wafer from the wafer mounting section on the basis of an image captured by the imaging unit.

Abstract: The invention is directed to the provision of a method for manufacturing a semiconductor light-emitting element that eliminates the need for preparing a plurality of different fluorescent sheets. The method for manufacturing the semiconductor light-emitting element containing an LED die includes the steps of arranging the LED die on a fluorescent sheet containing a fluorescent substance and adjusting the amount by which the LED die is depressed into the fluorescent sheet so that the semiconductor light-emitting element has a desired color emission.

Abstract: A stack package includes a first semiconductor chip having a plurality of first pads, and a second semiconductor chip stacked on the first semiconductor chip and having a plurality of second pads corresponding to the first pads respectively, the second pads connected to the corresponding first pads. The first and second pads are arranged such that the first and second pads overlap with each other even after the first and second semiconductor chips are rotated relative to each other by a predetermined angle.

Abstract: Arrayed imaging systems include an array of detectors formed with a common base and a first array of layered optical elements, each one of the layered optical elements being optically connected with a detector in the array of detectors.

Abstract: Methods and systems to method to determine an adhesion force of an underfill material to a chip assembled in a flip-chip module are provided. A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module.

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Abstract: Semiconductor device assemblies having solid-state transducer (SST) devices and associated semiconductor devices, systems, and are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a support substrate, a transfer structure, and a plurality semiconductor structures between the support substrate and the transfer structure. The method further includes removing the support substrate to expose an active surface of the individual semiconductor structures and a trench between the individual semiconductor structures. The semiconductor structures can be attached to a carrier substrate that is optically transmissive such that the active surface can emit and/or receive the light through the carrier substrate. The individual semiconductor structures can then be processed on the carrier substrate with the support substrate removed.

Abstract: An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source.

Abstract: Provided is a luminance measurement method for accurately measuring luminance of each pixel even if pixel images of a display panel overlap each other on an imaging surface of a camera. Pixels of a display panel are imaged by a solid-state imaging camera. One or more pixels are turned on and imaged such that pixel images do not overlap each other on an imaging surface. A central exposure factor indicating luminance of the central part of the pixel image is calculated based on a picture element output corresponding to the central part. A peripheral exposure factor indicating luminance of the peripheral part of the pixel image is calculated based on a picture element output corresponding to the peripheral part. All pixels are turned on and imaged, and luminance of all pixels is calculated based on this imaged image, the central exposure factor, and the peripheral exposure factor.