Specified Crystallographic Orientation Patents (Class 438/150)
  • Patent number: 6528397
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203 is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko MIno
  • Patent number: 6528830
    Abstract: A semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the active layer has at least one recombination center which is located between the source and the drain and which extends from the substrate side through the active layer for less than the full depth thereof. The transistor can be fabricated by depositing the recombination centers on the substrate prior to depositing the active layer or by other methods such as diffusing material from the substrate side into the active layer.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: March 4, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Basil Lui, Piero Migliorato
  • Patent number: 6521492
    Abstract: In the thin-film semiconductor device fabrication method according to the present invention, after forming an amorphous semiconductor film, the film is crystallized in the solid phase state, then a portion of the semiconductor film is molten by irradiating it with a pulsed laser beam having an absorption coefficient in amorphous silicon that is greater than the absorption coefficient in polysilicon. Thereby, polycrystalline thin-film semiconductor devices having superior characteristics can be fabricated.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: February 18, 2003
    Assignees: Seiko Epson Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsutoshi Miyasaka, Hidetada Tokioka, Tetsuya Ogawa
  • Patent number: 6521473
    Abstract: The present invention relates to a method of fabricating a liquid crystal display panel that involves patterning a silicon film crystallized by sequential lateral solidification. The method comprises the steps of preparing a silicon film, crystallizing the silicon film by growing silicon grains on a slant with respect to a horizontal direction of the silicon film, and forming a driver and a pixel part using the crystallized silicon film wherein the driver and pixel part comprise devices having channels arranged in horizontal and perpendicular directions relative to the silicon film. The crystallized silicon film has uniform grain boundaries in the channels of the devices, thereby improving the products by providing uniform electrical characteristics of devices that comprise a driver and a pixel part of an LCD panel.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: February 18, 2003
    Assignee: LGPhilips LCD Co., Ltd.
    Inventor: Yun-Ho Jung
  • Patent number: 6521491
    Abstract: A method for fabricating an LCD device provided with an active region where a plurality of gate lines are arranged to cross a plurality of data lines so as to define a pixel region, and a cutting region between a pad part of the gate line and a shorting bar, the method includes the steps of forming a gate line including a gate electrode in the active region on a substrate and forming a gate metal pattern for connecting the gate line and the shorting bar in the cutting region, forming an insulating film on an entire surface of the active and cutting regions, forming a TFT provided with source and drain electrodes in the active region, depositing a passivation film on an entire surface of the active region and forming a contact hole at a drain electrode of the TFT and the gate metal pattern, forming a transparent electrode for electrically connecting to the drain electrode through contact hole, selectively etching the transparent electrode so that only a pixel electrode remains in the active region and the gate
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: February 18, 2003
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Hyung Chan Lee, Youn Bo Lee, Gi Bum Park, Ii Nam Song, Beung Hwa Jeong
  • Patent number: 6518103
    Abstract: A method for fabricating a NROM is described, in which a bottom anti-reflective coating (BARC) and a photoresist pattern are sequentially formed on a substrate that has a charge trapping layer formed thereon. An etching process is then performed to pattern the BARC and the charge trapping layer with the photoresist pattern as a mask. The etching process is conducted in an etching chamber equipped with a source power supply and a bias power supply, which two have a power ratio of 1.5˜3, while an etchant used therein is a gas plasma containing trifluoromethane (CHF3) and tetrafluoromethane (CF4). Thereafter, a buried drain is formed in the substrate, a buried drain oxide layer is formed on the buried drain, and then plural gates are formed on the substrate.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: February 11, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Jiun-Ren Lai
  • Publication number: 20030027410
    Abstract: A thin film semiconductor device and a method for producing it are described. In the thin film layer of semiconductor of the device, a plurality of large size single-crystalline grains of semiconductor are formed in a regulated configuration, and each of single crystalline grains is equipped with one unit of electric circuit having a gate electrode, a source electrode and drain electrode. Such regulated arrangement of large size single-crystalline grains in the semiconductor layer is realized by a process including a step of irradiating the layer of amorphous or polycrystalline semiconductor with energy beam such as excimer laser so that maximum irradiation intensity points and minimum irradiation intensity points are arranged regulatedly. The device can have a high mobility such as about 500 cm2/V sec..
    Type: Application
    Filed: July 11, 2002
    Publication date: February 6, 2003
    Applicant: ALTEDEC
    Inventors: Masakiyo Matsumura, Yasuhisa Oana, Hiroyuki Abe, Yoshitaka Yamamoto, Hideo Koseki, Mitsunori Warabisako
  • Patent number: 6511892
    Abstract: Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of amorphous silicon. To further enhance uniformity in the formation of the hemispherical grain silicon, the exposed surface of the amorphous silicon can be seeded before crystallization to further enhance uniformity of the surface structures formed in the hemispherical grain silicon.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: January 28, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Er-Xuan Ping, Randhir Thakur
  • Patent number: 6511869
    Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: January 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Kai R. Schleupen, Takatoshi Tsujimura
  • Publication number: 20030013281
    Abstract: A method of crystallizing polysilicon, a method of fabricating a thin film transistor using the same, and a method of fabricating a liquid crystal display thereof form a polysilicon layer having uniformly oriented crystalline grains with high quality. A polysilicon crystallizing method includes forming a polysilicon layer on a substrate, making grains of the polysilicon layer amorphous except a portion of the grains having specific orientation, and crystallizing the polysilicon layer using the grains having the specific orientation.
    Type: Application
    Filed: July 8, 2002
    Publication date: January 16, 2003
    Inventor: Se Jin Chung
  • Publication number: 20030013239
    Abstract: In a thin film transistor, a first insulating film on a silicon layer formed in an island on a substrate is smaller in thickness than the silicon layer so that the stepped island edges is gentle in slope to facilitate covering the island with a second insulating film. This reduces occurrence of gate leak considerably. Since the peripheral region of the stepped island is smaller in thickness than the central region above the channel, it is possible to minimize occurrence of gate electrode breakage. The silicon layer contains two or more inert gas atoms, and the atoms smaller in mass number (e.g., He) are contained in and near an interface with a silicon active layer while the atoms larger in mass number (e.g., Ar) than those smaller in mass number are contained in and near a second interface with a gate elect.
    Type: Application
    Filed: August 30, 2002
    Publication date: January 16, 2003
    Applicant: NEC CORPORATION
    Inventors: Hiroshi Tanabe, Katsuhisa Yuda, Hiroshi Okumura, Yoshinobu Sato
  • Patent number: 6504174
    Abstract: A novel and very useful method for forming a crystal silicon film by introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and for eliminating or reducing the metal element existing within the crystal silicon film thus obtained is provided. The method for fabricating a semiconductor device comprises steps of intentionally introducing the metal element which promotes crystallization of silicon to the amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain the crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the region from which the thermal oxide film has been eliminated by implementing another thermal oxidation.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: January 7, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20020177259
    Abstract: The present invention relates to a method of fabricating a liquid crystal display panel that involves patterning a silicon film crystallized by sequential lateral solidification. The method comprises the steps of preparing a silicon film, crystallizing the silicon film by growing silicon grains on a slant with respect to a horizontal direction of the silicon film, and forming a driver and a pixel part using the crystallized silicon film wherein the driver and pixel part comprise devices having channels arranged in horizontal and perpendicular directions relative to the silicon film. The crystallized silicon film has uniform grain boundaries in the channels of the devices, thereby improving the products by providing uniform electrical characteristics of devices that comprise a driver and a pixel part of an LCD panel.
    Type: Application
    Filed: July 17, 2002
    Publication date: November 28, 2002
    Inventor: Yun-Ho Jung
  • Patent number: 6486046
    Abstract: It is possible to prevent lowering in productivity of thin-film transistors with no decrease in performance of the transistors. Provided are depositing an amorphous semiconductor film on a substrate, a first irradiating the amorphous semiconductor film with an energy-rich beam in an atmosphere of a gas containing an inert gas as a major component with a specific amount of oxygen, to change the amorphous semiconductor film into a polycrystalline semiconductor film, and a second irradiating the polycrystalline semiconductor film with an energy-rich beam in an atmosphere of a gas containing an inert gas as major component with oxygen of an amount less than the specific amount.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: November 26, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Fujimura, Shinichi Kawamura
  • Patent number: 6486812
    Abstract: A D/A conversion circuit is described which comprises a n switching, n capacitors and a coupling circuit. Upper n bit of the digital signal control n switches respectively and control charging and discharging of electric charge into the n capacitors, and the n capacitors are connected to the output line in an upper bit writing period. Lower n bit of the digital signal control the n switches and control charging and discharging of electric charge into the n capacitors, and the capacitors are connected to the output line through the coupling capacitor in a lower bit writing period.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: November 26, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yukio Tanaka
  • Patent number: 6480179
    Abstract: An image display device has an image display section including an insulating substrate having a matrix of pixels formed on an inner surface thereof and a liquid crystal layer sandwiched between the insulating substrate and a substrate opposing the insulating substrate. The image display device includes signal lines, driver circuits for driving the matrix of pixels via the signal lines, voltage amplifiers formed by polycrystalline semiconductor TFTs and each coupled between one of the signal lines and a corresponding one of the driver circuits. The signal lines, the driver circuits and the voltage amplifiers are formed on a surface of the insulating substrate on a side thereof facing the liquid crystal layer. A channel, a source and a drain of the polycrystalline semiconductor TFTs each are formed of a polycrystalline semiconductor film. A gate insulating film and a gate electrode are superposed on the polycrystalline semiconductor film in the order named.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventor: Hajime Akimoto
  • Patent number: 6468872
    Abstract: The present invention relates to a simplified method of fabricating a thin film transistor (TFT), including the steps of preparing a first conductive type TFT including a first semiconductor layer and a first gate electrode and a second conductive type TFT including a second semiconductor layer and a second gate electrode on a substrate; doping the first and second semiconductor layers with a first conductive type impurity using the first and second gate electrodes as a mask; forming a doping mask covering the first conductive type TFT; counter-doping the second semiconductor layer with a second conductive type impurity using the doping mask and the second gate electrode as masks; and forming a CMOS TFT by electrically connecting the first conductive type TFT to the second conductive type TFT.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: October 22, 2002
    Assignee: L.G. Philips LCD Co., Ltd
    Inventor: Joon-Young Yang
  • Patent number: 6468841
    Abstract: At least a part of the surface of a crystalline silicon semiconductor substrate is rendered porous to convert at least a part of the crystalline silicon semiconductor substrate to a porous silicon layer. A catalytic metal layer is formed on the porous silicon layer. An amorphous silicon thin film is formed on the catalytic metal layer. The amorphous silicon thin film is heated to monocrystallize the amorphous silicon thin film, thereby converting the amorphous silicon thin film to a crystalline silicon thin film. The crystalline silicon semiconductor substrate, provided with the crystalline silicon thin film, is joined to a support substrate so that the crystalline silicon thin film faces the support substrate. The crystalline silicon semiconductor substrate, together with the porous silicon layer, which is the crystalline silicon semiconductor substrate in its portion converted to a porous layer, is separated and removed from the crystalline silicon thin film joined to the support substrate.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: October 22, 2002
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shinichi Muramatsu, Harunori Sakaguchi, Susumu Takahashi
  • Patent number: 6468921
    Abstract: A thin-film forming method applied in an IC manufacturing process is disclosed. The thin-film forming method is used for forming a thin film on a topographically rugged substrate with an improved evenness. The method is characterized in that after a depositing step for forming the thin film is finished, the thin film is continuously ion bombed for a specific time to improve the evenness of the thin film.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: October 22, 2002
    Assignee: Winbond Electronics Corp.
    Inventors: Hon-Ling Shih, Chung-Chieh Juan, Fu-Chun Chen, An-Chow Chen
  • Patent number: 6458636
    Abstract: A method for forming a polycrystalline silicon layer for TFT according to the present invention includes steps of: depositing an amorphous silicon layer and a silicon oxidation layer on a substrate in this order; and implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: October 1, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Jong-Hoon Yi, Sang-Gul Lee, Won-Kyu Park
  • Publication number: 20020137265
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Application
    Filed: March 13, 2001
    Publication date: September 26, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Publication number: 20020125479
    Abstract: The invention relates to a MOSFET with a doped silicon source layer and a doped polycrystalline silicon gate layer and a doped silicon drain layer and to a method of fabricating the layers of such a transistors, in which an otherwise possible interaction between closely spaced layers or structural components of decreased size is eliminated or at least substantially reduced by incorporation in at least one layer of the MOSFET of an element from Group IV in a predetermined concentration.
    Type: Application
    Filed: November 5, 2001
    Publication date: September 12, 2002
    Inventors: Gunther Lippert, Abbas Ourmazd, Hans-Joerg Osten
  • Publication number: 20020117718
    Abstract: A method is provided to produce thin film transistors (TFTs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. A gate is formed overlying the polycrystalline film. The polycrystalline film is doped to produce source and drain regions.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Inventor: Apostolos Voutsas
  • Publication number: 20020115244
    Abstract: An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.
    Type: Application
    Filed: April 22, 2002
    Publication date: August 22, 2002
    Inventors: Sung-Bae Park, Jun Kim, Eun-Han Kim, Hee-Sung Kang, Young-Wug Kim
  • Publication number: 20020115243
    Abstract: A process to fabricate a thin film transistor using an intrinsic polycrystalline silicon film, by a method of: preparing a semiconductor assembly; forming an insulation layer on a substrate; forming a first amorphous silicon layer on said insulation layer; forming silicon nucleation sites on said first amorphous silicon layer, converting said first amorphous silicon layer into hemispherical grained silicon, said hemispherical grained silicon being formed about said silicon nucleation sites; forming a second amorphous silicon layer covering said hemispherical grained silicon; annealing said second amorphous silicon layer to convert said second amorphous silicon layer into a grained silicon film, said grained silicon film being formed about said hemispherical grained silicon and having a dimension of approximately 0.1 microns to 0.
    Type: Application
    Filed: April 26, 2002
    Publication date: August 22, 2002
    Inventor: Er-Xuan Ping
  • Patent number: 6432758
    Abstract: The present invention proposes a crystallization method of the poly-Si thin film in a thin film transistor. A substrate having an insulator layer is provided. An amorphous silicon layer or a micro-crystalline silicon layer having two thickness is first formed on the insulator layer. The region of thinner is defined as the channel region of the TFT, while the region of thicker can be defined as the source/drain regions of the TFT. Next, an excimer laser is used for crystallization. During the excimer laser irradiation, the amorphous silicon layer of thinner is completely melted, and the amorphous silicon layer of thicker is partially melted. The partially melted amorphous silicon layer is used as crystallization seeds.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: August 13, 2002
    Inventors: Huang-Chung Cheng, Ching-Wei Lin, Li-Jing Cheng
  • Publication number: 20020102821
    Abstract: A method is provided to improve uniformity between the channel characteristics of multiple sets of thin film transistors (TFTs) formed with different orientations on a polycrystalline film. The method is well suited to the production of TFTs for use as drivers on liquid crystal display devices, as well as other devices. TFT channels are formed over a polycrystalline region on a substrate such that the predominant crystal orientation of the polycrystalline region is a compromise orientation between an ideal orientation for one set of TFTs and an ideal orientation for another set of TFTs. In one preferred embodiment, where a set of row drivers and a set of column drivers are 90 degrees relative to each other, the predominant crystal orientation would be at approximately 45 degrees relative to both set of drivers.
    Type: Application
    Filed: January 29, 2001
    Publication date: August 1, 2002
    Inventor: Apostolos Voutsas
  • Patent number: 6426246
    Abstract: A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a portion of the amorphous silicon layer by excimer laser system, and the lateral-growth grain is formed by using the seeds to grow laterally by annealing the amorphous silicon layer, wherein the amorphous silicon layer defines an active region. Then, sequentially a dielectric layer and a polysilicon layer is deposited on the active region, wherein the dielectric layer and the polysilicon layer are gate electrodes, a gate is defined on the substrate, and the polysilicon layer is formed by etching. Next, source and drain regions are formed by implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: July 30, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Ting-Chang Chang, Du-Zen Peng, Chun-Yen Chang
  • Publication number: 20020052069
    Abstract: An object is to fabricate high quality thin-film semiconductor devices at comparatively low temperatures. After providing a local heating system, an active semiconductor layer is formed, and melt crystallization is promoted by irradiating a pulsed laser onto the active semiconductor layer.
    Type: Application
    Filed: June 8, 2001
    Publication date: May 2, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Jiroku, Mitsutoshi Miyasaka, Hidetada Tokioka, Tetsuya Ogawa
  • Publication number: 20020047122
    Abstract: In case of growing a polycrystalline silicon layer (10) by catalytic CVD on a substrate (4) such as glass substrate, quartz substrate or silicon substrate having formed an oxide film on its surface, the total pressure of the growth atmosphere is maintained in the range from 1.33×10−3 Pa to 4 Pa at least in the initial period of the growth, or alternatively, partial pressure of oxygen and moisture in the grow that atmosphere is maintained in the range from 6.65×10−10 to 2×10−6 Pa at least in the initial period of the growth. Thus, the maximum oxygen concentration of the grown polycrystalline silicon layer (10) becomes not higher than 3×1018 atoms/cm−3 at least in a region of the polycrystalline silicon layer with the thickness of 10 nm from the boundary with the substrate (4). It is thus ensured to grow a high-quality polycrystalline silicon layer having a quality required for use as a TFT polycrystalline silicon layer by catalytic CVD.
    Type: Application
    Filed: December 8, 2000
    Publication date: April 25, 2002
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6376285
    Abstract: An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: April 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Keith A. Joyner, Leland S. Swanson
  • Patent number: 6372558
    Abstract: The present invention provides an active matrix substrate having a built-in high-performance driver, in which a single crystal silicon thin film having high electron/hole mobility is uniformly deposited at a relatively low temperature, and an electrooptic device such as a thin film semiconductor device for display including the active matrix substrate. The single crystal silicon thin film is deposited by hetero epitaxial growth by a catalytic CVD method or the like using a crystalline sapphire thin film formed on the substrate as a seed so that the single crystal silicon layer obtained is used for top gate type MOSTFTs of the electrooptic device such as a LED or the like in which a display region and a peripheral driving circuit region are integrated.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: April 16, 2002
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Sato, Hajime Yagi
  • Publication number: 20020042168
    Abstract: A method for forming a polycrystalline silicon layer for TFT according to the present invention includes steps of: depositing an amorphous silicon layer and a silicon oxidation layer on a substrate in this order; and implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer.
    Type: Application
    Filed: December 7, 2001
    Publication date: April 11, 2002
    Inventors: Jong-Hoon Yi, Sang-Gul Lee, Won-Kyu Park
  • Patent number: 6344374
    Abstract: The present invention discloses a method of forming an isolation region in a silicon-containing substrate. The method includes forming a mask layer on the silicon-containing substrate. A window is subsequently formed in the mask layer to expose the isolation area to be formed in the substrate. An oxygen-containing region is formed in the substrate by introducing oxygen-containing ions through the window in the mask layer. Then, the oxygen-containing region is subjected to a thermal treatment, thereby resulting in a silicon oxide insulator (SiOx) for isolating electronic devices.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: February 5, 2002
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Horng-Huei Tseng
  • Patent number: 6338987
    Abstract: A method for forming a polycrystalline silicon layer for TFT according to the present invention includes steps of: depositing an amorphous silicon layer and a silicon oxidation layer on a substrate in this order; and implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: January 15, 2002
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Jong-Hoon Yi, Sang-Gul Lee, Won-Kyu Park
  • Patent number: 6337231
    Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a crystallization-promoting, catalyst is introduced.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: January 8, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Yasuhiko Takemura, Toru Takayama
  • Patent number: 6335213
    Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: January 1, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 6323072
    Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: November 27, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Komaya, Akiharu Miyanaga, Takeshi Fukunaga
  • Patent number: 6306694
    Abstract: A semiconductor device having high operating performance and reliability is disclosed, and its fabrication process is also disclosed. In an n-channel type TFT 302, an Lov region 207 is disposed, whereby a TFT structure highly resistant to hot carriers is realized. Further, in an n-channel type TFT 304 forming a pixel portion, Loff regions 217 to 220 are disposed, whereby a TFT structure having a low OFF-current value is realized. In this case, in the Lov region, the n-type impurity element exists at a concentration higher than that of the Loff regions, and the whole of the n-type impurity region (b) which constitutes the Lov region is sufficiently activated by optical annealing, so that a good junction portion is formed between the n-type impurity region and the channel forming region.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: October 23, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hidehito Kitakado
  • Patent number: 6306692
    Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating an impurity and a catalyst metal on the amorphous silicon layer using the gate electrode as a mask; and applying a DC voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: October 23, 2001
    Assignee: LG. Philips Lcd., Co. LTD
    Inventors: Seong Moh Seo, Sung Ki Kim
  • Publication number: 20010026006
    Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.
    Type: Application
    Filed: May 8, 2001
    Publication date: October 4, 2001
    Applicant: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
  • Patent number: 6294452
    Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: September 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, D. Mark Durcan, Brent D. Gilgen
  • Patent number: 6291261
    Abstract: Semiconductor wafers are glued onto a carrier foil which is stretched across a frame. Instead of restretching the carrier foil directly at a processing machine, the foil is restretched on an adapter frame which can be stored and then later manipulated in the processing machine. The adapter frame includes a clamping ring, a base ring, and a threaded ring which secures the carrier foil.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: September 18, 2001
    Assignee: Alphasem AG
    Inventors: Kurt Stark, Markus Keller
  • Patent number: 6287899
    Abstract: A method for manufacturing a thin film transistor array panel for a liquid crystal display is disclosed. The present invention enables to manufacture a thin film transistor array panel in lesser steps than the conventional method by fabricating certain film layers on the panel in one photolithography process. For this purpose, a mask that has parts of different light transmittance is used to fabricate multiple film layers in one photolithography process. The method according to the present invention can increase the productivity and yield by reducing the number of photolithography steps, which are expensive and time consuming.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: September 11, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Yong Park, Jong-Soo Yoon
  • Patent number: 6248606
    Abstract: In a method of manufacturing semiconductor chips for display, a semiconductor thin film is first formed on an insulating substrate, and then a series of processes including a heat-treatment process for the semiconductor thin film are carried out to form integrated thin film transistors on a sectioned area for one chip. Thereafter, pixel electrodes for one picture (frame) are formed within the sectioned area. During the series of processes, a laser pulse is irradiated onto the sectioned area by one shot to perform a heat treatment on the semiconductor thin film for one chip collectively and simultaneously (i.e., perform a batch heat treatment on the semiconductor thin film). Through the batch heat treatment, the crystallization of the semiconductor thin film is promoted. In addition, after the semiconductor thin film is doped with impurities, the activation of impurities doped in the semiconductor thin film can be performed by the batch heat treatment.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: June 19, 2001
    Assignee: Sony Corporation
    Inventors: Masumitsu Ino, Hisao Hayashi, Masafumi Kunii, Takenobu Urazono, Shizuo Nishihara, Masahiro Minegishi
  • Patent number: 6245615
    Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: June 12, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
  • Patent number: 6235614
    Abstract: A method for crystallizing an amorphous silicon layer and for fabricating a thin film transistor. An amorphous silicon layer is formed on a substrate, and patterned to form an active layer by etching the amorphous silicon layer using photolithography. The amorphous silicon layer is crystallized using sequential lateral solidification to form a crystallized active layer having a smooth surface. A smooth surface is obtained by the crystallization process without a subsequent smoothing step by canceling an increased volume of silicon during crystallization for an increased surface of the active silicon layer. The crystallized silicon layer is used to form a thin film transistor by forming a gate insulating layer and a gate electrode on the crystallized active layer, and forming a source and a drain region by doping the crystallized active layer with impurities in use of the gate electrode as a mask.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: May 22, 2001
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Myoung-Su Yang
  • Patent number: 6235560
    Abstract: A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: May 22, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yi Ma, Allen Yen
  • Publication number: 20010000756
    Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.
    Type: Application
    Filed: December 15, 2000
    Publication date: May 3, 2001
    Inventors: Shubneesh Batra, Monte Manning, Sanjay Banerjee, John Damiano
  • Patent number: 6214653
    Abstract: A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis L. Hsu, Li-Kong Wang