On Insulating Substrate Or Layer (e.g., Tft, Etc.) Patents (Class 438/149)
  • Patent number: 10388799
    Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki
  • Patent number: 10368434
    Abstract: Provided is a display device and a manufacturing method of the same. The display device includes: a base substrate having a top surface and a side surface, a display region over the top surface, a terminal over the top surface and between the display region and the side surface, the terminal being electrically connected to the display region, and an anisotropic conductive film over the terminal. An edge portion of the anisotropic conductive film is spaced from the side surface, and its distance is equal to or larger than 10 ?m and equal to or smaller than 1 mm.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 30, 2019
    Assignee: Japan Display Inc.
    Inventor: Takuya Nakagawa
  • Patent number: 10361260
    Abstract: A semiconductor device includes a base substrate, a first transistor including a first semiconductor pattern, a first control electrode, a first input electrode, and a first output electrode, each of which is disposed on the base substrate, a second transistor including a second semiconductor pattern, a second control electrode, a second input electrode, and a second output electrode, and a plurality of insulating layers. A single first through part exposes the first control electrode and the first semiconductor pattern disposed on both sides of the first control electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaybum Kim, Kyoungseok Son, Jihun Lim, Eoksu Kim, Junhyung Lim
  • Patent number: 10354869
    Abstract: A method of manufacturing a nanostructure includes: heating a mixed solution to a first temperature, the mixed solution including a solvent, a compound including indium, and an octadecylphosphonic acid; heating the mixed solution to a second temperature; injecting, after heating the mixed solution to the second temperature, a phosphine precursor into the mixed solution; and heating the mixed solution including the injected phosphine precursor to a third temperature.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 16, 2019
    Assignees: Samsung Display Co., Ltd., POSTECH Academy-Industry Foundation
    Inventors: Dae Hyun Kim, Jong Hyuk Kang, Hyun Deok Im, Hyun Min Cho, Yongju Kwon, Bomi Kim, Sung-Jee Kim, Mihye Lim
  • Patent number: 10326008
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10312312
    Abstract: Provided is a display device. A poly-Si layer is disposed on a substrate. A first metal layer is disposed on the poly-Si layer, and a metal oxide layer is disposed on the first metal layer. A second metal layer is disposed on the metal oxide layer. The first metal layer is overlapped with the second metal layer. The first metal layer and the second metal layer may be gate lines connected to different TFTs.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 4, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Eui Tae Kim, Bu Yeol Lee
  • Patent number: 10304942
    Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jyun-Ming Lin, Hua Feng Chen, Kuo-Hua Pan, Min-Yann Hsieh, C. H. Wu
  • Patent number: 10297635
    Abstract: A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3?), a semiconductor-layer thin film (4?) and a passivation-shielding-layer thin film (5?) successively; forming a pattern (5?) that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a?); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c?) and a drain electrode (4b?). The source electrode (4c?) and the drain electrode (4b?) are disposed on two sides of the active layer (4a?) respectively and in a same layer as the active layer (4a?).
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 21, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Huichao Gao, Zongmin Tian, Peng Li
  • Patent number: 10290666
    Abstract: The present disclosure relates to a thin film transistor (TFT) array substrate and a manufacturing method thereof. The manufacturing method includes adopting a shading metal layer to form the bottom gate electrode, depositing a buffer layer on the substrate having the bottom gate electrode, applying a patterned process on the buffer layer to reduce the thickness of the buffer layer on the bottom gate electrode, applying the patterned process on the semiconductor layer to form the semiconductor pattern corresponding to the bottom gate electrode within the thin area of the buffer layer. The present disclosure may reduce a thickness of the buffer layer corresponding to the bottom gate electrode, so as to improve the whole performance of the array substrate caused by the bottom gate electrode.
    Type: Grant
    Filed: May 27, 2017
    Date of Patent: May 14, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd
    Inventors: Mian Zeng, Xiaodi Liu
  • Patent number: 10290717
    Abstract: The thin film transistor (TFT) contains a gate electrode metallic layer above a substrate, a gate insulator layer covering the substrate and the gate electrode metallic layer, a first source electrode metallic layer and a first drain electrode metallic layer above the gate insulator layer and separated by a gap, an active layer above the first source and first drain electrode metallic layers filling the gap and forming a ditch in the active layer above the gap, and a second source electrode metallic layer and a second drain electrode metallic layer above the active layer at two lateral sides of the ditch, respectively. The second source/drain electrode metallic layer contacts the first source/drain electrode metallic layer. The TFT has lower parasitic capacitance and takes up less area. As such, when the TFT is applied to a LCD, the reduced space consumed by the TFT enhances pixel's aperture ratio.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 14, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Tuo Feng
  • Patent number: 10283628
    Abstract: A thin film transistor and manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes a source electrode, a drain electrode and an active layer; the source electrode, the drain electrode and the active layer are disposed in a same layer, the source electrode and the drain electrode are separately joined to the active layer through their respective side faces, a material of the source electrode and the drain electrode is metal, and a material of the active layer is a metal oxide semiconductor in correspondence with material of the source electrode and the drain electrode. With the thin film transistor, procedures can be decreased, thereby reducing costs.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 7, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Botao Song, Liang Lin, Zhixiang Zou, Yinhu Huang
  • Patent number: 10283610
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 7, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Patent number: 10269973
    Abstract: A TFT backplane structure includes a gate insulating layer that includes a three-layered portion, which includes, from bottom up, a dielectric layer, a SiNx layer, and a SiO2 layer, set at a location corresponding to a TFT in order to enhance the TFT reliability, and also includes a double-layered portion, which includes from bottom up, the dielectric layer and at least a portion of the SiNx layer, set at a location corresponding to a storage capacitor, or alternatively a single-layered structure that includes only the dielectric layer set at the location corresponding to the storage capacitor so that the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 23, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xingyu Zhou
  • Patent number: 10263089
    Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: April 16, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
  • Patent number: 10254609
    Abstract: An array substrate and a method of manufacturing the same, a display panel and a display device are provided. The array substrate includes a thin film transistor and a pixel electrode. An insulating layer is formed between a drain electrode of the thin film transistor and the pixel electrode. The drain electrode is in direct electrical contact with the pixel electrode through a via-hole in the insulating layer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 9, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shoukun Wang, Huibin Guo, Yuchun Feng, Liangliang Li
  • Patent number: 10249735
    Abstract: The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jian Min, Xiaolong Li, Zhengyin Xu, Ping Song, Youwei Wang
  • Patent number: 10249540
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • Patent number: 10244628
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 26, 2019
    Assignees: THE TRUSTEES OF PRINCETON UNIVERSITY, VORBECK MATERIALS CORPORATION
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'homme
  • Patent number: 10243016
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 10236280
    Abstract: A light emitting device package is provided. The light emitting device package includes three light emitting diode (LED) chips configured to emit light having different wavelengths, each of the three LED chips including a light emitting structure having a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; a through electrode portion disposed adjacent to the three LED chips; a molding portion encapsulating respective side surfaces of the three LED chips and the through electrode portion; a transparent electrode layer disposed on a first surface of the molding portion, the three LED chips, and the through electrode portion; and three individual electrodes exposed through a second surface of the molding portion and disposed on the three LED chips, respectively.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Min Kwon, Kyoung Jun Kim
  • Patent number: 10228231
    Abstract: In one aspect the invention provides a laminated device of flexible and compliant layers of material, such as used to provide a dielectric elastomer sensor. A flexible and compliant layer of material is affixed to a substrate to avoid strain during processing is bonded to another layer of flexible and compliant material and released from the substrate to form a laminate. The layer of flexible and compliant material affixed to the substrate may be inspected prior to bonding.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 12, 2019
    Assignee: Stretchsense Limited
    Inventors: Benjamin Marc O'Brien, Todd Alan Gisby, Antoni Edward Harbuz, Samuel Schlatter
  • Patent number: 10224326
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Balasubramanian S. Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
  • Patent number: 10217834
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 26, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Patent number: 10192879
    Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10192905
    Abstract: The present disclosure relates to a manufacturing method of array substrates, wherein a second masking process forming an active layer, a source electrode and a drain electrode further includes: forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence; applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask; applying a first wet etching process and a first dry etching process to etch the metal thin-film layer, the semiconductor thin-film layer, and the N+ doping thin-film layer; applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask; applying a second wet etching process to etch the metal thin-film layer; and peeling off the second photo-resistor mask, applying a second dry etching process to etch the N+ doping thin-film layer.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: January 29, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Wei Zhao, Xiangyang Xu
  • Patent number: 10181465
    Abstract: Embodiments of the invention provide an array substrate, a display device and a manufacturing method of the array substrate. The array substrate comprises a substrate (10) and a plurality of electrostatic discharge short-circuit rings (20) provided on the substrate. Each of the electrostatic discharge short-circuit rings (20) comprises a gate electrode (22), a gate insulating layer (26), an active layer (21), a source electrode (23), a drain electrode (24) and a passivation layer (30). Each of the electrostatic discharge short-circuit ring (20) further comprises a transparent conductive layer (25) for connecting the gate electrode (22) and the drain electrode (24), and the transparent conductive layer (25) is provided below the passivation layer (30).
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 15, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunfang Zhang, Yan Wei, Chao Xu, Heecheol Kim
  • Patent number: 10170711
    Abstract: A thin-film transistor layer, an organic light-emitting diode layer, and other layers may be used in forming an array of pixels on a substrate in a display. Vias may be formed through one or more layers of the display such as the substrate layer to form vertical signal paths. The vertical signal paths may convey signals between display driver circuitry underneath the display and the pixels. The vias may pass through a polymer layer and may contact pads formed within openings in the substrate. Vias may pass through a glass support layer. Metal traces may be formed in the thin-film transistor layer to create signal paths such as data lines and gate lines. Portions of the metal traces may form vias through a polymer layer such as a substrate layer or a polymer layer that has been formed on top of the substrate layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 1, 2019
    Assignee: Apple Inc.
    Inventors: Jason C. Sauers, Jean-Pierre S. Guillou, Peter J. Kardassakis, Shaowei Qin, Yi Tao
  • Patent number: 10164071
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10153379
    Abstract: The present invention provides a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor according to the present invention is such that by forming a first photoresist layer on an active layer and using a mask associated with the active layer to pattern the first photoresist layer so as to form the first photoresist pattern, the first photoresist pattern so formed provides protection of the active layer against corrosion caused by acidic etchant solution in the subsequently conducted etching operation of source and drain electrodes so as to function as an etching stopper layer and further, a major portion of the first photoresist pattern can be removed in a photolithographic process of the source and drain electrodes so that only a minor portion is left in the finally-formed thin-film transistor and does not affect the properties of the thin-film transistor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 11, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhe Chen
  • Patent number: 10150230
    Abstract: A method for drying a thin film stack having a thin film located on a substrate is disclosed. The thin film stack is conveyed past a flashlamp during which the thin film stack is irradiated with a composite light pulse from the flashlamp. The composite light pulse is composed of multiple micropulses. The time duration of the composite light pulse is shorter than a total thermal equilibration time of the thin film stack. In addition, when the thin film stack is being conveyed past the flashlamp, the thin film stack should move less than 10% of the length of the irradiating area in the conveyance direction during the delivery of the composite light pulse.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: December 11, 2018
    Assignee: NCC NANO, LLC
    Inventors: Kurt A. Schroder, Ian M. Rawson, Steven C. McCool, Andrew E. Edd, Ronald I. Dass
  • Patent number: 10141444
    Abstract: An oxide thin-film transistor, an array substrate and methods for manufacturing the same, and a display device are provided. The method for manufacturing the oxide thin-film transistor includes: forming a pattern of an oxide semi-conductor layer above a base substrate; and illuminating, by a light source, two opposite boundary regions of the pattern of the oxide semi-conductor layer, where the illuminated two opposite boundary regions of the pattern of the oxide semi-conductor layer form ohmic contact layers and a region of the pattern of the oxide semi-conductor layer that is not illuminated forms a semi-conductor active layer; forming a source electrode and a drain electrode which are connected to the semi-conductor active layer via the ohmic contact layers respectively.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ke Wang, Ce Ning
  • Patent number: 10109647
    Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 23, 2018
    Assignee: CBRITE INC.
    Inventors: Gang Yu, Chan-Long Shieh, Juergen Musolf, Fatt Foong, Tian Xiao
  • Patent number: 10095070
    Abstract: A pixel electrode or a common electrode is a light-transmissive conductive film; therefore, it is formed of ITO conventionally. Accordingly, the number of manufacturing steps and masks, and manufacturing cost have been increased. An object of the present invention is to provide a semiconductor device, a liquid crystal display device, and an electronic appliance each having a wide viewing angle, less numbers of manufacturing steps and masks, and low manufacturing cost compared with a conventional device. A semiconductor layer of a transistor, a pixel electrode, and a common electrode of a liquid crystal element are formed in the same step.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10068827
    Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Max L. Lifson, James A. Slinkman, Theodore G. Van Kessel, Randy L. Wolf
  • Patent number: 10062711
    Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Shank, Alvin Joseph, Michel Abou-Khalil, Michael Zierak
  • Patent number: 10043991
    Abstract: An array substrate and a manufacturing method thereof are provided. The method comprises steps of: forming a first metal layer, a gate insulation layer, a second metal layer, and a barrier layer; and patterning the barrier layer to form a gap portion by etching a portion of the barrier layer corresponding to a channel location. The width of one side of the gap portion close to the second metal layer is greater than that of the other side of the gap portion far away from the second metal layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 7, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhe Liu
  • Patent number: 10029919
    Abstract: Present disclosure provides a multicrystalline silicon (mc-Si) brick, including a bottom portion starting from a bottom to a height of 100 mm, a middle portion starting from the height of 100 mm to a height of 200 mm; and a top portion starting from the height of 200 mm to a top. A percentage of incoherent grain boundary in the bottom portion is greater than a percentage of incoherent grain boundary in the top portion. Present disclosure also provides a multicrystalline silicon (mc-Si) wafer. The mc-Si wafer includes a percentage of non-? grain boundary from about 60 to about 75 and a percentage of ?3 grain boundary from about 12 to about 25.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 24, 2018
    Assignee: SINO-AMERICAN SILICON PRODUCTS INC.
    Inventors: Hung-Sheng Chou, Yu-Min Yang, Wen-Huai Yu, Sung Lin Hsu, Wen-Ching Hsu, Chung-Wen Lan, Yu-Ting Wong
  • Patent number: 10026564
    Abstract: This invention discloses a preparation method for precious metal switching contact components by means of plating masking, plating and etching processes. The plating masking process is performed by using a plating mask ink with or without a photo exposure machine. Plating of precious metals is performed by electroless plating or electro plating methods. Etching is carried out with etching solutions containing weak organic acids, weak inorganic acids or acidic buffering agents. Improvement of the etched surface gloss and prevention of the side etching are realized with the sulfur-contained compounds. The dust- and oil stain-resistances of the switch contacts are improved by increasing the etching depth. The switch contacts made by this invention are featured with the advantages of good reliability, good resistance to dust and oil stain, short contact bounce time, long service life, low cost of raw materials and so on.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: July 17, 2018
    Assignee: NANTONG MEMTECH TECHNOLOGY CO., LTD.
    Inventors: Huisheng Han, Hongmei Zhang, Yang Ding, Zhihong Dong, Cheng Huang
  • Patent number: 9997634
    Abstract: The invention provides a TFT backplane structure and manufacturing method thereof. The TFT backplane structure uses the three-layered structure, from bottom up, dielectric layer (41), SiNx layer (42), and SiO2 layer (43), for the gate insulating layer (4) corresponding to the location of the TFT (T), to enhance the TFT reliability; uses a double-layered gate insulating layer (4), from bottom up, the dielectric layer (41), and at least a portion of SiNx layer (42), at the location corresponding to the storage capacitor (C), or a single-layered gate insulating layer (4), i.e., the dielectric layer (4), at the location corresponding to the storage capacitor (C), the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: June 12, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xingyu Zhou
  • Patent number: 9991290
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 5, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hideto Ohnuma, Hideaki Kuwabara
  • Patent number: 9983265
    Abstract: Provided is a device capable of generating a new test pattern after the design stage with the area of a circuit that is not in use during normal operation reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and operating as part of the first circuit. The fourth circuits have a function of storing first data and second data. The fifth circuit has a function of writing the first data to the fourth circuits, writing the second data to the fourth circuits, and reading the second data from the fourth circuits. The first data is used to control the conduction between the third circuits. The second data is used for processing in the first circuit.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9972666
    Abstract: A display device includes a pixel electrode, a pixel isolation insulating film in which an opening through which the pixel electrode is exposed at a bottom is formed, and a light-emitting layer formed inside the opening. The pixel isolation insulating film contains particles that receive light emitted from the light-emitting layer and propagate light in a direction different from that of the light emitted from the light-emitting layer.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 15, 2018
    Assignee: Japan Display Inc.
    Inventors: Hironori Toyoda, Toshihiro Sato
  • Patent number: 9966436
    Abstract: A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Xiaomeng Chen, Chien-Hong Chen, Shih-Chang Liu, Zhiqiang Wu
  • Patent number: 9958719
    Abstract: According to one embodiment, a display device includes an insulating substrate, a first insulating film, a second insulating film, a third insulating film, a fourth insulating film, a fifth insulating film, a sixth insulating film, a color filter layer, a semiconductor layer disposed between the second insulating film and the third insulating film, and a gate electrode disposed between the third insulating film and the fourth insulating film, wherein the first, fourth, and sixth insulating films are formed of a silicon nitride, and the second, third, and fifth insulating films are formed of a silicon oxide.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 1, 2018
    Assignee: Japan Display Inc.
    Inventors: Yuki Matsuura, Osamu Itou
  • Patent number: 9947697
    Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 17, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping Long, Yinan Liang, Zheng Liu, Zuqiang Wang, Xueyan Tian
  • Patent number: 9941416
    Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Gregory Bidal
  • Patent number: 9925146
    Abstract: A thermoformed pharmaceutical dosage form having a breaking strength of at least 300 N, said dosage form comprising a pharmacologically active ingredient (A), a free physiologically acceptable acid (B) in an amount of from 0.001 wt.-% to 5.0 wt.-%, based on the total weight of the pharmaceutical dosage form, and a polyalkylene oxide (C) having a weight average molecular weight Mw of at least 200,000 g/mol.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: March 27, 2018
    Assignee: GR√úNENTHAL GMBH
    Inventors: Lutz Barnscheid, Eric Galia, Sebastian Schwier, Ulrike Bertram, Anja Geissler, Kornelia Griessmann, Johannes Bartholomäus
  • Patent number: 9929341
    Abstract: A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed around the first gate insulating film, gate lines connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance f
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 27, 2018
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9911854
    Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the source and drain conductors; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein at least one of the source and drain conductors comprises a multilayer structure in at least one region thereof, the multilayer structure comprising a lower layer and an upper layer, the material of the lower layer being better than the material of the upper layer at injecting charge into the semiconductor material; and the material of the upper layer exhibiting better electrical conductivity than the material of the lower layer.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 6, 2018
    Assignee: FLEXENABLE LIMITED
    Inventors: Jon Jongman, Brian Asplin
  • Patent number: 9905755
    Abstract: A semiconductor device includes first pillar-shaped silicon layers, a first gate insulating film formed around the first pillar-shaped silicon layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped silicon layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped silicon layers, diffusion layers formed in lower portions of the first pillar-shaped silicon layers, and variable-resistance memory elements formed on the second contacts.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: February 27, 2018
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura