On Insulating Substrate Or Layer (e.g., Tft, Etc.) Patents (Class 438/149)
  • Patent number: 10727442
    Abstract: An organic light-emitting display apparatus includes: a substrate; first electrodes arranged on the substrate at separate positions; a second electrode disposed on the first electrodes to face the first electrodes; an intermediate layer disposed between the first electrodes and the second electrode and including an emission layer; a first encapsulating layer disposed on the second electrode and patterned to have a plurality of islands, the first encapsulating layer including an organic material; and a second encapsulating layer covering the islands of the first encapsulating layer and including an inorganic material.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seongmin Wang, Taekyung Kim, Ohjune Kwon, Mugyeom Kim, Yoonhyeung Cho
  • Patent number: 10714485
    Abstract: A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
  • Patent number: 10690853
    Abstract: A III-V optoelectronic light emitting device is epitaxially formed on a semiconductor on insulator substrate over a buried waveguide core. The device is optically coupled to the underlying waveguide core. A MOSFET device is formed on a semiconductor substrate beneath the insulator that contains the waveguide core.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana, Christopher Heidelberger
  • Patent number: 10651312
    Abstract: A flexible thin film transistor and a method for fabricating the same are provided. The flexible thin film transistor has: a flexible substrate; an inorganic insulating layer disposed on the flexible substrate; and a thin film transistor disposed on the inorganic insulating layer. A rough structure is formed on a side surface of the inorganic insulating layer facing toward the thin film transistor.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 12, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiang Liu
  • Patent number: 10644024
    Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Inventor: Chen-Chih Wang
  • Patent number: 10629438
    Abstract: The laser doping apparatus may irradiate a predetermined region of a semiconductor material with a pulse laser beam to perform doping. The laser doping apparatus may include: a solution supplying system configured to supply dopant-containing solution to the predetermined region, and a laser system including at least one laser device configured to output the pulse laser beam to be transmitted by the dopant-containing solution, and a time-domain pulse waveform changing apparatus configured to control a time-domain pulse waveform of the pulse laser beam.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 21, 2020
    Assignees: Kyushu University, Gigaphoton Inc.
    Inventors: Tomoyuki Ohkubo, Hiroshi Ikenoue, Akihiro Ikeda, Tanemasa Asano, Osamu Wakabayashi
  • Patent number: 10622428
    Abstract: Disclosed are a backplane substrate that is capable of expressing high gradation even through a small pixel, a method of manufacturing the same, and an organic light-emitting display device using the same. Integration for ultra-high resolution is possible through structural modification.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 14, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Kum-Mi Oh, Shun-Young Yang, Min-Seong Yun
  • Patent number: 10615184
    Abstract: An array substrate includes a plurality of pixel units arranged in an array. Each of the pixel units includes a common electrode, a first insulation layer, a sub pixel electrode, a second insulation layer, and a conductor plate that are sequentially stacked. The conductor plate is electrically connected to the common electrode. The common electrode and the sub pixel electrode collectively form therebetween a first confronting area and the conductor plate and the sub pixel electrode collectively form therebetween a second confronting area, such that a storage capacitor is formed, collectively, between the common electrode and the sub pixel electrode and between the conductor plate and the sub pixel electrode. The above-described array substrate provides a relatively large storage capacitor. Also disclosed is a display panel.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 7, 2020
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Liyang An
  • Patent number: 10608094
    Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: March 31, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Tsun Tsai, I-Chih Chen, Chih-Mu Huang, Jiun-Jie Huang, Jen-Pan Wang
  • Patent number: 10600919
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first oxide layer disposed over the substrate, a second oxide layer, and a semiconductor layer disposed over the second oxide layer. The second oxide layer is disposed at one side of the first oxide layer and is in contact with the first oxide layer. The second oxide layer partially overlaps the first oxide layer, and the first oxide layer and the second oxide layer include the same oxide.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 24, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Lin, Chia-Hao Lee
  • Patent number: 10593708
    Abstract: An array substrate, a driving method thereof and a display device are provided. The array substrate includes a base substrate, a pixel electrode located on the base substrate; a first gate line and a second gate line located on the base substrate at both sides of the pixel electrode, respectively, the pixel electrode being partially overlapped with the first gate line and the second gate line respectively to form a first storage capacitor and a second storage capacitor respectively; and a gate driver connected with the first gate line and the second gate line and configured to sequentially provide a gate signal to the first gate line and the second gate line and perform a waveform chamfering operation to the gate signal.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: March 17, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tao Hou, Junping Bao, Xinghua Li
  • Patent number: 10576268
    Abstract: Aspects include high resolution brain-electronic interfaces and related methods. Aspects include forming a semiconductor circuit on a substrate, depositing a tensile stress layer on the circuit, and separating the semiconductor circuit from a portion of the silicon substrate. Aspects also include removing the tensile stress layer from the semiconductor circuit and transferring the semiconductor circuit to a biocompatible film.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Hariklia Deligianni, Fei Liu
  • Patent number: 10573830
    Abstract: A flexible display panel has an active region and a peripheral region surrounding the active region. The flexible display panel includes a barrier layer, a flexible layer, a display device array and a driving IC. The barrier layer has a first opening. The flexible layer is disposed on the barrier layer, and filled into the first opening of the barrier layer. The display device array is disposed on the flexible layer and located in the active region. The driving IC is disposed on the flexible layer, electrically connected to the display device array and corresponding to the first opening of the barrier layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: February 25, 2020
    Assignee: AU OPTRONICS CORP.
    Inventors: Po-Yang Lin, Tsung-Ying Ke
  • Patent number: 10566393
    Abstract: A transparent organic light emitting diode display is disclosed. The transparent organic light emitting diode display includes a substrate, a pixel disposed on the substrate, the pixel including a light-transmitting area and a light-emitting area, an organic light emitting diode disposed in the light-emitting area of the substrate, an encapsulation substrate that is bonded face to face opposite the substrate, a color filter disposed in the encapsulation substrate corresponding to the light-emitting area, and a color compensation layer disposed in the encapsulation substrate corresponding to the light-transmitting area.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 18, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Seokwon Ji, Jongmoo Kim
  • Patent number: 10546922
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
  • Patent number: 10515864
    Abstract: The present invention provides a glass substrate in which in a step of sticking a glass substrate and a silicon-containing substrate to each other, bubbles hardly intrude therebetween. The present invention relates to a glass substrate for forming a laminated substrate by lamination with a silicon-containing substrate, having a warpage of 2 ?m to 300 ?m, and an inclination angle due to the warpage of 0.0004° to 0.12°.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 24, 2019
    Assignee: AGC Inc.
    Inventors: Yu Hanawa, Shigeki Sawamura, Shuhei Nomura, Kazutaka Ono, Nobuhiko Takeshita, Keisuke Hanashima
  • Patent number: 10509250
    Abstract: A cholesteric liquid crystal writing board comprises a cholesteric liquid crystal device, a photo-sensing array layer and a mode control unit. The photo-sensing array layer is disposed at one side of the light-emitting surface of the cholesteric liquid crystal device. The photo-sensing array layer comprises a plurality of gate control lines and a plurality of mode control lines. The mode control unit comprises a main control circuitry and a plurality of mode switches coupled to the main control circuitry. Each mode switch is coupled to one of the mode control lines correspondingly. The gate control lines intersect with the mode control lines so as to define a plurality of light sensing areas arranged in an array. Each light sensing area has a switch element and a light-sensing element. The main control circuitry controls each mode switch to be switched between a voltage output mode and a voltage write mode.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 17, 2019
    Assignee: IRIS OPTRONICS CO., LTD.
    Inventors: Chi-Chang Liao, Shu-Shien Liu, Tsung-Ming Pai, Fu-Ming Wang
  • Patent number: 10510460
    Abstract: A method of manufacturing a laminate, transistor, and method of manufacturing transistor using a composition that includes an organic compound having a hydroxy group; a first cross-linking agent that is at least one organic silicon compound selected from the group including an organic silicon compound including a siloxane bond in the molecule and having three or more cyclic ether groups in the molecule, a chain organic silicon compound including two or more siloxane bonds in the molecule and having two or more cyclic ether groups in the molecule, a cyclic organic silicon compound including D unit in the molecule and having four or more cyclic ether groups bonded to a silicon atom of the D unit in the molecule, and a cyclic organic silicon compound including a T unit in the molecule and having two or more cyclic ether groups in the molecule; and a photocationic polymerization initiator.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 17, 2019
    Assignee: NIKON CORPORATION
    Inventors: Shohei Koizumi, Takashi Sugizaki, Kenji Miyamoto, Yusuke Kawakami
  • Patent number: 10505019
    Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10497724
    Abstract: The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 3, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhichao Zhou, Hui Xia, Meng Chen
  • Patent number: 10483308
    Abstract: A semiconductor package includes: a sheet-like thin plate on which a semiconductor chip is secured; and a substrate including a wiring layer, disposed on the thin plate to extend over a part of a region surrounding the region where the semiconductor chip is secured or over the entire surrounding region, wherein the semiconductor chip and the substrate are electrically connected.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 19, 2019
    Assignee: SONY CORPORATION
    Inventor: Masayuki Ishikida
  • Patent number: 10461199
    Abstract: The present disclosure discloses a manufacturing method of a thin film transistor, including: forming a gate layer on a substrate; forming a gate insulating layer on the gate layer and the substrate; forming an active layer on the gate insulating layer; and simultaneously forming a source and a drain formed on the active layer by a combination of a chemical plating method and a lift-off method. In the present disclosure, the chemical plating method is combined with the lift-off method, so that the wet-etching method is not used for forming the source and the drain, and thus the IGZO at the channel is not required to be protected by the etching-stop-layer. Therefore, while simplifying the production process, but also can reduce costs.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 29, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Hui Xia, Zhiwei Tan, Shu Jhih Chen
  • Patent number: 10460684
    Abstract: The disclosure, which relates to a display device is created so that it can be integrated in a surface, providing in particular a seamless extension and an integrated appearance between the surface surrounding the display device and the display device itself and thus appears to the viewer of the display device as being part of a surface.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 29, 2019
    Assignee: Visteon Global Technologies, INC.
    Inventors: Alexander Van Laack, Ruddy Cittadini, Frederik Belzl
  • Patent number: 10417982
    Abstract: The disclosure, which relates to a display device is created so that it can be integrated in a surface, providing in particular a seamless extension and an integrated appearance between the surface surrounding the display device and the display device itself and thus appears to the viewer of the display device as being part of a surface.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 17, 2019
    Assignee: Visteon Global Technologies, INC.
    Inventors: Alexander Van Laack, Ruddy Cittadini, Frederik Belzl
  • Patent number: 10411189
    Abstract: The invention provides a display panel and a manufacturing method thereof, and a display device, belongs to the field of display device manufacturing technology, which can solve the following problem in the existing display device: when light transmits the cathode layer which is thin, has high resistance and thus poor conductivity, the display effect is nonuniform. The display panel of the invention comprises a first substrate and a second substrate which are assembled, wherein the second substrate is provided with an organic electroluminescent device thereon, an anode layer of the organic electroluminescent device is away from the first substrate and an cathode layer thereof is close to the first substrate; and the cathode layer is electrically connected to an auxiliary electrode on a light entering surface of the first substrate through a plurality of conductive spacers spaced at certain intervals, wherein the cathode layer is a transparent electrode layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangyong Kong, Dongfang Wang
  • Patent number: 10411695
    Abstract: The field effect transistor (FET) of the present subject matter comprises a bottom gate electrode, a bottom gate dielectric provided on the bottom gate electrode, a channel layer provided on the bottom gate dielectric. A top portion comprising a source electrode, a drain electrode, a top gate electrode provided, and a top dielectric layer is provided on the channel layer. The channel layer forms Schottky barriers at points of contact with the source and the drain electrode. A back-gate voltage varies a height and a top-gate voltage varies a width of the Schottky barrier. The FET can be programmed to work in two operating modes-tunnelling (providing low power consumption) and thermionic mode (providing high performance). The FET can also be programmed to combine the tunnelling and thermionic mode in a single operating cycle, yielding high performance with low power consumption.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 10, 2019
    Assignee: Indian Institute of Science
    Inventors: Shubhadeep Bhattacharjee, Kolla Lakshmi Ganapathi, Sangeneni Mohan, Navakanta Bhat
  • Patent number: 10403759
    Abstract: Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other. The logic circuit of the invention is configured such that dual-gate thin-film transistors are three-dimensionally stacked, whereby the advantages of the dual-gate structure and of thin-film transistors can be exhibited together and the degree of integration can be drastically increased, and a logic gate is made in the area of a single transistor, thereby remarkably simplifying wire and circuit designs.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 3, 2019
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Sungjune Jung, Jimin Kwon
  • Patent number: 10392725
    Abstract: A method for depositing silicon feedstock material may include introducing a first gas including silicon into a reactor chamber and introducing a second gas including at least one of gallium or indium into the reactor chamber and depositing silicon doped with at least one of gallium or indium onto a surface within the reactor chamber. Doped silicon feedstock material may be obtained by the method may be used for obtaining a silicon wafer, a solar cell, and/or a PV module.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 27, 2019
    Inventor: Frank Asbeck
  • Patent number: 10388799
    Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki
  • Patent number: 10368434
    Abstract: Provided is a display device and a manufacturing method of the same. The display device includes: a base substrate having a top surface and a side surface, a display region over the top surface, a terminal over the top surface and between the display region and the side surface, the terminal being electrically connected to the display region, and an anisotropic conductive film over the terminal. An edge portion of the anisotropic conductive film is spaced from the side surface, and its distance is equal to or larger than 10 ?m and equal to or smaller than 1 mm.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 30, 2019
    Assignee: Japan Display Inc.
    Inventor: Takuya Nakagawa
  • Patent number: 10361260
    Abstract: A semiconductor device includes a base substrate, a first transistor including a first semiconductor pattern, a first control electrode, a first input electrode, and a first output electrode, each of which is disposed on the base substrate, a second transistor including a second semiconductor pattern, a second control electrode, a second input electrode, and a second output electrode, and a plurality of insulating layers. A single first through part exposes the first control electrode and the first semiconductor pattern disposed on both sides of the first control electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaybum Kim, Kyoungseok Son, Jihun Lim, Eoksu Kim, Junhyung Lim
  • Patent number: 10354869
    Abstract: A method of manufacturing a nanostructure includes: heating a mixed solution to a first temperature, the mixed solution including a solvent, a compound including indium, and an octadecylphosphonic acid; heating the mixed solution to a second temperature; injecting, after heating the mixed solution to the second temperature, a phosphine precursor into the mixed solution; and heating the mixed solution including the injected phosphine precursor to a third temperature.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 16, 2019
    Assignees: Samsung Display Co., Ltd., POSTECH Academy-Industry Foundation
    Inventors: Dae Hyun Kim, Jong Hyuk Kang, Hyun Deok Im, Hyun Min Cho, Yongju Kwon, Bomi Kim, Sung-Jee Kim, Mihye Lim
  • Patent number: 10326008
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10312312
    Abstract: Provided is a display device. A poly-Si layer is disposed on a substrate. A first metal layer is disposed on the poly-Si layer, and a metal oxide layer is disposed on the first metal layer. A second metal layer is disposed on the metal oxide layer. The first metal layer is overlapped with the second metal layer. The first metal layer and the second metal layer may be gate lines connected to different TFTs.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 4, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Eui Tae Kim, Bu Yeol Lee
  • Patent number: 10304942
    Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jyun-Ming Lin, Hua Feng Chen, Kuo-Hua Pan, Min-Yann Hsieh, C. H. Wu
  • Patent number: 10297635
    Abstract: A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3?), a semiconductor-layer thin film (4?) and a passivation-shielding-layer thin film (5?) successively; forming a pattern (5?) that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a?); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c?) and a drain electrode (4b?). The source electrode (4c?) and the drain electrode (4b?) are disposed on two sides of the active layer (4a?) respectively and in a same layer as the active layer (4a?).
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 21, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Huichao Gao, Zongmin Tian, Peng Li
  • Patent number: 10290717
    Abstract: The thin film transistor (TFT) contains a gate electrode metallic layer above a substrate, a gate insulator layer covering the substrate and the gate electrode metallic layer, a first source electrode metallic layer and a first drain electrode metallic layer above the gate insulator layer and separated by a gap, an active layer above the first source and first drain electrode metallic layers filling the gap and forming a ditch in the active layer above the gap, and a second source electrode metallic layer and a second drain electrode metallic layer above the active layer at two lateral sides of the ditch, respectively. The second source/drain electrode metallic layer contacts the first source/drain electrode metallic layer. The TFT has lower parasitic capacitance and takes up less area. As such, when the TFT is applied to a LCD, the reduced space consumed by the TFT enhances pixel's aperture ratio.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 14, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Tuo Feng
  • Patent number: 10290666
    Abstract: The present disclosure relates to a thin film transistor (TFT) array substrate and a manufacturing method thereof. The manufacturing method includes adopting a shading metal layer to form the bottom gate electrode, depositing a buffer layer on the substrate having the bottom gate electrode, applying a patterned process on the buffer layer to reduce the thickness of the buffer layer on the bottom gate electrode, applying the patterned process on the semiconductor layer to form the semiconductor pattern corresponding to the bottom gate electrode within the thin area of the buffer layer. The present disclosure may reduce a thickness of the buffer layer corresponding to the bottom gate electrode, so as to improve the whole performance of the array substrate caused by the bottom gate electrode.
    Type: Grant
    Filed: May 27, 2017
    Date of Patent: May 14, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd
    Inventors: Mian Zeng, Xiaodi Liu
  • Patent number: 10283610
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 7, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Patent number: 10283628
    Abstract: A thin film transistor and manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes a source electrode, a drain electrode and an active layer; the source electrode, the drain electrode and the active layer are disposed in a same layer, the source electrode and the drain electrode are separately joined to the active layer through their respective side faces, a material of the source electrode and the drain electrode is metal, and a material of the active layer is a metal oxide semiconductor in correspondence with material of the source electrode and the drain electrode. With the thin film transistor, procedures can be decreased, thereby reducing costs.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 7, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Botao Song, Liang Lin, Zhixiang Zou, Yinhu Huang
  • Patent number: 10269973
    Abstract: A TFT backplane structure includes a gate insulating layer that includes a three-layered portion, which includes, from bottom up, a dielectric layer, a SiNx layer, and a SiO2 layer, set at a location corresponding to a TFT in order to enhance the TFT reliability, and also includes a double-layered portion, which includes from bottom up, the dielectric layer and at least a portion of the SiNx layer, set at a location corresponding to a storage capacitor, or alternatively a single-layered structure that includes only the dielectric layer set at the location corresponding to the storage capacitor so that the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 23, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xingyu Zhou
  • Patent number: 10263089
    Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: April 16, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
  • Patent number: 10254609
    Abstract: An array substrate and a method of manufacturing the same, a display panel and a display device are provided. The array substrate includes a thin film transistor and a pixel electrode. An insulating layer is formed between a drain electrode of the thin film transistor and the pixel electrode. The drain electrode is in direct electrical contact with the pixel electrode through a via-hole in the insulating layer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 9, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shoukun Wang, Huibin Guo, Yuchun Feng, Liangliang Li
  • Patent number: 10249735
    Abstract: The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jian Min, Xiaolong Li, Zhengyin Xu, Ping Song, Youwei Wang
  • Patent number: 10249540
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • Patent number: 10244628
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 26, 2019
    Assignees: THE TRUSTEES OF PRINCETON UNIVERSITY, VORBECK MATERIALS CORPORATION
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'homme
  • Patent number: 10243016
    Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Mark Lamorey
  • Patent number: 10236280
    Abstract: A light emitting device package is provided. The light emitting device package includes three light emitting diode (LED) chips configured to emit light having different wavelengths, each of the three LED chips including a light emitting structure having a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; a through electrode portion disposed adjacent to the three LED chips; a molding portion encapsulating respective side surfaces of the three LED chips and the through electrode portion; a transparent electrode layer disposed on a first surface of the molding portion, the three LED chips, and the through electrode portion; and three individual electrodes exposed through a second surface of the molding portion and disposed on the three LED chips, respectively.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Min Kwon, Kyoung Jun Kim
  • Patent number: 10228231
    Abstract: In one aspect the invention provides a laminated device of flexible and compliant layers of material, such as used to provide a dielectric elastomer sensor. A flexible and compliant layer of material is affixed to a substrate to avoid strain during processing is bonded to another layer of flexible and compliant material and released from the substrate to form a laminate. The layer of flexible and compliant material affixed to the substrate may be inspected prior to bonding.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 12, 2019
    Assignee: Stretchsense Limited
    Inventors: Benjamin Marc O'Brien, Todd Alan Gisby, Antoni Edward Harbuz, Samuel Schlatter
  • Patent number: 10224326
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Balasubramanian S. Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre