On Insulating Substrate Or Layer (e.g., Tft, Etc.) Patents (Class 438/149)
  • Patent number: 11069725
    Abstract: A display substrate and a method of preparing the same, and a display device are provided, the method including: providing a substrate; forming a switching thin film transistor precursor and a driving thin film transistor precursor on the substrate, each including a semiconductor layer, a gate insulating material layer and a gate metallic layer stacked sequentially above the substrate; forming a photoresist layer above the switching thin film transistor precursor and the driving thin film transistor precursor, and forming an etching mask from the photoresist layer, a first portion of the etching mask at the switching thin film transistor precursor and a second portion of the etching mask at the driving thin film transistor precursor having different shapes; and forming a switching thin film transistor and a driving thin film transistor, by etching processing the switching thin film transistor precursor and the driving thin film transistor precursor with the etching mask.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: July 20, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jun Liu, Luke Ding, Ning Liu, Wei Li, Bin Zhou, Liangchen Yan
  • Patent number: 11069419
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Wei Cheng Wu, Ku-Ning Chang, Yu-Chen Wang
  • Patent number: 11069800
    Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 11049885
    Abstract: An array substrate and a manufacturing method thereof, a display panel, and a display device are disclosed. The array substrate includes a base substrate including a bending region; and an insulating layer disposed on the base substrate wherein the insulating layer located in the bending region is provided with at least one recess and a surface of the recess includes a concave-convex structure.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 29, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhen Zhang
  • Patent number: 11037855
    Abstract: A system-in-package apparatus includes a contoured heat sink that provides a first recess and a subsequent recess. The system-in-package apparatus includes a flexible printed wiring board that is wrapped onto the contoured heat sink after a manner to enclose the first semiconductive device into the first recess and a semiconductive device in the subsequent recess.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 15, 2021
    Assignee: Intel IP Corporation
    Inventors: Sonja Koller, Reinhard Mahnkopf
  • Patent number: 11031406
    Abstract: A semiconductor device includes a first transistor element having a first channel region and a second transistor element having a second channel region, wherein the first channel region includes a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration, and wherein the second channel region includes a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than the first germanium concentration.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 8, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Elliot John Smith, Gunter Grasshoff, Carsten Peters
  • Patent number: 11018112
    Abstract: A bonding method of a first member includes arranging an activated front surface of a first member and an activated front surface of a second member so as to face each other with a back surface of the first member attached to a sheet, pushing a back surface of the first member through the sheet to closely attach the activated front surface of the first member and the activated front surface of the second member, and stripping the sheet from the back surface of the first member while maintaining a state in which the activated front surface of the first member is closely attached to the activated front surface of the second member.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 25, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoichiro Kurita
  • Patent number: 10985273
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chun Wing Yeung, ChoongHyun Lee, Jingyun Zhang, Robin Hsin Kuo Chao, Heng Wu
  • Patent number: 10978531
    Abstract: A transparent display substrate, a manufacturing method thereof and a transparent display panel are provided. The transparent display substrate includes: a base substrate; a plurality of sub-pixels arranged on the substrate, wherein each of the plurality of sub-pixels comprising a light emitting region and a first transparent region, and the light emitting region being provided with an organic light emitting diode (OLED); a driving circuit, located in each of the plurality of sub-pixels and configured to drive the OLED to emit light, the driving circuit comprising a capacitor disposed in the first transparent region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 13, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 10971530
    Abstract: A manufacturing method for TFT array substrate and TFT array substrate are disclosed. After depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer in sequence after the active layer above the gate electrode is formed. A photoresist pattern is formed on the metal material layer. The photoresist pattern includes a first and second photoresist blocks with different thicknesses. The metal material layer and the electrode material layer are etched using the photoresist pattern to form a contact electrode and pixel electrodes connected with two ends of the active layer and the source/drain electrodes on the contact electrode. The process is simple and can effectively reduce the contact resistance between the source/drain and the active layer and improve the quality of the product.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: April 6, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Guanghui Liu, Peng He, Yong Xu, Fei Ai
  • Patent number: 10957723
    Abstract: To provide a semiconductor device in which a layer to be peeled is attached to a base having a curved surface, and a method of manufacturing the same, and more particularly, a display having a curved surface, and more specifically a light-emitting device having a light emitting element attached to a base with a curved surface. A layer to be peeled, which contains a light emitting element furnished to a substrate using a laminate of a first material layer which is a metallic layer or nitride layer, and a second material layer which is an oxide layer, is transferred onto a film, and then the film and the layer to be peeled are curved, to thereby produce a display having a curved surface.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 10957577
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 23, 2021
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 10950626
    Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Murshed Chowdhury, Raiden Matsuno
  • Patent number: 10937816
    Abstract: A switching element, a manufacturing method thereof, an array substrate and a display device are provided. The switching element includes: a base substrate; a first thin-film transistor (TFT), disposed on the base substrate; and a second TFT, disposed on the first TFT, wherein the first TFT includes a first electrode and a second electrode, and the first TFT and the second TFT share the first electrode and the second electrode.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 2, 2021
    Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Liqing Liao, Hongmin Li, Ying Wang, Dong Wang
  • Patent number: 10937822
    Abstract: A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 2, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mineo Shimotsusa, Masatsugu Itahashi, Yusuke Onuki, Nobuaki Kakinuma, Masato Fujita
  • Patent number: 10886499
    Abstract: A light emitting display apparatus includes a passivation layer on a thin film transistor, a light emitting diode on the passivation layer, the light emitting diode having an anode, a light emitting layer on the anode, and a cathode on the light emitting layer, and a hydrogen absorbing layer on the light emitting diode, the hydrogen absorbing layer including an inorganic material having a mass percentage of 0.08% to 50%.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 5, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Goeun Kim, YoungHoon Shin
  • Patent number: 10872807
    Abstract: A manufacturing method of a via hole, a display substrate and a manufacturing method thereof are provided. The manufacturing method of a via hole includes: forming a first via hole penetrating the passivation protection layer, the first via hole being defined by a first side wall of the passivation protection layer; forming an organic insulating layer on the passivation protection layer; and forming a second via hole penetrating the organic insulating layer, the second via hole being defined by a second side wall of the organic insulating layer; wherein in a sectional view, a bottom of the second via hole is located in the first via hole and is in direct contact with the conductive layer, and the second side wall of the organic insulating layer is separated from the first side wall of the passivation protection layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: December 22, 2020
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yunhai Wan, Chengshao Yang, Wenlong Wang, Ke Cao
  • Patent number: 10867864
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung, Da-Yuan Lee
  • Patent number: 10868046
    Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 10868266
    Abstract: A method for manufacturing a semiconductor thin film includes sequentially forming a first semiconductor layer, an intermediate layer, and a second semiconductor layer over a substrate. The first semiconductor layer and the second semiconductor layer can be one and another of an n-type semiconductor layer and a p-type semiconductor layer. At least one of the first semiconductor layer, the intermediate layer, or the second semiconductor layer is formed via a solution process. The n-type semiconductor layer can include indium oxide. The intermediate layer can include a self-assembly material. The p-type semiconductor layer can include a p-type organic semiconductor material, and can be pentacene. On the basis, a semiconductor thin film manufactured thereby, a semiconductor thin film transistor, and a display apparatus, are also disclosed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Liangchen Yan, Xiaoguang Xu, Lei Wang, Junbiao Peng, Linfeng Lan
  • Patent number: 10852337
    Abstract: Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 1, 2020
    Assignee: PDF Solutions, Inc.
    Inventors: Sharad Saxena, Tomasz Brozek, Yuan Yu, Mike Kyu Hyon Pak, Meindert Martin Lunenborg
  • Patent number: 10840335
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10818797
    Abstract: The present application provides a thin film transistor and a method of fabricating the same, an array substrate and a display device. The thin film transistor includes: a gate electrode; an active layer including a first portion made of polysilicon and a second portion made of amorphous silicon; a source electrode and a drain electrode; and an ohmic contact layer. The second portion of the active layer is in contact with the source electrode and the drain electrode through the ohmic contact layer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 27, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shengguang Ban, Zhanfeng Cao, Qi Yao, Dapeng Xue
  • Patent number: 10818688
    Abstract: A storage device includes: a plurality of electrode films stacked in a first direction, and extending in a second direction intersecting the first direction; a first semiconductor film provided adjacent to the plurality of electrode films, and extending in the first direction; a first charge holding film provided between one electrode film among the plurality of electrode films, and the semiconductor film, and including any one of a metal, a metal compound, and a high dielectric material; and a second semiconductor film located between the first semiconductor film and the charge holding film, and extending in the first direction along the first semiconductor film. The second semiconductor film is electrically insulated from the plurality of electrode films, the first charge holding film, and the first semiconductor film.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 27, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Murakoshi, Hiroki Sasaki
  • Patent number: 10790341
    Abstract: An array substrate, a fabrication method thereof, and an organic light-emitting diode display device are provided; the array substrate (10) comprises a base substrate (100), the base substrate (100) including a display region (102) and a peripheral region (101) surrounding the display region (102), the display region (102) including: a plurality of data lines (12) and a plurality of gate lines (11) intersecting with each other, a plurality of pixel regions (21), formed in a matrix and defined by the plurality of data lines (12) and the plurality of gate lines (11) intersecting with each other formed on the base substrate (100), wherein a thin film transistor (32) is formed in each of the plurality of pixel regions (21); and further, the array substrate (10) also comprises at least one solar cell unit (31), which, together with the thin film transistor (32), is located on a same side of the base substrate (100), and is formed in at least one of the plurality of pixel regions (21) and the peripheral region (101
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: September 29, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yidong Guo, Chunping Long
  • Patent number: 10777588
    Abstract: The present application provides a method of fabricating a thin film transistor. The method includes selecting a nano-structure material having a monotonic relationship between a threshold voltage and a channel length when the nano-structure material is formed as a channel part in a thin film transistor; forming an active layer using the nano-structure material; determining a nominal channel length of a channel part of the thin film transistor based on the monotonic relationship and a reference threshold voltage so that the thin film transistor is formed to have a nominal threshold voltage; and forming a source electrode and a drain electrode thereby forming the channel part in the active layer having the nominal channel length.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Hu Meng, Xuelei Liang, Jiye Xia, Boyuan Tian, Guodong Dong, Qi Huang
  • Patent number: 10770564
    Abstract: A MOS component includes a source area, a drain area, a body area, a channel area, and a gate element, the channel area and the gate element being electrically insulated with respect to one another by a total of at least three individual layers in the form of a first individual layer, a second individual layer, and a third individual layer. The second individual layer is designed in such a way that it may permanently store electric charges. The third individual layer, which is situated between the channel area and the second individual layer, has a greater equivalent oxide thickness than the first individual layer situated between the second individual layer and the gate element.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: September 8, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Joachim Joos, Walter von Emden
  • Patent number: 10763340
    Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee Mo, Brent A. Wacaser
  • Patent number: 10756117
    Abstract: An array substrate includes a display region and a peripheral circuit region surrounding the display region. The array substrate further includes: a base substrate; first TFTs arranged on a first surface of the base substrate and at the display region, and each first TFT including a first gate electrode, a first active layer and a first source-drain electrode; and second TFTs arranged on the first surface and at the peripheral circuit region, and each second TFT including a second gate electrode, a second active layer and a second source-drain electrode. The first active layer of each first TFT is made of a material different from, and arranged at a same layer as, the second active layer of each second TFT, and the first source-drain electrode is arranged at a same layer as the second source-drain electrode.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 25, 2020
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chao Wang, Shengwei Zhao, Huafeng Liu, Chunxiang Nan
  • Patent number: 10741692
    Abstract: The present disclosure provides a method for manufacturing an LTPS thin film transistor which includes: forming a light shielding pattern and an active layer of the LTPS thin film transistor on a base substrate through one single patterning process, in which an orthogonal projection of the active layer on the base substrate falls within an orthogonal projection of the light shielding pattern on the base substrate, and the light shielding pattern is made of a semiconductor material.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 11, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shengguang Ban, Zhanfeng Cao, Qi Yao, Dapeng Xue
  • Patent number: 10727442
    Abstract: An organic light-emitting display apparatus includes: a substrate; first electrodes arranged on the substrate at separate positions; a second electrode disposed on the first electrodes to face the first electrodes; an intermediate layer disposed between the first electrodes and the second electrode and including an emission layer; a first encapsulating layer disposed on the second electrode and patterned to have a plurality of islands, the first encapsulating layer including an organic material; and a second encapsulating layer covering the islands of the first encapsulating layer and including an inorganic material.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seongmin Wang, Taekyung Kim, Ohjune Kwon, Mugyeom Kim, Yoonhyeung Cho
  • Patent number: 10714485
    Abstract: A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
  • Patent number: 10690853
    Abstract: A III-V optoelectronic light emitting device is epitaxially formed on a semiconductor on insulator substrate over a buried waveguide core. The device is optically coupled to the underlying waveguide core. A MOSFET device is formed on a semiconductor substrate beneath the insulator that contains the waveguide core.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana, Christopher Heidelberger
  • Patent number: 10651312
    Abstract: A flexible thin film transistor and a method for fabricating the same are provided. The flexible thin film transistor has: a flexible substrate; an inorganic insulating layer disposed on the flexible substrate; and a thin film transistor disposed on the inorganic insulating layer. A rough structure is formed on a side surface of the inorganic insulating layer facing toward the thin film transistor.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 12, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiang Liu
  • Patent number: 10644024
    Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Inventor: Chen-Chih Wang
  • Patent number: 10629438
    Abstract: The laser doping apparatus may irradiate a predetermined region of a semiconductor material with a pulse laser beam to perform doping. The laser doping apparatus may include: a solution supplying system configured to supply dopant-containing solution to the predetermined region, and a laser system including at least one laser device configured to output the pulse laser beam to be transmitted by the dopant-containing solution, and a time-domain pulse waveform changing apparatus configured to control a time-domain pulse waveform of the pulse laser beam.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 21, 2020
    Assignees: Kyushu University, Gigaphoton Inc.
    Inventors: Tomoyuki Ohkubo, Hiroshi Ikenoue, Akihiro Ikeda, Tanemasa Asano, Osamu Wakabayashi
  • Patent number: 10622428
    Abstract: Disclosed are a backplane substrate that is capable of expressing high gradation even through a small pixel, a method of manufacturing the same, and an organic light-emitting display device using the same. Integration for ultra-high resolution is possible through structural modification.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 14, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Kum-Mi Oh, Shun-Young Yang, Min-Seong Yun
  • Patent number: 10615184
    Abstract: An array substrate includes a plurality of pixel units arranged in an array. Each of the pixel units includes a common electrode, a first insulation layer, a sub pixel electrode, a second insulation layer, and a conductor plate that are sequentially stacked. The conductor plate is electrically connected to the common electrode. The common electrode and the sub pixel electrode collectively form therebetween a first confronting area and the conductor plate and the sub pixel electrode collectively form therebetween a second confronting area, such that a storage capacitor is formed, collectively, between the common electrode and the sub pixel electrode and between the conductor plate and the sub pixel electrode. The above-described array substrate provides a relatively large storage capacitor. Also disclosed is a display panel.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 7, 2020
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Liyang An
  • Patent number: 10608094
    Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: March 31, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Tsun Tsai, I-Chih Chen, Chih-Mu Huang, Jiun-Jie Huang, Jen-Pan Wang
  • Patent number: 10600919
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first oxide layer disposed over the substrate, a second oxide layer, and a semiconductor layer disposed over the second oxide layer. The second oxide layer is disposed at one side of the first oxide layer and is in contact with the first oxide layer. The second oxide layer partially overlaps the first oxide layer, and the first oxide layer and the second oxide layer include the same oxide.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 24, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Lin, Chia-Hao Lee
  • Patent number: 10593708
    Abstract: An array substrate, a driving method thereof and a display device are provided. The array substrate includes a base substrate, a pixel electrode located on the base substrate; a first gate line and a second gate line located on the base substrate at both sides of the pixel electrode, respectively, the pixel electrode being partially overlapped with the first gate line and the second gate line respectively to form a first storage capacitor and a second storage capacitor respectively; and a gate driver connected with the first gate line and the second gate line and configured to sequentially provide a gate signal to the first gate line and the second gate line and perform a waveform chamfering operation to the gate signal.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: March 17, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tao Hou, Junping Bao, Xinghua Li
  • Patent number: 10576268
    Abstract: Aspects include high resolution brain-electronic interfaces and related methods. Aspects include forming a semiconductor circuit on a substrate, depositing a tensile stress layer on the circuit, and separating the semiconductor circuit from a portion of the silicon substrate. Aspects also include removing the tensile stress layer from the semiconductor circuit and transferring the semiconductor circuit to a biocompatible film.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Hariklia Deligianni, Fei Liu
  • Patent number: 10573830
    Abstract: A flexible display panel has an active region and a peripheral region surrounding the active region. The flexible display panel includes a barrier layer, a flexible layer, a display device array and a driving IC. The barrier layer has a first opening. The flexible layer is disposed on the barrier layer, and filled into the first opening of the barrier layer. The display device array is disposed on the flexible layer and located in the active region. The driving IC is disposed on the flexible layer, electrically connected to the display device array and corresponding to the first opening of the barrier layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: February 25, 2020
    Assignee: AU OPTRONICS CORP.
    Inventors: Po-Yang Lin, Tsung-Ying Ke
  • Patent number: 10566393
    Abstract: A transparent organic light emitting diode display is disclosed. The transparent organic light emitting diode display includes a substrate, a pixel disposed on the substrate, the pixel including a light-transmitting area and a light-emitting area, an organic light emitting diode disposed in the light-emitting area of the substrate, an encapsulation substrate that is bonded face to face opposite the substrate, a color filter disposed in the encapsulation substrate corresponding to the light-emitting area, and a color compensation layer disposed in the encapsulation substrate corresponding to the light-transmitting area.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 18, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Seokwon Ji, Jongmoo Kim
  • Patent number: 10546922
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
  • Patent number: 10515864
    Abstract: The present invention provides a glass substrate in which in a step of sticking a glass substrate and a silicon-containing substrate to each other, bubbles hardly intrude therebetween. The present invention relates to a glass substrate for forming a laminated substrate by lamination with a silicon-containing substrate, having a warpage of 2 ?m to 300 ?m, and an inclination angle due to the warpage of 0.0004° to 0.12°.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 24, 2019
    Assignee: AGC Inc.
    Inventors: Yu Hanawa, Shigeki Sawamura, Shuhei Nomura, Kazutaka Ono, Nobuhiko Takeshita, Keisuke Hanashima
  • Patent number: 10510460
    Abstract: A method of manufacturing a laminate, transistor, and method of manufacturing transistor using a composition that includes an organic compound having a hydroxy group; a first cross-linking agent that is at least one organic silicon compound selected from the group including an organic silicon compound including a siloxane bond in the molecule and having three or more cyclic ether groups in the molecule, a chain organic silicon compound including two or more siloxane bonds in the molecule and having two or more cyclic ether groups in the molecule, a cyclic organic silicon compound including D unit in the molecule and having four or more cyclic ether groups bonded to a silicon atom of the D unit in the molecule, and a cyclic organic silicon compound including a T unit in the molecule and having two or more cyclic ether groups in the molecule; and a photocationic polymerization initiator.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 17, 2019
    Assignee: NIKON CORPORATION
    Inventors: Shohei Koizumi, Takashi Sugizaki, Kenji Miyamoto, Yusuke Kawakami
  • Patent number: 10509250
    Abstract: A cholesteric liquid crystal writing board comprises a cholesteric liquid crystal device, a photo-sensing array layer and a mode control unit. The photo-sensing array layer is disposed at one side of the light-emitting surface of the cholesteric liquid crystal device. The photo-sensing array layer comprises a plurality of gate control lines and a plurality of mode control lines. The mode control unit comprises a main control circuitry and a plurality of mode switches coupled to the main control circuitry. Each mode switch is coupled to one of the mode control lines correspondingly. The gate control lines intersect with the mode control lines so as to define a plurality of light sensing areas arranged in an array. Each light sensing area has a switch element and a light-sensing element. The main control circuitry controls each mode switch to be switched between a voltage output mode and a voltage write mode.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 17, 2019
    Assignee: IRIS OPTRONICS CO., LTD.
    Inventors: Chi-Chang Liao, Shu-Shien Liu, Tsung-Ming Pai, Fu-Ming Wang
  • Patent number: 10505019
    Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10497724
    Abstract: The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 3, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhichao Zhou, Hui Xia, Meng Chen