On Insulating Substrate Or Layer (e.g., Tft, Etc.) Patents (Class 438/149)
  • Patent number: 11901367
    Abstract: A method of manufacturing an array substrate, includes: providing a substrate; forming a gate conductive layer including at least one first alignment mark; forming a source-drain conductive thin film; aligning a first mask and the substrate on which the gate conductive layer and the source-drain conductive thin film have been formed according to the at least one first alignment mark; patterning the source-drain conductive thin film by using the first mask to form at least one second alignment mark to obtain a source-drain conductive layer; forming a black matrix thin film; aligning a second mask and the substrate on which the gate conductive layer, the source-drain conductive layer and the black matrix thin film have been formed according to the at least one second alignment mark; patterning the black matrix thin film by using the second mask to form a black matrix; and forming a color filter layer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 13, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yan Wang, Yanqing Chen, Wei Li, Ning Wang, Weida Qin, Zhao Zhang, Jing Li, Feng Yang
  • Patent number: 11894486
    Abstract: Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: February 6, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miyuki Hosoba, Suzunosuke Hiraishi
  • Patent number: 11889736
    Abstract: A display device may include a substrate including a display area and a bending area, a buffer layer disposed on the substrate, a first dummy pattern disposed in the bending area on the buffer layer; a first insulating layer disposed on the buffer layer, the first insulating layer exposing an upper surface of the first dummy pattern, a second insulating layer disposed on the first insulating layer, the second insulating layer having an opening exposing an upper surface of the first dummy pattern, a second dummy pattern disposed on the first dummy pattern, and a transmission line disposed on the second dummy pattern.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 30, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chungi You
  • Patent number: 11881434
    Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Connie Alagadan Esteron, Dolores Babaran Milo
  • Patent number: 11874574
    Abstract: According to one embodiment, a display device includes a signal line, a scanning line, a semiconductor layer, a first insulating layer which covers the semiconductor layer, a color filter above the first insulating layer, a pixel electrode above the color filter and a common electrode. The first insulating layer includes a first contact hole for connecting the semiconductor layer and the pixel electrode to each other. The first contact hole is provided at a position displaced from the color filter in plan view.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 16, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Fumiya Kimura, Isao Suzumura
  • Patent number: 11862626
    Abstract: An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Hung Yeh
  • Patent number: 11860541
    Abstract: The present disclosure discloses a silicon-based nanowire, a preparation method thereof, and a thin film transistor. By using a eutectic point of catalyst particles and silicon, and a driving factor that the Gibbs free energy of amorphous silicon is greater than that of crystalline silicon, and due to absorption of the amorphous silicon by the molten catalyst particles to form a supersaturated silicon eutectoid, the silicon nucleates and grows into silicon-based nanowires. Moreover, during the growth of the silicon-based nanowire, the amorphous silicon film grows linearly along guide slots under the action of the catalyst particles, and reverse growth of the silicon-based nanowire is restricted by the retaining walls, thus obtaining silicon-based nanowires with a high density and high uniformity. Furthermore, by controlling the size of the catalyst particles and the thickness of the amorphous silicon film, the width of the silicon-based nanowire may also be controlled.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 2, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xue Dong, Guangcai Yuan, Feng Guan
  • Patent number: 11848397
    Abstract: The present application relates to the technical field of solar cells, and in particular, to a method for preparing a solar cell, the solar cell, and a photovoltaic module. The method for preparing the solar cell includes: providing a substrate; forming a doped amorphous silicon layer on the first side of the substrate; performing laser treatment N times on the doped amorphous silicon layer to form N doped polysilicon layers ranging from a first doped polysilicon layer to a Nth doped polysilicon layer stacked in a direction away from the substrate, where N>1, a power, a wavelength and a pulse irradiation number of a nth laser treatment are respectively smaller than a power, a wavelength and a pulse irradiation number of a (n?1)th laser treatment, where n?N, and the first doped polysilicon layer is disposed closer to the substrate than the Nth doped polysilicon layer. The embodiments of the present application are conducive to simplify the process of forming the solar cell.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: December 19, 2023
    Assignee: ZHEJIANG JINKO SOLAR CO., LTD.
    Inventors: Jingsheng Jin, Bike Zhang, Xinyu Zhang
  • Patent number: 11834741
    Abstract: A method includes: 1) performing an atomic layer deposition cycle including (a) introducing precursors into a deposition chamber housing a substrate to deposit a material on the substrate; and (b) introducing a passivation gas into the deposition chamber to passivate a surface of the material; and 2) repeating 1) a plurality of times to form a film of the material.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 5, 2023
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Friedrich B. Prinz, Shicheng Xu, Timothy English, John Provine, Dickson Thian, Jan Torgersen
  • Patent number: 11822173
    Abstract: A substrate, a method of manufacturing thereof, and a display panel are provided. The substrate includes a substrate layer and a super-hydrophobic layer. The substrate layer includes a first surface and a second surface disposed opposite the first surface. The super-hydrophobic layer is located on the first surface of the substrate layer. The super-hydrophobic layer is a porous metal film formed of a copper-zinc alloy.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 21, 2023
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Hu Wang
  • Patent number: 11810921
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: November 7, 2023
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
  • Patent number: 11791416
    Abstract: This application discloses a display panel, a method for manufacturing a display panel, and a display device. The method includes steps of forming, in a display region of the display panel, a first active switch including a first semiconductor layer, and forming, in a non-display region of the display panel, a second active switch including a second semiconductor layer. A material of the first semiconductor layer formed is an oxide, a material of the second semiconductor layer formed is polysilicon, and the first semiconductor layer and the second semiconductor layer are formed on an identical layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 17, 2023
    Assignee: HKC CORPORATION LIMITED
    Inventors: En-Tsung Cho, Qionghua Mo
  • Patent number: 11793013
    Abstract: A flexible display panel and a fabricating method thereof are described. The fabricating method has steps of: providing a substrate comprising a hard state and a soft state; forming a thin-film transistor layer on a side of the substrate in the hard state; forming an organic light-emitting layer on a side of the thin-film transistor layer away from the substrate; forming an encapsulation layer on a side of the organic light-emitting layer away from the thin-film transistor; wherein, after laying of each film layer in the flexible display panel, a photoinitiator layer is formed on a side of the substrate away from the thin-film transistor layer, and the substrate and the photoinitiator layer are irradiated with the preset ultraviolet light to change the substrate from the hard state to the soft state to obtain the flexible display panel. The fabricating method avoids problems caused by using laser lift-off technology.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: October 17, 2023
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jing Liu
  • Patent number: 11774231
    Abstract: A method comprising: measuring a plurality of measurement capacitances using a capacitance measurement device; calculating a plurality of deposition coefficients for the deposition parameter corresponding to each of the plurality of the measurement capacitances, a plurality of exposure coefficients for the exposure parameter corresponding to each of the plurality of the measurement capacitances, and a plurality of etching coefficients for the etching parameter corresponding to each of the plurality of the measurement capacitances; calculating a corrected deposition coefficient for the plurality of the deposition coefficients, a corrected exposure coefficient for the plurality of the exposure coefficients, and a corrected etching coefficient for the plurality of the etching coefficients; and calculating the capacitance based on a capacitance calculation equation including the deposition parameter, the corrected deposition coefficient, the exposure parameter, the corrected exposure coefficient, the etching para
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: October 3, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jungho Choi
  • Patent number: 11774858
    Abstract: A touch sensor comprises a group pattern having a sensing cell part including a plurality of sensing cell groups in which a plurality of sensing cells are electrically connected and a wiring part formed outside the sensing cell part. The wiring part includes a first sub-wiring part and a second sub-wiring part. The first sub-wiring part has a drawing wire electrically connected to a sensing cell at one end of the sensing cell group. The second sub-wiring part is disposed outside the first sub-wiring part and has a non-drawing wire not electrically connected to the sensing cell part. The non-drawing wires are provided as many as the number of unit patterns repeatedly formed to constitute a large-area touch sensor minus one.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 3, 2023
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Byoungin Kim, Cheol Hun Lee, Chang Gyeong Lim, Minseok Jang
  • Patent number: 11764225
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 19, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Uzma Rana, Siva P. Adusumilli, Steven M. Shank
  • Patent number: 11749365
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: September 5, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yuugo Goto, Hiroyuki Miyake, Daisuke Kurosaki
  • Patent number: 11742356
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Uejima, Kazuhiro Koudate
  • Patent number: 11710521
    Abstract: 6T-SRAM cell designs for larger SRAM arrays and methods of manufacture generally include a single fin device for both nFET (pass-gate (PG) and pull-down (PD)) and pFET (pull-up (PU). The pFET can be configured with a smaller effective channel width (Weff) than the nFET or with a smaller active fin height. An SRAM big cell consumes the (111) 6t-SRAM design area while provide different Weff ratios other than 1:1 for PU/PD or PU/PG as can be desired for different SRAM designs.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: July 25, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lan Yu, Junli Wang, Heng Wu, Ruqiang Bao, Dechao Guo
  • Patent number: 11681225
    Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 11682679
    Abstract: The present disclosure provides a manufacturing method of a display substrate, a display substrate and a display device, belongs to the field of display technology, and can at least partially solve a problem of residual sand in the display substrate. The manufacturing method of the display substrate includes: providing a base; forming a passivation layer on a surface of the base; forming an amorphous oxide conductive material layer on a surface of the passivation layer facing away from the base; forming a photoresist pattern on the oxide conductive material layer, the photoresist pattern having an exposure region; etching a portion of the oxide conductive material layer in the exposure region of the photoresist pattern to form a hollow position exposing a portion of the passivation layer; and removing a certain thickness material of the portion of the passivation layer exposed through the hollow position.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 20, 2023
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lin Chen, Chengshao Yang, Tao Ma, Dengfeng Wang, Ling Han
  • Patent number: 11678513
    Abstract: A display device includes a substrate, sub-pixels on the substrate, a passivation layer on the sub-pixels, and an emitted light control layer on the passivation layer to define a non-emissive area between the sub-pixels, wherein the emitted light control layer includes black matrix layers divided into at least two layers.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: June 13, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Soon-Hwan Hong, Kyung-Ah Chin, Seong-Yeong Kim
  • Patent number: 11653524
    Abstract: A display device includes a substrate including a plastic layer, a barrier layer, and a display area in which an image is displayed. The display device further includes a light-emitting diode disposed in the display area, a planarization layer, and a pixel definition layer. The planarization layer and the pixel definition layer overlap the light-emitting diode. The display device further includes a thin film encapsulation layer disposed on the pixel definition layer. The thin film encapsulation layer includes at least one inorganic layer. The display device further includes an opening disposed in the display area and penetrating the substrate. The opening includes a protruded portion and a depressed portion, and the barrier layer overlaps at least one of the pixel definition layer and the planarization layer at the protruded portion.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Ho Yoon, Woo Yong Sung, Won Je Cho, Won Woo Choi
  • Patent number: 11631529
    Abstract: In an electronic component, a terminal electrode has a thickest portion and a part thinner than the thickest portion. Accordingly, an increase in solder fillet forming region occurs when the electronic component is solder-mounted onto a predetermined mounting substrate. In the electronic component, mounting strength is improved as a result of the increase in solder fillet forming region. In addition, in the electronic component, the thickest portion overlaps a bump electrode in a direction orthogonal to the lower surface of an element body. Accordingly, the impact that is applied to the electronic component during the mounting onto the mounting substrate is reduced and the impact resistance of the electronic component is improved.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 18, 2023
    Assignee: TDK CORPORATION
    Inventors: Takahiro Kawahara, Manabu Ohta, Kenei Onuma, Yuuya Kaname, Ryo Fukuoka, Hokuto Eda, Masataro Saito, Kohei Takahashi
  • Patent number: 11626568
    Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, resistance of a laterally conductive OLED layer may be increased. The laterally conductive layer may include an organic host material, dopants, and a resistance-increasing additive. Another way to reduce leakage current is to apply bias voltages to the anodes of the display and/or expose the laterally conductive layer to ultraviolet light, causing dopants within the laterally conductive layer to degrade.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: April 11, 2023
    Assignee: Apple Inc.
    Inventors: Jared S. Price, Mathew K. Mathai, Hitoshi Yamamoto, Martijn Kuik
  • Patent number: 11610807
    Abstract: Methods and apparatus for cleaving a substrate in a semiconductor chamber. The semiconductor chamber pressure is adjusted to a process pressure, a substrate is then heated to a nucleation temperature of ions implanted in the substrate, the temperature of the substrate is then adjusted below the nucleation temperature of the ions, and the temperature is maintained until cleaving of the substrate occurs. Microwaves may be used to provide heating of the substrate for the processes. A cleaving sensor may be used for detection of successful cleaving by detecting pressure changes, acoustic emissions, changes within the substrate, and/or residual gases given off by the implanted ions when the cleaving occurs.
    Type: Grant
    Filed: April 11, 2021
    Date of Patent: March 21, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Felix Deng, Yueh Sheng Ow, Tuck Foong Koh, Nuno Yen-Chu Chen, Yuichi Wada, Sree Rangasai V. Kesapragada, Clinton Goh
  • Patent number: 11609463
    Abstract: According to one embodiment, a display device includes a first substrate including a scanning line, a first inorganic insulating film, an oxide semiconductor, and a first light-shielding wall. The first inorganic insulating film, in planer view, includes a first groove formed between the oxide semiconductor and a light-emitting module. The first light-shielding wall is disposed on the first groove.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 21, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventor: Akihiro Hanada
  • Patent number: 11591710
    Abstract: A method for crystallizing an amorphous multicomponent ionic compound comprises applying an external stimulus to a layer of an amorphous multicomponent ionic compound, the layer in contact with an amorphous surface of a deposition substrate at a first interface and optionally, the layer in contact with a crystalline surface at a second interface, wherein the external stimulus induces an amorphous-to-crystalline phase transformation, thereby crystallizing the layer to provide a crystalline multicomponent ionic compound, wherein the external stimulus and the crystallization are carried out at a temperature below the melting temperature of the amorphous multicomponent ionic compound. If the layer is in contact with the crystalline surface at the second interface, the temperature is further selected to achieve crystallization from the crystalline surface via solid phase epitaxial (SPE) growth without nucleation.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: February 28, 2023
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Paul Gregory Evans, Thomas Francis Kuech, Susan Elizabeth Babcock, Mohammed Humed Yusuf, Yajin Chen
  • Patent number: 11545581
    Abstract: The present invention discloses a metal oxide (MO) semiconductor, which is implemented by respectively doping at least an oxide of rare earth element R and an oxide of rare earth element R? into an indium-containing MO semiconductor to form an InxMyRnR?mOz semiconductor. According to the present invention, the extremely high oxygen bond breaking energy in the oxide of rare earth element R is used to effectively control the carrier concentration in the semiconductor, and a charge transportation center can be formed by using the characteristic that the radius of rare earth ions is equivalent to the radius of indium ions, so that the electrical stability of the semiconductor is improved. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 3, 2023
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Miao Xu, Hua Xu, Min Li, Junbiao Peng, Lei Wang, Jian Hua Zou, Hong Tao
  • Patent number: 11538896
    Abstract: A display device includes: a display panel including first pads arranged along a first direction, and second pads spaced apart from the first pads; a first connection circuit board electrically connected to the first pads; and a second connection circuit board electrically connected to the second pads. The first connection circuit board includes: first output pads electrically connected to the first pads; and at least two first protrusion parts spaced along the first direction and protruding in a second direction crossing the first direction. The second connection circuit board includes: second output pads electrically connected to the second pads; and at least one second protrusion part protruding in the second direction, and located between the first protrusion parts when viewed on a plane that is parallel to a surface of the display panel.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 27, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wontae Kim, Jae-Han Lee
  • Patent number: 11531243
    Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: December 20, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Yukinori Shima, Kenichi Okazaki, Shunpei Yamazaki
  • Patent number: 11521873
    Abstract: According to one embodiment, a processing information management system includes: an abnormality analyzer configured to generate abnormality occurrence data of a target wafer based on processing location information, the processing location information collected based on a first sensor outputting a first sensor signal according to a detected processing state, the first sensor provided in a wafer processing apparatus; and an integration system configured to integrate the abnormality occurrence data into wafer map data corresponding to the target wafer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hidekazu Saeki, Kenta Kawamura
  • Patent number: 11521990
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first. TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 6, 2022
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
  • Patent number: 11515251
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Vincent Dorgan, Jeffrey Hicks, Inanc Meric
  • Patent number: 11508306
    Abstract: A display apparatus can include a first thin film transistor and a second thin film transistor, the first thin film transistor has a bottom gate structure, the second thin film transistor has a top gate structure, and an s-factor value of the first thin film transistor is smaller than an s-factor value of the second thin film transistor.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 22, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: JeongSuk Yang, YongSeok Park
  • Patent number: 11508613
    Abstract: The invention relates to a method of healing defects related to implantation of species in a donor substrate (1) made of a semiconducting material to form therein a plane of weakness (5) in it separating a thin layer (4) from a bulk part of the donor substrate. The method comprises a superficial amorphisation of the thin layer, followed by application of a heat treatment on the superficially amorphised thin layer. The method comprises application of laser annealing to the superficially amorphised thin layer after the heat treatment, to recrystallise it in the solid phase.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 22, 2022
    Assignee: COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pablo Acosta Alba, Shay Reboh
  • Patent number: 11502153
    Abstract: An array substrate and a manufacturing method thereof, a display device and a manufacturing method thereof are provided, which belong to the technical field of display. The array substrate includes: an interposer substrate, a thin-film transistor disposed on one side of the interposer substrate, and a bonding connection line embedded in the other side of the interposer substrate. The bonding connection line is configured to be connected to a drive circuit. An interposer via hole is arranged on the interposer substrate. A conductive structure is arranged in the interposer via hole. The thin-film transistor is electrically connected to the bonding connection line by the conductive structure.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 15, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Renquan Gu, Qi Yao, Jaiil Ryu, Zhiwei Liang, Yingwei Liu, Wusheng Li, Muxin Di
  • Patent number: 11500239
    Abstract: A display device is provided. The display device comprises a first substrate, a second substrate facing the first substrate, a first polarizing layer disposed between the first substrate and the second substrate and including first line grid patterns, a light scattering layer disposed between the first polarizing layer and the second substrate, and color filter layers disposed between the light scattering layer and the second substrate.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 15, 2022
    Inventors: Tae Hyung Hwang, Dong Il Son
  • Patent number: 11489027
    Abstract: A display apparatus having a display area and a pad area and a method of manufacturing the same, the display apparatus including a base substrate; a thin film transistor on the base substrate in the display area; an insulation layer on the base substrate and the thin film transistor; a conductive pattern layer on the insulation layer, the conductive pattern layer including a pad electrode in the pad area; and a via insulation layer on the insulation layer, exposing an upper surface of the pad electrode, and covering edges of the pad electrode, wherein, in the pad area, the insulation layer includes a groove having a depth, the pad electrode being in the groove.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwui-Hyun Park, Chulwon Park, Pil Soon Hong, Hyunjin Son
  • Patent number: 11482583
    Abstract: A display apparatus having a plurality of subpixels is provided. The display apparatus includes an array substrate and a counter substrate facing the array substrate. The counter substrate includes a base substrate; an optical compensation device on the base substrate configured to adjust light emitting brightness values of the plurality of subpixels to target brightness values respectively; and a plurality of light shielding walls on the base substrate. The optical compensation device include a plurality of photosensors configured to respectively detect light emitting brightness values of the plurality of subpixels. A respective one of the plurality of light shielding walls is configured to at least partially shield a lateral side of a respective one of the plurality of photosensors from light emitted from adjacent subpixels.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 25, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing BOE Technology Development Co., Ltd.
    Inventors: Weipin Hu, Lianjie Qu, Qianqian Bu, Xiao Sun
  • Patent number: 11476342
    Abstract: Semiconductor device includes substrate having fins, first S/D feature comprising first epitaxial layer contacting first fin, second epitaxial layer on first epitaxial layer, third epitaxial layer on second epitaxial layer, third epitaxial layer comprising center and edge portion higher than center portion, and fourth epitaxial layer on third epitaxial layer, second S/D feature adjacent first S/D feature and comprising first epitaxial layer contacting second fin, second epitaxial layer on first epitaxial layer of second S/D feature, third epitaxial layer on second epitaxial layer of second S/D feature, third epitaxial layer comprising center and edge portion higher than center portion of third epitaxial layer, center and edge portions of third epitaxial layer of first and second S/D features are merging, and fourth epitaxial layer on third epitaxial layer of second S/D feature, S/D contact covering edge and center portions of third epitaxial layers of first and second S/D features.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11475829
    Abstract: An optoelectronic light emitting device includes an optoelectronic semiconductor component configured to generate light, a current source configured to generate a current, and a PWM transistor driven by a pulse-width modulated signal. The PWM transistor enters a first state or a second state based on said pulse-width modulated signal. The PWN transistor is configured to supply the optoelectronic semiconductor component with the current generated by the current source in the first state and to decouple it from the current generated by the current source in the second state. The current source is manufactured by a first technology and the PWM transistor is manufactured by a second technology.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 18, 2022
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Hubert Halbritter, Jens Richter
  • Patent number: 11476282
    Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Hideki Kitagawa, Yoshiharu Hirata
  • Patent number: 11456297
    Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: September 27, 2022
    Assignees: SK hynix Inc., Duality Inc.
    Inventor: Jin Hong Ahn
  • Patent number: 11442317
    Abstract: The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 13, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11424246
    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hiroyuki Miyake, Kiyoshi Kato
  • Patent number: 11411208
    Abstract: A highly reliable light-emitting device is provided. A yield in a manufacturing process of a light-emitting device is increased. A light-emitting device is provided in which a non-light-emitting portion having a frame-like shape outside a light-emitting portion includes a portion thinner than the light-emitting portion. A light-emitting element and a bonding layer are formed over a substrate. The light-emitting element is sealed by overlapping a pair of substrates and curing the bonding layer. Then, while the cured bonding layer is heated, pressure is applied to at least a portion of the non-light-emitting portion with a member having a projection.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 11398492
    Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 26, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Tianhong Yan, Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11398437
    Abstract: A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 26, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Bongyong Lee, Bohee Kang, Doojin Choi, Kyeongseok Park, Thomas Neyer, Jeongwoo Yang
  • Patent number: RE49814
    Abstract: A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 23, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyuk Soon Kwon