On Insulating Substrate Or Layer (e.g., Tft, Etc.) Patents (Class 438/149)
  • Patent number: 11545581
    Abstract: The present invention discloses a metal oxide (MO) semiconductor, which is implemented by respectively doping at least an oxide of rare earth element R and an oxide of rare earth element R? into an indium-containing MO semiconductor to form an InxMyRnR?mOz semiconductor. According to the present invention, the extremely high oxygen bond breaking energy in the oxide of rare earth element R is used to effectively control the carrier concentration in the semiconductor, and a charge transportation center can be formed by using the characteristic that the radius of rare earth ions is equivalent to the radius of indium ions, so that the electrical stability of the semiconductor is improved. The present invention further provides a thin-film transistor based on the MO semiconductor and application thereof.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 3, 2023
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Miao Xu, Hua Xu, Min Li, Junbiao Peng, Lei Wang, Jian Hua Zou, Hong Tao
  • Patent number: 11538896
    Abstract: A display device includes: a display panel including first pads arranged along a first direction, and second pads spaced apart from the first pads; a first connection circuit board electrically connected to the first pads; and a second connection circuit board electrically connected to the second pads. The first connection circuit board includes: first output pads electrically connected to the first pads; and at least two first protrusion parts spaced along the first direction and protruding in a second direction crossing the first direction. The second connection circuit board includes: second output pads electrically connected to the second pads; and at least one second protrusion part protruding in the second direction, and located between the first protrusion parts when viewed on a plane that is parallel to a surface of the display panel.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 27, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wontae Kim, Jae-Han Lee
  • Patent number: 11531243
    Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: December 20, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Yukinori Shima, Kenichi Okazaki, Shunpei Yamazaki
  • Patent number: 11521990
    Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first. TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 6, 2022
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
  • Patent number: 11521873
    Abstract: According to one embodiment, a processing information management system includes: an abnormality analyzer configured to generate abnormality occurrence data of a target wafer based on processing location information, the processing location information collected based on a first sensor outputting a first sensor signal according to a detected processing state, the first sensor provided in a wafer processing apparatus; and an integration system configured to integrate the abnormality occurrence data into wafer map data corresponding to the target wafer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hidekazu Saeki, Kenta Kawamura
  • Patent number: 11515251
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Vincent Dorgan, Jeffrey Hicks, Inanc Meric
  • Patent number: 11508613
    Abstract: The invention relates to a method of healing defects related to implantation of species in a donor substrate (1) made of a semiconducting material to form therein a plane of weakness (5) in it separating a thin layer (4) from a bulk part of the donor substrate. The method comprises a superficial amorphisation of the thin layer, followed by application of a heat treatment on the superficially amorphised thin layer. The method comprises application of laser annealing to the superficially amorphised thin layer after the heat treatment, to recrystallise it in the solid phase.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 22, 2022
    Assignee: COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pablo Acosta Alba, Shay Reboh
  • Patent number: 11508306
    Abstract: A display apparatus can include a first thin film transistor and a second thin film transistor, the first thin film transistor has a bottom gate structure, the second thin film transistor has a top gate structure, and an s-factor value of the first thin film transistor is smaller than an s-factor value of the second thin film transistor.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 22, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: JeongSuk Yang, YongSeok Park
  • Patent number: 11500239
    Abstract: A display device is provided. The display device comprises a first substrate, a second substrate facing the first substrate, a first polarizing layer disposed between the first substrate and the second substrate and including first line grid patterns, a light scattering layer disposed between the first polarizing layer and the second substrate, and color filter layers disposed between the light scattering layer and the second substrate.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 15, 2022
    Inventors: Tae Hyung Hwang, Dong Il Son
  • Patent number: 11502153
    Abstract: An array substrate and a manufacturing method thereof, a display device and a manufacturing method thereof are provided, which belong to the technical field of display. The array substrate includes: an interposer substrate, a thin-film transistor disposed on one side of the interposer substrate, and a bonding connection line embedded in the other side of the interposer substrate. The bonding connection line is configured to be connected to a drive circuit. An interposer via hole is arranged on the interposer substrate. A conductive structure is arranged in the interposer via hole. The thin-film transistor is electrically connected to the bonding connection line by the conductive structure.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 15, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Renquan Gu, Qi Yao, Jaiil Ryu, Zhiwei Liang, Yingwei Liu, Wusheng Li, Muxin Di
  • Patent number: 11489027
    Abstract: A display apparatus having a display area and a pad area and a method of manufacturing the same, the display apparatus including a base substrate; a thin film transistor on the base substrate in the display area; an insulation layer on the base substrate and the thin film transistor; a conductive pattern layer on the insulation layer, the conductive pattern layer including a pad electrode in the pad area; and a via insulation layer on the insulation layer, exposing an upper surface of the pad electrode, and covering edges of the pad electrode, wherein, in the pad area, the insulation layer includes a groove having a depth, the pad electrode being in the groove.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwui-Hyun Park, Chulwon Park, Pil Soon Hong, Hyunjin Son
  • Patent number: 11482583
    Abstract: A display apparatus having a plurality of subpixels is provided. The display apparatus includes an array substrate and a counter substrate facing the array substrate. The counter substrate includes a base substrate; an optical compensation device on the base substrate configured to adjust light emitting brightness values of the plurality of subpixels to target brightness values respectively; and a plurality of light shielding walls on the base substrate. The optical compensation device include a plurality of photosensors configured to respectively detect light emitting brightness values of the plurality of subpixels. A respective one of the plurality of light shielding walls is configured to at least partially shield a lateral side of a respective one of the plurality of photosensors from light emitted from adjacent subpixels.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 25, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing BOE Technology Development Co., Ltd.
    Inventors: Weipin Hu, Lianjie Qu, Qianqian Bu, Xiao Sun
  • Patent number: 11475829
    Abstract: An optoelectronic light emitting device includes an optoelectronic semiconductor component configured to generate light, a current source configured to generate a current, and a PWM transistor driven by a pulse-width modulated signal. The PWM transistor enters a first state or a second state based on said pulse-width modulated signal. The PWN transistor is configured to supply the optoelectronic semiconductor component with the current generated by the current source in the first state and to decouple it from the current generated by the current source in the second state. The current source is manufactured by a first technology and the PWM transistor is manufactured by a second technology.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 18, 2022
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Hubert Halbritter, Jens Richter
  • Patent number: 11476282
    Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Hideki Kitagawa, Yoshiharu Hirata
  • Patent number: 11476342
    Abstract: Semiconductor device includes substrate having fins, first S/D feature comprising first epitaxial layer contacting first fin, second epitaxial layer on first epitaxial layer, third epitaxial layer on second epitaxial layer, third epitaxial layer comprising center and edge portion higher than center portion, and fourth epitaxial layer on third epitaxial layer, second S/D feature adjacent first S/D feature and comprising first epitaxial layer contacting second fin, second epitaxial layer on first epitaxial layer of second S/D feature, third epitaxial layer on second epitaxial layer of second S/D feature, third epitaxial layer comprising center and edge portion higher than center portion of third epitaxial layer, center and edge portions of third epitaxial layer of first and second S/D features are merging, and fourth epitaxial layer on third epitaxial layer of second S/D feature, S/D contact covering edge and center portions of third epitaxial layers of first and second S/D features.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11456297
    Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: September 27, 2022
    Assignees: SK hynix Inc., Duality Inc.
    Inventor: Jin Hong Ahn
  • Patent number: 11442317
    Abstract: The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 13, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11424246
    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hiroyuki Miyake, Kiyoshi Kato
  • Patent number: 11411208
    Abstract: A highly reliable light-emitting device is provided. A yield in a manufacturing process of a light-emitting device is increased. A light-emitting device is provided in which a non-light-emitting portion having a frame-like shape outside a light-emitting portion includes a portion thinner than the light-emitting portion. A light-emitting element and a bonding layer are formed over a substrate. The light-emitting element is sealed by overlapping a pair of substrates and curing the bonding layer. Then, while the cured bonding layer is heated, pressure is applied to at least a portion of the non-light-emitting portion with a member having a projection.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 11398437
    Abstract: A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 26, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Bongyong Lee, Bohee Kang, Doojin Choi, Kyeongseok Park, Thomas Neyer, Jeongwoo Yang
  • Patent number: 11398492
    Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 26, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Tianhong Yan, Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11393871
    Abstract: A method for fabricating an array substrate, a display panel, and a display device is provided. The array substrate is divided into a plurality of pixel regions, and each of the pixel regions is provided with a pixel thin film transistor (TFT). At least one of the pixel regions is provided with a pressure component and a force TFT, the force TFT includes a first electrode, a second electrode and a control electrode, and the pressure component is connected to one of the first electrode and the control electrode of the force TFT. At least one of layer structures of the pixel TFT is disposed in the same layer as a corresponding layer structure of the force TFT.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 19, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuzhen Guo, Xue Dong, Haisheng Wang, Chunwei Wu, Yingming Liu, Xiaoliang Ding, Xueyou Cao, Chihjen Cheng
  • Patent number: 11387308
    Abstract: The present application discloses an array substrate having a plurality of first thin film transistors and a plurality of second thin film transistors. Each of the plurality of first thin film transistors includes a silicon active layer. The array substrate includes a base substrate; a silicon layer having a plurality of silicon active layers respectively for the plurality of first thin film transistors; and a UV absorption layer on a side of the silicon layer distal to the base substrate, and including a plurality of UV absorption blocks. Each of the plurality of UV absorption blocks is on a side of the one of the plurality of silicon active layers distal to the base substrate, and is insulated from the one of the plurality of silicon active layers.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 12, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Zhang, Zhijun Lv, Wenqu Liu, Liwen Dong, Shizheng Zhang, Ning Dang, Zhiyong Liu
  • Patent number: 11367740
    Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, a flexible display panel, and a display device, all for achieving a frame-free full-screen flexible display product. The array substrate provided in the present disclosure comprises a flexible base substrate, a thin film transistor on a first surface of the flexible base substrate, and a wiring terminal for transmitting a signal to an electrode of the thin film transistor on a second surface of the flexible base substrate opposite to the first surface. The electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 21, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qi Yao, Yingwei Liu
  • Patent number: 11348991
    Abstract: A display device includes a substrate in which a first area, a second area and a bending area between the first and second areas are defined, a plurality of pixels disposed above the substrate in the first area, a plurality of conductive layers extending to and intersecting the bending area, a protective film covering the conductive layers and disposed in the bending area, a first portion of the first area adjacent to the bending area, and a second portion of the second area adjacent to the bending area. The display device further includes a plurality of tag layers disposed in the first and second portions and connected to both ends of the conductive layers, wherein the bending area is interposed between the plurality of tag layers. The tag layers are exposed to an outside of the display device by exposure holes defined in the protective film.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Horyun Chung, Sejoong Shin, Hyojin Kim, Taehyun Sung, Changhan Lee
  • Patent number: 11309403
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11287798
    Abstract: A substrate processing apparatus includes a film-forming device that forms a photosensitive film on a front surface of a substrate, a warping data acquisition device that acquires measured warping data of the substrate, a roughening process device that applies roughening process on a back surface of the substrate, and a control device including circuitry that controls the warping data acquisition device such that after the photosensitive film is formed on the front surface of the substrate, the warping data acquisition device acquires the measured warping data before the photosensitive film on the substrate undergoes exposure process, and control the roughening process device such that before the photosensitive film on the substrate undergoes the exposure process, the roughening process device applies the roughening process on the back surface of the substrate based on the measured warping data.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 29, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Teruhiko Kodama, Masashi Enomoto
  • Patent number: 11288485
    Abstract: Disclosed herein includes a method, an apparatus, a display device and storage medium storing computer executable instructions for fingerprint recognition. The method may comprise turning on a first subset of a plurality of light sources located on an apparatus, capturing a first fingerprint acquisition frame using a plurality of image sensors on the apparatus, turning on a second subset of the plurality of light sources, and capturing a second fingerprint acquisition frame using the plurality of image sensors. The first fingerprint acquisition frame may include a first set of valid image zones and a first set of invalid image zones. The second fingerprint acquisition frame may include a second set of valid image zones and a second set of invalid image zones. The second set of valid image zones at least partially covers areas of a finger touching interface different from the first set of valid image zones.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 29, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Changfeng Li, Haisheng Wang, Lei Wang, Yingming Liu, Xiaoliang Ding, Yapeng Li, Yuanyuan Ma, Yawei Wang
  • Patent number: 11271015
    Abstract: A display device includes a substrate, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including an oxide semiconductor and a first active layer, a first gate insulating layer disposed on the first semiconductor layer and the buffer layer, a second semiconductor layer disposed on the first gate insulating layer and including an oxide semiconductor, a second active layer, and a first oxide layer on the first active layer, a second gate insulating layer disposed on the second semiconductor layer, a first conductive layer disposed on the second gate insulating layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a passivation layer disposed on the second conductive layer, and a third conductive layer disposed on the first passivation layer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joon Seok Park, Myoung Hwa Kim, Tae Sang Kim, Hyung Jun Kim, Yeon Keon Moon, Geun Chul Park, Sang Woo Sohn, Jun Hyung Lim, Kyung Jin Jeon, Hye Lim Choi
  • Patent number: 11249361
    Abstract: An electro-optical device includes a wiring substrate including a wiring line, a common electrode, a conduction member that is electrically conductive, the conduction member being configured to electrically couple the wiring line and the common electrode, a pixel electrode disposed between the wiring substrate and the common electrode, and an electro-optical layer disposed between the pixel electrode and the common electrode. The wiring substrate includes: an insulating layer disposed between the wiring line and the common electrode, a conduction electrode between the insulating layer and the common electrode and in contact with the insulating layer, the conduction member being disposed at the conduction electrode, and a contact portion composed of a material different from the conduction electrode and penetrating the insulating layer, the contact portion being configured to electrically couple the conduction electrode and the wiring line.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: February 15, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11239298
    Abstract: An Organic Light-emitting Diode (OLED) display substrate, a method of forming the same and a display device are provided. The OLED display substrate includes: a driving thin film transistor located on a base substrate and configured to drive an OLED light-emitting unit to emit light; and a photosensitive thin film transistor located on the base substrate and configured to be capable of detecting light emitted by the OLED light-emitting unit and generating an electrical signal, at least a part of film layers of the photosensitive thin film transistor and at least a part of film layers of the driving thin film transistor are disposed at a same layer and made of a same material.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: February 1, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Muxin Di, Yingwei Liu, Zhiwei Liang, Haixu Li, Zhanfeng Cao
  • Patent number: 11222899
    Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
  • Patent number: 11205570
    Abstract: A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side surface of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 21, 2021
    Inventor: Ying Hong
  • Patent number: 11189493
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate having a front surface and a rear surface, and an ohmic electrode in ohmic contact with silicon carbide of at least one of the front surface or the rear surface of the silicon carbide semiconductor substrate. The ohmic electrode is made of Ni containing 0.1 wt % or more and 15 wt % or less of P as an impurity. The ohmic electrode contains Ni silicide including NiSi. The ohmic electrode further contains Ni5P2 in the Ni silicide. A method for manufacturing the silicon carbide semiconductor device includes forming a metal thin film on the silicon carbide that is to be in ohmic contact with the ohmic electrode, and forming the ohmic electrode by laser annealing that includes irradiating the metal thin film with laser light and reacting the Ni with Si in the silicon carbide to generate Ni silicide.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 30, 2021
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Kazuhiko Sugiura
  • Patent number: 11183519
    Abstract: A method of manufacturing a TFT substrate and a manufacturing apparatus of a TFT substrate are provided. The method of manufacturing a TFT substrate comprises: forming active switches on a substrate; forming transparent electrode layer on the active switches; and forming a pixel layer on the transparent electrode layer. The step of forming the active switches on the substrate comprises: forming a metal layer on the substrate; bombarding the metal layer with hydrogen ions; and forming a protection layer on the metal layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 23, 2021
    Assignee: HKC CORPORATION LIMITED
    Inventor: Huailiang He
  • Patent number: 11183663
    Abstract: One or more exemplary embodiments provide a display apparatus including a substrate; an encapsulation substrate facing the substrate; a display portion disposed between the substrate and the encapsulation substrate and including a display region; a metal layer disposed on the substrate and surrounding the display region; and a sealing portion formed to overlap the metal layer and coupling the substrate to the encapsulation substrate, wherein the metal layer includes a first region disposed outside of the display region at one side of the display region and a second region disposed outside of the display region at another side, which is opposite to the one side, of the display region, and the metal layer has a different light reflectivity in the first region and the second region.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jungho Choi
  • Patent number: 11183516
    Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: November 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yuta Endo, Kazuya Hanaoka
  • Patent number: 11177334
    Abstract: A display substrate, display panel, and method of fabricating the display substrate. The display substrate includes: a first thin film transistor on a substrate; a second thin film transistor on the substrate and on the same side of the substrate as first thin film transistor; a light blocking structure between the substrate and an active region of first thin film transistor. The light blocking structure is configured to block at least a portion of light incident on the active region of first thin film transistor, such that a ratio of area of an illuminated portion of the active region of first thin film transistor to an area of the active region of first thin film transistor is less than a ratio of area of an illuminated portion of an active region of second thin film transistor to an area of the active region of second thin film transistor.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: November 16, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liang Lin, Yunhai Wan, Zhixiang Zou, Chuan Chen, Wei He
  • Patent number: 11171308
    Abstract: A display device comprising: a display panel including: a first area having a first transmittance; and a second area having a second transmittance higher than the first transmittance; and a first module under the second area, wherein the display panel comprises: a base layer; a circuit layer on the base layer; a first pixel electrode electrically connected to the circuit layer and in the first area; a second pixel electrode electrically connected to the circuit layer and in the second area; a first stack structure on the circuit layer and adjacent to the first pixel electrode; and a second stack structure which is on the circuit layer, is adjacent to the second pixel electrode, and is different from the first stack structure.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Haram Yoo, Sangyeol Kim, Sokwon Noh
  • Patent number: 11164740
    Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 2, 2021
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
  • Patent number: 11158732
    Abstract: A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 26, 2021
    Inventors: Seongjae Cho, EunSeon Yu, Jae Yoon Lee
  • Patent number: 11152260
    Abstract: An embedding method includes: removing a metal oxide film at a surface of a metal layer from a substrate that includes the metal layer on a bottom of a recess formed in an insulating layer; covering the surface of the metal layer by embedding ruthenium in the recess from the bottom of the recess; forming a ruthenium liner film in the recess; and further embedding ruthenium in the recess in which the liner film is formed.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: October 19, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tadahiro Ishizaka
  • Patent number: 11127855
    Abstract: A LDMOS transistor that may include (i) a first region that is a reduced surface field (RESURF) implant region of a first type; (ii) a second region that is a RESURF implant region of a second type, wherein the first type differs from the second type; (iii) a gate; (iv) a stepped oxide region and a gate oxide region that are positioned above the first region and below the gate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Tower Semiconductors Ltd.
    Inventors: Daniel Sherman, Sagy Levy, David Mistele
  • Patent number: 11119053
    Abstract: Wireless sensing devices including stable near-field antennas are provided. A spacer layer is attached to a portion of the substrate adjacent to the antenna. The spacer layer has a thickness T, a relative permittivity k, and a figure of merit defined as the ratio of T (in micrometers) by k. The spacer layer has the figure of merit no less than 20 (micrometers).
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: September 14, 2021
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Zohaib Hameed, Nicholas T. Gabriel, Ronald D. Jesme, Christian Weinmann, Kristin J. Godbey, Bret W. Ludwig, John P. Baetzold
  • Patent number: 11121257
    Abstract: The present disclosure provides a thin film transistor, a pixel structure, a display device, and a manufacturing method. The thin film transistor includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain respectively connected to the semiconductor layer. The first support portion and the second support portion are respectively configured to support the semiconductor layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 14, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhaohui Qiang, Feng Guan, Zhi Wang, Yupeng Gao, Yang Lyu, Chao Li, Jianhua Du, Lei Chen
  • Patent number: 11107819
    Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 11100989
    Abstract: A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operation section, memory cells storing respective synaptic connection weights are arranged in rows and columns. Output lines are connected to memory cells in the corresponding column, and input lines are connected to memory cells in the corresponding row. Each output line is precharged, and then its electric potential is decreased during the corresponding memory cells flow cell currents corresponding to their synaptic connection weights. A memory element of each memory cell includes a memory transistor, a drain side transistor, and a source side transistor connected in series, and is connected between the corresponding input and output line. The memory transistor stores a synaptic connection weight according to the amount of charge in a charge storage layer.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 24, 2021
    Assignee: FLOADIA CORPORATION
    Inventors: Kazumasa Yanagisawa, Tomoichi Hayashi, Satoshi Noda, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 11088180
    Abstract: The present disclosure provides a conductive wire structure, a manufacturing method thereof, an array substrate and a display device. The conductive wire structure includes a first conductive wire and a second conductive wire on a first plane, wherein a connection end of the first conductive wire is spaced apart from a connection end of the second conductive wire by a gap so as to discharge charges accumulated on the first conductive wire and the second conductive wire through the gap; an electrical connector connected to the connection end of the first conductive wire and the connection end of the second conductive wire, respectively, wherein a part of the electrical connector is located on a second plane different from the first plane.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: August 10, 2021
    Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Tianzhen Liu, Xianxue Duan, Dezhi Xu
  • Patent number: 11088222
    Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: August 10, 2021
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata, Kensuke Yoshizumi
  • Patent number: 11079241
    Abstract: An embodiment of a semiconductor package apparatus may include technology to acquire location related information, acquire local area characteristic information, and verify the location related information based on the local area characteristic information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Liuyang Yang, Manoj Sastry, Yonghong Huang, Xiruo Liu, Noor Abani