Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line crossing each other to define a pixel region, a thin film transistor at a crossing of the gate and data lines, a metal pattern over the gate line, a passivation layer exposing the substrate in the pixel region, a part of the thin film transistor and a part of the metal pattern, and a pixel electrode in the pixel region. The pixel electrode is connected to the part of the thin film transistor and contacts the part of the metal pattern. The metal pattern has at least one curved portion in a side contacting the pixel electrode.

Abstract: When the laser light is irradiated with high output in the manufacturing process for a semiconductor device, an attenuator is heated and cause a deformation due to the laser light scattered in the attenuator. As a result, the attenuation ratio of the attenuator fluctuates, and it is difficult to process the substrate with the homogeneous irradiation energy. It is a problem of the present invention to provide a laser irradiation apparatus, a method of irradiating laser light and a method of manufacturing a semiconductor device, which can perform the laser irradiation effectively and homogeneously. In the present invention, the thermal energy generated in an attenuator is absorbed by means of cooling in order to keep the temperature of the attenuator constant. By cooling the attenuator so as to prevent the change of the attenuation ratio, the function of the attenuator is protected. In addition, the energy fluctuation of the laser light irradiated on the substrate is also prevented.

Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

Abstract: A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.

Abstract: The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects.

Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract: A laminated film structure, method of manufacturing, and a preferable electronic element using the structure. The effective polarization into the electric field can be realized in the direction of crystal axis by enhancing the crystal property and alignment property of the ferroelectric substance film formed through epitaxial growth with reference to the plane alignment of semiconductor substrate. After the yttrium stabilized zirconium film and a film of the rock salt structure are sequentially formed with epitaxial growth on a semiconductor substrate, the ferroelectric substance film of simple Perovskite structure is also formed with epitaxial growth. The ferroelectric substance film can improve the crystal property and alignment property thereof by rotating the plane for 45 degrees within the plane for the crystal axis of the yttrium stabilized zirconium.

Abstract: A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so that the <110>directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in <110> direction to the upper wafer, and the other of which is equal in <110> direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.

Abstract: It is an object of the invention to provide a technique forming a crystalline semiconductor film whose orientation is uniform by control of crystal orientation and obtaining a crystalline semiconductor film in which concentration of an impurity is reduced. A configuration of the invention is that a first semiconductor region is formed on a substrate having transparent characteristics of a visible light region, a barrier film is formed over the first semiconductor region, a heat retaining film covering a top and side surfaces of the first semiconductor region is formed through the barrier film, the first semiconductor region is crystallized by scanning of a continuous wave laser beam from one edge of the first semiconductor region to the other through the substrate, the heat retaining film and the barrier film are removed, then a second semiconductor region is formed as an active layer of TFT by etching the first semiconductor region.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: The present invention relates to a liquid crystal display panel and a fabricating method thereof that is capable of enhancing crystallization efficiency of an active layer and simplifying the fabricating process. A fabricating method of a liquid crystal display panel includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode formed thereon; forming an amorphous silicon film on the gate insulating film; forming an insulating pattern on the amorphous silicon film; crystallizing the amorphous silicon film into a polycrystalline silicon film using a derivative metal, the polycrystalline silicon film having source, drain and channel areas, wherein the insulating pattern overlaps the channel area of the polycrystalline silicon film; and forming source and drain electrodes on the polycrystalline silicon film, wherein the source and the drain electrodes contacting the source and drain areas of the polycrystalline silicon film, respectively.

Abstract: A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film 111 forming an active layer of the pixel transistors is controlled to be relatively small so as to suppress a photo-leakage current. The smaller the crystal grain size, the larger the included crystal defects. Carriers excited by light irradiation are smoothly captured by a defect level, and an increase of a photo-leakage current is suppressed. On the other hand, the average crystal grain size of the polycrystalline silicon film 111 constituting the peripheral transistors is controlled so as to become relatively large. The larger the crystal grain size, the larger the mobility of the carriers, and the higher the drivability of the peripheral transistors.

Abstract: The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract: [Problem] To provide technology that allows, by controlling a crystal orientation, forming a crystalline semiconductor film aligned in orientation and obtaining a crystalline semiconductor film whose impurity concentration is reduced. [Means, for Resolution] On an insulating surface, a first semiconductor region made of an amorphous semiconductor is formed, a continuous wave laser beam is scanned from one end of the first semiconductor region to the other end thereof, thereby the first semiconductor region is once melted and crystallized, thereafter in order to form an active layer of a TFT the first semiconductor region is etched, and thereby a second semiconductor region is formed. In a pattern of the second semiconductor region formed by the etching, in order to improve a field-effect mobility in the TFT, a scanning direction of the laser beam is allowed roughly coinciding with a channel length direction in a thin film transistor. [Selected Drawing] FIG. 1.

Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.

Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

Abstract: On a silicon wafer (1) to which carbon is intentionally added, an element separation insulation film (2) is selectively formed. A well (3) is formed in an element active region defined by the element separation insulation film (2). When the element separation insulation film (2) and the well (3) are formed, the silicon wafer (1) is appropriately heated, so that after the well (3) is formed, no precipitated oxygen exists on the well (3) and precipitated oxygen exists at a position deeper than the well (3). A silicon nitride film is formed as a gate insulation film (4) on the well (3). A silicon film is formed on the gate insulation film (4), and these are patterned to form a gate electrode (6).

Abstract: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.

Abstract: A thin film transistor with multiple gates is fabricated using a super grain silicon (SGS) crystallization process. The thin film transistor a semiconductor layer formed in a zigzag shape on an insulating substrate, and a gate electrode intersecting with the semiconductor layer. The semiconductor layer has a high-angle grain boundary in a portion of the semiconductor layer that does not cross the gate electrode.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.

Abstract: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.

Abstract: The present disclosure is directed to methods and systems for processing a thin film samples. In an exemplary method, semiconductor thin films are loaded onto two different loading fixtures, laser beam pulses generated by a laser source system are split into first laser beam pulses and second laser beam pulses, the thin film loaded on one loading fixture is irradiated with the first laser beam pulses to induce crystallization while the thin film loaded on the other loading fixture is irradiated with the second laser beam pulses. In a preferred embodiment, at least a portion of the thin film that is loaded on the first loading fixture is irradiated while at least a portion of the thin film that is loaded on the second loading fixture is also being irradiated. In an exemplary embodiment, the laser source system includes first and second laser sources and an integrator that combines the laser beam pulses generated by the first and second laser sources to form combined laser beam pulses.

Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Abstract: Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.

Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract: An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.

Abstract: Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline region along with the dielectric region. In particular, crystalline semiconductor regions of different crystallographic orientations may be formed, wherein a high degree of flexibility and compatibility with currently used CMOS processes is maintained.

Abstract: In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a <110> crystallographic orientation and a second semiconductor layer (405) having a <100> crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

Abstract: An amorphous silicon layer on a glass substrate is crystallized by concentrating CW radiation from a number of OPS-lasers into a line of light on the layer. The layer is moved with respect to the line of light to control the dwell time of the line on any location on the layer and to crystallize an extended area of the layer.

Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.

Abstract: A method of fabricating a liquid crystal display panel includes forming a first conductive layer on a substrate and patterning the first conductive layer using a first resist pattern printed on the first conductive layer to form a gate pattern. A semiconductor layer and a second conductive layer are stacked on a gate insulating film formed on the gate pattern. A second resist pattern having a stepped part printed on the second conductive layer forms a source/drain pattern of a transistor. A third resist pattern printed on a passivation film formed on the substrate patterns the film. A third conductive layer is formed on the patterned film and the third resist pattern and the third resist pattern is stripped to form a transparent electrode pattern including a pixel electrode connected to the drain electrode of the transistor.

Abstract: A method of fabricating a thin film transistor with multiple gates uses a super grain silicon (SGS) crystallization process. The thin film transistor includes a semiconductor layer having a zigzag shape formed on an insulating substrate, and a gate electrode that overlaps the semiconductor layer. The semiconductor layer includes a high-angle grain boundary formed during the SGS crystallization process in a portion of the semiconductor layer that is not overlapped by the gate electrode.

Abstract: Provided are a piezoelectric element and a liquid-jet head using the same, in which favorable crystallinity can be obtained with improved uniformity, breakage of a piezoelectric film can be prevented, thereby providing stable displacement properties. The piezoeletric element includes a lower electrode, a piezoelectric film formed on the lower electrode, and an upper electrode formed on the piezoelectric film. The piezoelectric film in turn includes a lower layer portion having column crystals, and an upper layer portion having column crystals which are continuous from those in the lower layer portion and having sizes larger than those in the lower layer portion.

Abstract: It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO2 blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO2 blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.

Abstract: A method of forming a gate insulation film of a crystallized thin film transistor, is provided, which can enhance an interfacial feature which exists between a gate oxide film and a silicon thin film substrate and which is fatal to performance of the thin film transistor, in the case that crystallization of amorphous silicon is performed by metal induced lateral crystallization (MILC). The gate insulation film formation method includes the steps of: forming an amorphous silicon film on an insulation substrate, and then patterning the amorphous silicon film, to thereby form a semiconductor layer; processing the semiconductor layer made of the amorphous silicon film by an oxygen plasma method, and oxidizing the silicon surface, to thereby form a first silicon oxide film; and mixing gas with silicon and depositing a second silicon oxide film on the first silicon oxide film by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

Abstract: This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance.