Having Insulated Gate Patents (Class 438/151)
  • Patent number: 11443669
    Abstract: The present application provides a driving circuit and a display device. The driving circuit includes a circuit unit including a thin-film transistor, which includes a patterned member; a capacitor, connected to at least one end of the thin-film transistor of the circuit unit, the capacitor includes an electrode plate; and a redundant patterned member, the redundant patterned member, the electrode plate and the patterned member located in a same conductive layer, the redundant patterned member connected between the patterned member and the electrode plate.
    Type: Grant
    Filed: May 9, 2020
    Date of Patent: September 13, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yanan Gao, Bangyin Peng, Ilgon Kim
  • Patent number: 11417734
    Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Chen, Yu-Jen Yeh
  • Patent number: 11398555
    Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: July 26, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Lars Mueller-Meskamp, Luca Pirro
  • Patent number: 11393698
    Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 19, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoungHee Park, JinHee Jung, OMin Kwon, JiWon Lee, YuJeong Jang
  • Patent number: 11387314
    Abstract: A display substrate includes a scan driving circuit and a display area arranged on a substrate, the scan driving circuit includes shift register units; the scan driving circuit includes a first/second voltage signal line and a first/second clock signal line extending along a first direction; the display area includes at least one driving transistor configured to drive a light emitting element for display; at least one shift register unit includes a signal output line, a first capacitor, and at least two transistors coupled to a same electrode plate of the first capacitor; the signal output line extends along a second direction intersecting the first direction; gate electrodes of the at least two transistors are respectively coupled to the same electrode plate of the first capacitor, and the first capacitor and the at least two transistors are arranged on a same side of the first voltage signal line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 12, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jie Dai, Lu Bai, Pengfei Yu, Huijuan Yang, Huijun Li, Hao Zhang
  • Patent number: 11380662
    Abstract: The present disclosure provides a manufacturing method of a display backplane which includes a base substrate having first, second and third portions. The manufacturing method includes: forming a flexible layer extending from the first portion to and covering the second and third portions; forming a pixel driving circuit on the first portion and a backlight circuit on the third portion, wherein a part of a film layer of the pixel driving circuit extends from the first portion to and covers the second and third portions; removing a film layer on a side of the flexible layer away from the base substrate and on the second portion; separating the flexible layer from the second and third portions; removing the second and third portions; and bending a film layer separated from the third portion to a side of the first portion away from the flexible layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 5, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ke Wang
  • Patent number: 11374113
    Abstract: A method of manufacturing a low temperature polysilicon thin film, including the steps of: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; roughening a surface of the silicon layer to form an uneven surface as a recrystallization growth space; and annealing the silicon layer to form a polysilicon layer, and a partial silicon material of the polysilicon layer is formed on the recrystallization growth space.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 28, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Jianfeng Shan
  • Patent number: 11360617
    Abstract: Embodiments of the present disclosure provide a touch substrate, including: a plurality of touch electrodes arranged in a same layer and insulated from each other, the touch electrodes being configured to sense touch signals; and a plurality of first touch signal lines configured to transmit the touch signals, each touch electrode being connected with a corresponding first touch signal line via a first via hole. The touch substrate further includes a plurality of second touch signal lines, wherein an extension direction of the second touch signal lines is different from that of the first touch signal lines, and each touch electrode is connected with a corresponding second touch signal line via a second via hole. In particular, the second touch signal lines corresponding to different touch electrodes are disconnected from each other. Embodiments of the present disclosure further provide a touch screen including the touch substrate.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 14, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lu Bai, Shijun Wang, Zhiying Bao, Lei Mi
  • Patent number: 11362292
    Abstract: A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area pf the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 14, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Saemleenuri Lee, SeYeoul Kwon, Dojin Kim
  • Patent number: 11355633
    Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Ruilong Xie, Chun-Chen Yeh, Balasubramanian S Pranatharthi Haran
  • Patent number: 11342412
    Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 24, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Junji Iwahori
  • Patent number: 11335556
    Abstract: Methods and materials for growing TMD materials on substrates and making semiconductor devices are described. Metal contacts may be created prior to conducting a deposition process such as chemical vapor deposition (CVD) to grow a TMD material, such that the metal contacts serve as the seed/catalyst for TMD material growth. A method of making a semiconductor device may include conducting a lift-off lithography process on a substrate to produce a substrate having metal contacts deposited thereon in lithographically defined areas, and then growing a TMD material on the substrate by a deposition process to make a semiconductor device. Further described are semiconductor devices having a substrate with metal contacts deposited thereon in lithographically defined areas, and a TMD material on the substrate, where the TMD material is a continuous, substantially uniform monolayer film between and on the metal contacts, where the metal contacts are chemically bonded to the TMD material.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 17, 2022
    Assignee: Ohio University
    Inventors: Eric Stinaff, Martin Kordesch, Sudiksha Khadka
  • Patent number: 11335553
    Abstract: A method is disclosed that includes operations as follows: after forming an ion-implanted layer disposed between an epitaxial layer and a first semiconductor substrate, bounding the epitaxial layer to a bonding oxide layer without forming any layer between the epitaxial layer and the bonding oxide layer; and removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping a remaining portion of the ion-implanted layer on the epitaxial layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 11329159
    Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Li-Ping Huang, Wei-Yuan Lu
  • Patent number: 11322564
    Abstract: A display device capable of reducing a non-display area includes a substrate including at least one hole area disposed within an emission area, and at least one blocking hole passing through inorganic insulating films disposed beneath a light emitting element while including upper and lower insulating films made of different materials. Side surfaces of the upper inorganic insulating film exposed through the blocking hole protrude beyond side surfaces of the lower inorganic insulating film exposed through the blocking hole, respectively. Accordingly, it is possible to minimize a bezel area, which is a non-display area, and to disconnect a light emitting stack by the blocking hole.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 3, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Seok-Woo Son, Jeong-Gi Yun, Jong-Han Park, Jo-Yeon Kim
  • Patent number: 11302836
    Abstract: A plasmonic field-enhanced photodetector is disclosed. The photodetector absorbs surface plasmon polaritons (SPPs) by using a light absorbing layer having a conduction band and a valence band in which an energy is split, the SPPs being generated by combining surface plasmons (SPs) with photons of a light wave, and generates photocurrent based on the absorbed SPPs.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: April 12, 2022
    Inventor: Hoon Kim
  • Patent number: 11295988
    Abstract: Semiconductor FET devices with bottom dielectric isolation and high-? first are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; source and drains alongside the active layers; and gates, offset from the source and drains by inner spacers, surrounding a portion of each of the active layers, wherein the gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers. A method of forming a semiconductor FET device is also provided.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Julien Frougier, Jingyun Zhang, Alexander Reznicek, Takashi Ando
  • Patent number: 11296225
    Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Fu-Ting Yen
  • Patent number: 11264322
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 1, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
  • Patent number: 11251311
    Abstract: A thin-film transistor, method of manufacturing the same, and a display apparatus are provided. The thin-film transistor includes a first active layer, a source, a drain, a gate, and a second active layer, the source, the drain, the gate are disposed on the first active layer with spacing, the gate is located between the source and the drain, the second active layer is disposed on the gate, the source, and the drain, the source and the drain are both respectively connected to the first active layer and the second active layer, and the gate is respectively insulated from the first active layer, the second active layer, the source, and the drain. When a voltage is applied to the gate, the source and the drain may be conducting via the first and second active layer. Therefore, a larger current may flow between the source and the drain.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 15, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 11217583
    Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 4, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Patent number: 11217700
    Abstract: Micron scale tin oxide-based semiconductor devices are provided. Reactive-ion etching is used to produce a micron-scale electronic device using semiconductor films with tin oxides, such as barium stannate (BaSnO3). The electronic devices produced with this approach have high mobility, drain current, and on-off ratio without adversely affecting qualities of the tin oxide semiconductor, such as resistivity, electron or hole mobility, and surface roughness. In this manner, electronic devices, such as field-effect transistors (e.g., thin-film transistors (TFTs)), are produced having micron scale channel lengths and exhibiting complete depletion at room temperature.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: January 4, 2022
    Assignee: Cornell University
    Inventor: Jisung Park
  • Patent number: 11211456
    Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujin Jung, Kihwan Kim, Sunguk Jang, Youngdae Cho
  • Patent number: 11201247
    Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 14, 2021
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Juncheng Xiao, Chao Tian
  • Patent number: 11177177
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. A first layer is formed over a semiconductor layer, and a first patterned mask is formed over the first layer. A cyclic etch process is then performed to define a second patterned mask in the first layer. The cyclic etch process includes a first phase to form a polymer layer over the first patterned mask and a second phase to remove the polymer layer and to remove a portion of the first layer. A portion of the semiconductor layer is removed using the second patterned mask to define a fin from the semiconductor layer.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Fo-Ju Lin, Chia-Wei Chang, Chiung Wen Hsu
  • Patent number: 11152478
    Abstract: A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kangguo Cheng, Tak H. Ning, Alexander Reznicek
  • Patent number: 11145746
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co.y, Ltd.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
  • Patent number: 11107905
    Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 11088248
    Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chun Hsiung Tsai
  • Patent number: 11049951
    Abstract: A coating liquid for forming an oxide or oxynitride insulator film, the coating liquid including: A element; at least one selected from the group consisting of B element and C element; and a solvent, wherein the A element is at least one selected from the group consisting of Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B element is at least one selected from the group consisting of Ga, Ti, Zr, and Hf, the C element is at least one selected from the group consisting of Group 2 elements in a periodic table, and the solvent includes at least one selected from the group consisting of an organic solvent having a flash point of 21° C. or more but less than 200° C. and water.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Ryoichi Saotome, Sadanori Arae, Minehide Kusayanagi, Yuichi Ando
  • Patent number: 11031348
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface and a back surface, at least one semiconductor device, a first TSV disposed in the substrate, an insulating layer surrounding the first TSV, a shielding layer surrounding the insulating layer, and a second TSV adjacent to the first TSV. The semiconductor device is disposed in a device region of the substrate. The first TSV is exposed by the front surface and the back surface of the substrate. The insulating layer includes an electrically insulating material. The shielding layer includes an electrically conductive material coupled to ground through a ground layer. The second TSV is exposed by the front surface and the back surface of the substrate.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 8, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Tse-Yao Huang
  • Patent number: 11011552
    Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Yong Park, Tae-Gon Kim
  • Patent number: 11004874
    Abstract: The disclosure discloses a thin film transistor, a method for fabricating the same, an array substrate, and a display panel. The thin film transistor includes: a first conductive layer on a base substrate, a first insulation layer on a side of the first conductive layer facing away from the base substrate, and a second conductive layer on a side of the first insulation layer facing away from the first conductive layer, wherein an active layer is arranged on a side of the first insulation layer facing the first conductive layer, and/or a side thereof facing the second conductive layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 11, 2021
    Assignees: Chongqing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hongru Zhou, Yongliang Zhao, Zhonghao Huang, Zhaojun Wang, Chao Zhang
  • Patent number: 10957536
    Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 23, 2021
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10957551
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10957796
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani, Abhijit Jayant Pethe
  • Patent number: 10923475
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heonjong Shin, Sunghun Jung, Minchan Gwak, Yongsik Jeong, Sangwon Jee, Sora You, Doohyun Lee
  • Patent number: 10877340
    Abstract: A TFT array substrate, a fabrication method thereof and a LCD panel are provided. The TFT array substrate adopts the transparent silicon-based nanolines to form the semiconductor layer of the TFT, adopts the transparent material to form the gate electrode of the TFT, and has the pixel electrode covering the region occupied by the TFT, such that the illumination emitted by the backlight can pass through the whole TFT and the pixel electrode, i.e. the pixel portion occupied by the TFT 20 is also transparent, and thus the aperture ratio can be significantly increased to enhance transmittance and display effect of high PPI LCD panels.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 29, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Hongyuan Xu
  • Patent number: 10868121
    Abstract: A method and apparatus, the method comprising: forming a layer of two dimensional material (23), in particular graphene, on a first release layer; forming, possibly a (gate) insulating layer (35), and at least two, preferably three, electrodes (25); forming a second release layer overlaying at least a portion of the layer of two dimensional material; providing a mouldable polymer (24, 26, 28) overlaying the at least two electrodes and the second release layer; and removing the first and second release layers to provide a cavity (29) between the mouldable polymer (26) and the layer of two dimensional material (23).
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 15, 2020
    Assignee: Nokia Technologies Oy
    Inventors: Darryl Cotton, Yinglin Liu, Adam Robinson, Alexander Bessonov, Richard White
  • Patent number: 10868147
    Abstract: A method of forming a transistor from a stack of layers comprising at least one insulating layer topped by at least one active layer and at least one first and one second insulating trench defining in the active layer a reception area for receiving the transistor, the transistor comprising a conduction channel formed at least partially in the active layer, the method comprising at least the following steps: forming a grid stack extending over at least the conduction channel; forming a source zone and a drain zone; wherein the formation of the grid stack is carried out in such a way as to provide at least a first and a second portion of the reception zone, not covered by the grid stack.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: December 15, 2020
    Assignee: X-FAB FRANCE
    Inventor: Nicolas Pons
  • Patent number: 10854636
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 1, 2020
    Inventors: Koji Ono, Hideomi Suzawa
  • Patent number: 10847111
    Abstract: A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Jeon, Hyung Guel Kim, Dong Hwan Kim
  • Patent number: 10833074
    Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Cheng-Han Lee, Yi-Min Huang
  • Patent number: 10825716
    Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: November 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Moser, Matteo Dainese, Matthias Kuenle, Hans-Joachim Schulze
  • Patent number: 10818665
    Abstract: An array of recessed access devices comprises islands comprising semiconductive material surrounded by insulating material. The insulating material has a bottom adjacent individual of the islands. Rows of transistor gate lines individually cross multiple of the islands within the semiconductive material and cross within the insulating material between the individual islands. Individual of the gate lines are operatively adjacent a channel region of individual of the transistors within the individual islands and interconnect the transistors in that row. The individual transistors comprise a pair of source/drain regions on opposite sides of the individual gate lines in the individual islands. A lower portion of the individual islands proximate individual of the bottoms of the insulating material has less horizontal area than an uppermost portion of the individual islands. Additional embodiments are disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10818756
    Abstract: A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Patent number: 10770310
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Yukinori Shima, Masahiko Hayakawa, Takashi Hamochi, Suzunosuke Hiraishi
  • Patent number: 10770487
    Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 8, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Juncheng Xiao, Chao Tian
  • Patent number: 10749036
    Abstract: The invention provides an oxide semiconductor TFT and manufacturing method thereof. The oxide semiconductor TFT comprises: a substrate, a gate on the substrate, a gate insulating layer on the gate and substrate, an oxide semiconductor layer on the gate insulating layer, and a barrier layer on the semiconductor layer, and a source and a drain on the oxide semiconductor layer and gate insulating layer; the oxide semiconductor layer comprising: a channel region and two contact regions respectively located at two sides of the channel region, and the barrier layer being located on the channel region; the channel region comprising a plurality of channel strips spaced apart in a channel width direction, and the barrier layer comprising a plurality of barrier strips respectively corresponding to the plurality of channel strips. The invention can reduce power consumption of the oxide semiconductor TFT and improve and the stability in the winding state.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 18, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Qianyi Zhang
  • Patent number: 10741659
    Abstract: A semiconductor device comprising a first field insulating film around at least a part of a first fin type pattern and at least a part of a second fin type pattern, a second field insulating film between the first fin type pattern and the second fin type pattern and protruding from the first field insulating film and a first gate structure which extends over the first and second field insulating films in a second direction intersecting with a first direction, and includes a first portion on the first field insulating film, and a second portion on the second field insulating film, wherein a first width of the first portion of the first gate structure is greater than a second width of the second portion of the first gate structure.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Seop Yoon, Byoung Wook Jeong