Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a transistor, located on the base substrate, and including an active layer; and a data line, located between the active layer and the base substrate; the data line is connected with the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.

Abstract: According to one embodiment, a display device includes a switching element, a common electrode, an insulating film covering the common electrode, a first pixel electrode electrically connected to the switching element in a first contact hole penetrating the insulating film, and a transparent conductive film electrically connected to the common electrode in a second contact hole penetrating the insulating film. The first pixel electrode and the transparent conductive film are arranged in a first direction in a same layer. A size of the first contact hole and a size of the second contact hole are different from each other in planar view.

Abstract: A display device includes a substrate comprising a display part, a pad part, and a bending part between the display part and the pad part, a display layer disposed on a first surface of the display part and comprising pixels, a pad electrode disposed on a first surface of the pad part, and a metal layer disposed on a second surface of the display part and on a second surface of the pad part. The second surface of the display part is opposite to the first surface of the display part, and the second surface of the pad part is opposite to the first surface of the pad part. A thickness of the bending part is smaller than at least one of a thickness of the display part and a thickness of the pad part. A planar shape of the bending part is determined by the metal layer.

Abstract: The first layer includes a first gate electrode array disposed in the first direction to control the qubits of the qubit string, and a second gate electrode array disposed in the first direction to control the inter-qubit interaction of the interaction string. The second layer includes a third gate electrode array disposed in the second direction, and a fourth gate electrode array disposed in the second direction adjacently to the third gate electrode array. The third and the fourth gate electrode arrays control a part of the multiple qubits, and a part of the multiple inter-qubit interactions, respectively.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a composite gate dielectric, and a lower electrode layer disposed over the composite gate dielectric. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a graphene layer disposed between the lower electrode layer and the upper electrode layer. The composite gate dielectric includes a gate dielectric layer and a protection liner.

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).

Abstract: The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate, wherein the isolation structure includes a first dielectric layer in contact with the semiconductor substrate and a second dielectric layer over the first dielectric layer, wherein the first dielectric layer is between the second dielectric layer and the semiconductor substrate, the first dielectric layer comprises a bottom portion and a sidewall portion, and a thickness of the bottom portion is greater than a thickness of the sidewall portion.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Abstract: According to one embodiment, a display device includes a first substrate including a first transparent substrate, a switching element including an oxide semiconductor, an organic insulating film covering the switching element, a transparent electrode including a first aperture penetrating to an upper surface of the organic insulating film, an inorganic insulating film including a second aperture penetrating to the upper surface in the first aperture, and a pixel electrode electrically connected to the switching element, and a second substrate including a second transparent substrate and opposed to the first substrate.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: An embodiment of the present application discloses an array substrate and a manufacturing method thereof. The array substrate includes an underlay, an active layer, a gate electrode insulation layer, and a metal layer. A first through hole, second through holes, third through holes, and a fourth through hole are defined in the gate electrode insulation layer. The second through holes and third through holes are arranged at intervals such that partial regions of the active layer are shielded by the gate electrode insulation layer to prevent them from corrosion of an etching solution to guarantee a normal electrical connection of the active layer and a source electrode and a drain electrode and improve a yield rate of the array substrate.

Abstract: A transistor, an integrated semiconductor device, and methods of making the same are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: A method of manufacturing a display device includes providing a transistor on a light-emitting area of a substrate, patterning a first organic layer covering the transistor to provide a first insulating layer, providing a pixel electrode connected to the transistor, and patterning a second organic layer covering the first insulating layer and the pixel electrode to provide a second insulating layer which defines the light-emitting area. The first insulating layer includes a first area corresponding to the light-emitting area, and a second area outside the light-emitting area and having a thickness which is less than a thickness of the first area, within the light-emitting area, the second insulating layer covers edges of the pixel electrode and covers external lateral surfaces of the first area of the first insulating layer, and a height of the second insulating layer decreases along a direction from the first area to the second area.

Abstract: A semiconductor device includes a gate structure that is formed upon and around a channel fin. The device further includes a source or drain (S/D) region connected to the fin. A spacer liner is located upon a sidewall of the S/D region facing the gate structure. An air-gap spacer is located between the gate structure and the spacer liner. A spacer ear is located above the air-gap spacer between the gate structure and the spacer liner. The spacer ear may be formed by initially forming an inner spacer upon a sidewall of the gate structure and forming an outer spacer upon the inner spacer. The outer spacer may be recessed below the inner spacer and the spacer ear may be formed upon the recessed outer spacer. Subsequently, the inner spacer and outer spacer may be removed to form the air-gap spacer while retaining the spacer ear.

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).

Abstract: A display panel and a display device are disclosed. The display panel includes a first substrate and a second substrate that are aligned and bonded together, and further includes a spacer disposed between the first substrate and second substrate. One end of the spacer is disposed on the second substrate, and the other end faces the first substrate. The first substrate further includes a first limiting groove that is disposed on one side adjacent to the second substrate and that corresponds to a position of the spacer. The other end of the spacer extends into the first limiting groove. A first limiting protruding strip is disposed on a groove wall of the first limiting groove, and the surface of the first limiting protruding strip facing the spacer abuts against the side wall of the spacer, defining a gap between the spacer and the groove wall of the first limiting groove.

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: An organic light-emitting display device and a method of manufacturing the same are disclosed and these improve electrical connection between a cathode and an auxiliary electrode in order to reduce the resistance of the cathode that covers a plurality of sub-pixels, and may prevent lateral current leakage using the same structure.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.

Abstract: A temperature controlling apparatus includes a platen, a first and a second conduits, and a first and a second outlet thermal sensors. The first conduit includes a first inlet, a first outlet, and a first heater. A first fluid enters the first inlet and exits the first outlet, the first heater heats the first fluid to a first heating temperature, and the first fluid is dispensed on the platen. The second conduit includes a second inlet, a second outlet, and a second heater. A second fluid enters the second inlet and exits the second outlet, the second heater heats the second fluid to a second heating temperature, and the second fluid is dispensed on the platen. The first and the second outlet thermal sensors are respectively disposed at the first and the second outlets to sense temperatures of the first and the second fluid.

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.

Abstract: An electronic device is provided. The electronic device includes a supporting substrate, a flexible substrate disposed on the supporting substrate, a first conductive layer disposed on the flexible substrate, a second conductive layer disposed on the first conductive layer, a plurality of organic elements disposed between the first conductive layer and the second conductive layer, and an opening passing through the supporting substrate and exposing a portion of the flexible substrate. The first conductive layer alternately contacts the second conductive layer and the plurality of organic elements.

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

Abstract: A display device includes: a substrate; a thin film transistor structure disposed on the substrate and including a gate electrode and a drain electrode; and a data line disposed on the substrate. Herein, from a top view, the data line is separated from the drain electrode, an edge of the gate electrode overlaps the drain electrode, the edge has two ends, and a first direction is parallel to a connection line of the two ends. In addition, from the top view, the drain electrode has a first distance and a second distance, the first distance is a maximum distance of the drain electrode not overlapping the gate electrode in the first direction, the second distance is a maximum distance of the drain electrode overlapping the gate electrode in the first direction, and the first distance is greater than the second distance.

Abstract: An organic light-emitting display device includes: a substrate on which a display area and a non-display area surrounding the display area are defined, the display area includes a main area and at least one protruding area, and a plurality of pixels is in the display area; a first signal line on the substrate in the main area to provide signals to the plurality of pixels; a second signal line on the substrate in the protruding area to provide signals to the plurality of pixels; a compensation line on the substrate in the non-display area and electrically connected to the second signal line; and a bridge pattern over the second signal line and the compensation line in the non-display area and electrically connecting the second signal line with the compensation line, the bridge pattern including a double-bridge structure.

Abstract: The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.

Abstract: In a display device, a second wiring line extends in a display region and includes an imaginary straight line that extends from the second wiring line in an extension direction of the second wiring line and intersects with an opening of an edge cover. The second wiring line extends along the peripheral edge of the opening without intersecting with the opening of the edge cover.

Abstract: A display substrate, a display apparatus, and a manufacturing method for the display substrate are provided. The display substrate includes: a substrate and a plurality of pixel units arranged in an array on the substrate; the pixel unit includes a light emitting diode, a connecting metal pattern, and a thin film transistor arranged in sequence along a direction away from the substrate; the connecting metal pattern is conductively connected to a top electrode of the light emitting diode; an active layer of the thin film transistor is insulated and spaced from the connecting metal pattern, and the drain of the thin film transistor is conductively connected to the connecting metal pattern.

Abstract: A transistor, integrated semiconductor device and methods of making are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

Abstract: A method of processing a substrate includes: providing structures on a surface of a substrate; depositing a self-assembled monolayer (SAM) over the structures and the substrate, the SAM being reactive to a predetermined wavelength of radiation; determining a first pattern of radiation exposure, the first pattern of radiation exposure having a spatially variable radiation intensity across the surface of the substrate and the structures; exposing the SAM to radiation according to the first pattern of radiation exposure, the SAM being configured to react with the radiation; developing the SAM with a predetermined removal fluid to remove portions of the SAM that are not protected from the predetermined fluid; and depositing a spacer material on the substrate and the structures, the spacer material being deposited at varying thicknesses based on an amount of the SAM remaining on the surface of the substrate and the structures.