Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).

Abstract: A display panel and a display device are disclosed. The display panel includes a first substrate and a second substrate that are aligned and bonded together, and further includes a spacer disposed between the first substrate and second substrate. One end of the spacer is disposed on the second substrate, and the other end faces the first substrate. The first substrate further includes a first limiting groove that is disposed on one side adjacent to the second substrate and that corresponds to a position of the spacer. The other end of the spacer extends into the first limiting groove. A first limiting protruding strip is disposed on a groove wall of the first limiting groove, and the surface of the first limiting protruding strip facing the spacer abuts against the side wall of the spacer, defining a gap between the spacer and the groove wall of the first limiting groove.

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: An organic light-emitting display device and a method of manufacturing the same are disclosed and these improve electrical connection between a cathode and an auxiliary electrode in order to reduce the resistance of the cathode that covers a plurality of sub-pixels, and may prevent lateral current leakage using the same structure.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.

Abstract: A temperature controlling apparatus includes a platen, a first and a second conduits, and a first and a second outlet thermal sensors. The first conduit includes a first inlet, a first outlet, and a first heater. A first fluid enters the first inlet and exits the first outlet, the first heater heats the first fluid to a first heating temperature, and the first fluid is dispensed on the platen. The second conduit includes a second inlet, a second outlet, and a second heater. A second fluid enters the second inlet and exits the second outlet, the second heater heats the second fluid to a second heating temperature, and the second fluid is dispensed on the platen. The first and the second outlet thermal sensors are respectively disposed at the first and the second outlets to sense temperatures of the first and the second fluid.

Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

Abstract: An electronic device is provided. The electronic device includes a supporting substrate, a flexible substrate disposed on the supporting substrate, a first conductive layer disposed on the flexible substrate, a second conductive layer disposed on the first conductive layer, a plurality of organic elements disposed between the first conductive layer and the second conductive layer, and an opening passing through the supporting substrate and exposing a portion of the flexible substrate. The first conductive layer alternately contacts the second conductive layer and the plurality of organic elements.

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

Abstract: A display device includes: a substrate; a thin film transistor structure disposed on the substrate and including a gate electrode and a drain electrode; and a data line disposed on the substrate. Herein, from a top view, the data line is separated from the drain electrode, an edge of the gate electrode overlaps the drain electrode, the edge has two ends, and a first direction is parallel to a connection line of the two ends. In addition, from the top view, the drain electrode has a first distance and a second distance, the first distance is a maximum distance of the drain electrode not overlapping the gate electrode in the first direction, the second distance is a maximum distance of the drain electrode overlapping the gate electrode in the first direction, and the first distance is greater than the second distance.

Abstract: An organic light-emitting display device includes: a substrate on which a display area and a non-display area surrounding the display area are defined, the display area includes a main area and at least one protruding area, and a plurality of pixels is in the display area; a first signal line on the substrate in the main area to provide signals to the plurality of pixels; a second signal line on the substrate in the protruding area to provide signals to the plurality of pixels; a compensation line on the substrate in the non-display area and electrically connected to the second signal line; and a bridge pattern over the second signal line and the compensation line in the non-display area and electrically connecting the second signal line with the compensation line, the bridge pattern including a double-bridge structure.

Abstract: The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.

Abstract: A display substrate, a display apparatus, and a manufacturing method for the display substrate are provided. The display substrate includes: a substrate and a plurality of pixel units arranged in an array on the substrate; the pixel unit includes a light emitting diode, a connecting metal pattern, and a thin film transistor arranged in sequence along a direction away from the substrate; the connecting metal pattern is conductively connected to a top electrode of the light emitting diode; an active layer of the thin film transistor is insulated and spaced from the connecting metal pattern, and the drain of the thin film transistor is conductively connected to the connecting metal pattern.

Abstract: In a display device, a second wiring line extends in a display region and includes an imaginary straight line that extends from the second wiring line in an extension direction of the second wiring line and intersects with an opening of an edge cover. The second wiring line extends along the peripheral edge of the opening without intersecting with the opening of the edge cover.

Abstract: A transistor, integrated semiconductor device and methods of making are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

Abstract: A method of processing a substrate includes: providing structures on a surface of a substrate; depositing a self-assembled monolayer (SAM) over the structures and the substrate, the SAM being reactive to a predetermined wavelength of radiation; determining a first pattern of radiation exposure, the first pattern of radiation exposure having a spatially variable radiation intensity across the surface of the substrate and the structures; exposing the SAM to radiation according to the first pattern of radiation exposure, the SAM being configured to react with the radiation; developing the SAM with a predetermined removal fluid to remove portions of the SAM that are not protected from the predetermined fluid; and depositing a spacer material on the substrate and the structures, the spacer material being deposited at varying thicknesses based on an amount of the SAM remaining on the surface of the substrate and the structures.

Abstract: A sterilization structure, a sterilization board, and a display device are disclosed. The sterilization structure includes an active layer, wherein, one surface of the active layer has an exposed region, and a material of the active layer includes a laser-induced graphene material.

Abstract: The display device may include a substrate; at least one pixel along a first direction on the substrate and including first, second, and third emission areas, in each of which a plurality of light emitting elements are provided; a light blocking pattern corresponding to an area between the first to third emission areas; and a color filter layer including a first color filter pattern provided on the first emission area, a second color filter pattern provided on the second emission area, and a third color filter pattern provided on the third emission area. Here, the pixel may include a first storage capacitor, a second storage capacitor, and a third storage capacitor on the substrate and corresponding to one of the first to third color filter patterns.

Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

Abstract: A method for growing a transition metal dichalcogenide layer involves arranging a substrate having a first transition metal contained pad is arranged in a chemical vapor deposition chamber. A chalcogen contained precursor is arranged upstream of the substrate in the chemical vapor deposition chamber. The chemical vapor deposition chamber is heated for a period of time during which a transition metal dichalcogenides layer, containing transition metal from the first transition metal contained pad and chalcogen from the chalcogen contained precursor, is formed in an area adjacent to the first transition metal contained pad.

Abstract: A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: The present invention provides a mask, a display panel, and a method for manufacturing thereof. The display panel includes a display area and a peripheral area surrounding the display area, and the peripheral area comprises a wiring area and a bonding area. The wiring area is provided with a first ground wiring. In the present invention, the first ground wiring is routed through a double-layer or multi-layer metal wiring, and an electrostatic discharge (ESD) protection effect can be achieved in the use of a finished product.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

Abstract: A semiconductor structure includes a substrate having first and second wells of first and second conductivity types respectively. From a top view, the first and second wells extend lengthwise along a first direction, the first and second wells each includes a protruding section that protrudes along a second direction perpendicular to the first direction and a recessed section that recedes along the second direction. The protruding section of the first well fits into the recessed section of the second well, and vice versa. The semiconductor structure further includes first source/drain features over the protruding section of the first well; second source/drain features over the second well; third source/drain features over the protruding section of the second well; and fourth source/drain features over the first well. The first and second source/drain features are of the first conductivity type. The third and fourth source/drain features are of the second conductivity type.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate including an NMOS region and a PMOS region, forming an isolation layer on the substrate, forming initial hard mask layers on the isolation layer, and forming hard mask layers by removing a number of initial hard mask layers from the initial hard mask layers. The method also includes forming openings in the isolation layer in the NMOS region by removing portions of the isolation layer covered by the hard mask layers in the NMOS region, forming first fins in the openings in the isolation layer in the NMOS region, forming openings in the isolation layer in the PMOS region by removing portions of the isolation layer covered by the hard mask layers in the PMOS region, and forming second fins in the openings in the isolation layer in the PMOS region.

Abstract: The present application provides a driving circuit and a display device. The driving circuit includes a circuit unit including a thin-film transistor, which includes a patterned member; a capacitor, connected to at least one end of the thin-film transistor of the circuit unit, the capacitor includes an electrode plate; and a redundant patterned member, the redundant patterned member, the electrode plate and the patterned member located in a same conductive layer, the redundant patterned member connected between the patterned member and the electrode plate.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.

Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

Abstract: A display substrate includes a scan driving circuit and a display area arranged on a substrate, the scan driving circuit includes shift register units; the scan driving circuit includes a first/second voltage signal line and a first/second clock signal line extending along a first direction; the display area includes at least one driving transistor configured to drive a light emitting element for display; at least one shift register unit includes a signal output line, a first capacitor, and at least two transistors coupled to a same electrode plate of the first capacitor; the signal output line extends along a second direction intersecting the first direction; gate electrodes of the at least two transistors are respectively coupled to the same electrode plate of the first capacitor, and the first capacitor and the at least two transistors are arranged on a same side of the first voltage signal line.

Abstract: The present disclosure provides a manufacturing method of a display backplane which includes a base substrate having first, second and third portions. The manufacturing method includes: forming a flexible layer extending from the first portion to and covering the second and third portions; forming a pixel driving circuit on the first portion and a backlight circuit on the third portion, wherein a part of a film layer of the pixel driving circuit extends from the first portion to and covers the second and third portions; removing a film layer on a side of the flexible layer away from the base substrate and on the second portion; separating the flexible layer from the second and third portions; removing the second and third portions; and bending a film layer separated from the third portion to a side of the first portion away from the flexible layer.

Abstract: A method of manufacturing a low temperature polysilicon thin film, including the steps of: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; roughening a surface of the silicon layer to form an uneven surface as a recrystallization growth space; and annealing the silicon layer to form a polysilicon layer, and a partial silicon material of the polysilicon layer is formed on the recrystallization growth space.

Abstract: A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area pf the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device.

Abstract: Embodiments of the present disclosure provide a touch substrate, including: a plurality of touch electrodes arranged in a same layer and insulated from each other, the touch electrodes being configured to sense touch signals; and a plurality of first touch signal lines configured to transmit the touch signals, each touch electrode being connected with a corresponding first touch signal line via a first via hole. The touch substrate further includes a plurality of second touch signal lines, wherein an extension direction of the second touch signal lines is different from that of the first touch signal lines, and each touch electrode is connected with a corresponding second touch signal line via a second via hole. In particular, the second touch signal lines corresponding to different touch electrodes are disconnected from each other. Embodiments of the present disclosure further provide a touch screen including the touch substrate.

Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.

Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

Abstract: Methods and materials for growing TMD materials on substrates and making semiconductor devices are described. Metal contacts may be created prior to conducting a deposition process such as chemical vapor deposition (CVD) to grow a TMD material, such that the metal contacts serve as the seed/catalyst for TMD material growth. A method of making a semiconductor device may include conducting a lift-off lithography process on a substrate to produce a substrate having metal contacts deposited thereon in lithographically defined areas, and then growing a TMD material on the substrate by a deposition process to make a semiconductor device. Further described are semiconductor devices having a substrate with metal contacts deposited thereon in lithographically defined areas, and a TMD material on the substrate, where the TMD material is a continuous, substantially uniform monolayer film between and on the metal contacts, where the metal contacts are chemically bonded to the TMD material.

Abstract: A method is disclosed that includes operations as follows: after forming an ion-implanted layer disposed between an epitaxial layer and a first semiconductor substrate, bounding the epitaxial layer to a bonding oxide layer without forming any layer between the epitaxial layer and the bonding oxide layer; and removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping a remaining portion of the ion-implanted layer on the epitaxial layer.

Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Abstract: A display device capable of reducing a non-display area includes a substrate including at least one hole area disposed within an emission area, and at least one blocking hole passing through inorganic insulating films disposed beneath a light emitting element while including upper and lower insulating films made of different materials. Side surfaces of the upper inorganic insulating film exposed through the blocking hole protrude beyond side surfaces of the lower inorganic insulating film exposed through the blocking hole, respectively. Accordingly, it is possible to minimize a bezel area, which is a non-display area, and to disconnect a light emitting stack by the blocking hole.

Abstract: A plasmonic field-enhanced photodetector is disclosed. The photodetector absorbs surface plasmon polaritons (SPPs) by using a light absorbing layer having a conduction band and a valence band in which an energy is split, the SPPs being generated by combining surface plasmons (SPs) with photons of a light wave, and generates photocurrent based on the absorbed SPPs.

Abstract: Semiconductor FET devices with bottom dielectric isolation and high-? first are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; source and drains alongside the active layers; and gates, offset from the source and drains by inner spacers, surrounding a portion of each of the active layers, wherein the gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers. A method of forming a semiconductor FET device is also provided.

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.