Having Insulated Gate Patents (Class 438/151)
  • Patent number: 11107905
    Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 11088248
    Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chun Hsiung Tsai
  • Patent number: 11049951
    Abstract: A coating liquid for forming an oxide or oxynitride insulator film, the coating liquid including: A element; at least one selected from the group consisting of B element and C element; and a solvent, wherein the A element is at least one selected from the group consisting of Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B element is at least one selected from the group consisting of Ga, Ti, Zr, and Hf, the C element is at least one selected from the group consisting of Group 2 elements in a periodic table, and the solvent includes at least one selected from the group consisting of an organic solvent having a flash point of 21° C. or more but less than 200° C. and water.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Ryoichi Saotome, Sadanori Arae, Minehide Kusayanagi, Yuichi Ando
  • Patent number: 11031348
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface and a back surface, at least one semiconductor device, a first TSV disposed in the substrate, an insulating layer surrounding the first TSV, a shielding layer surrounding the insulating layer, and a second TSV adjacent to the first TSV. The semiconductor device is disposed in a device region of the substrate. The first TSV is exposed by the front surface and the back surface of the substrate. The insulating layer includes an electrically insulating material. The shielding layer includes an electrically conductive material coupled to ground through a ground layer. The second TSV is exposed by the front surface and the back surface of the substrate.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 8, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Tse-Yao Huang
  • Patent number: 11011552
    Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Yong Park, Tae-Gon Kim
  • Patent number: 11004874
    Abstract: The disclosure discloses a thin film transistor, a method for fabricating the same, an array substrate, and a display panel. The thin film transistor includes: a first conductive layer on a base substrate, a first insulation layer on a side of the first conductive layer facing away from the base substrate, and a second conductive layer on a side of the first insulation layer facing away from the first conductive layer, wherein an active layer is arranged on a side of the first insulation layer facing the first conductive layer, and/or a side thereof facing the second conductive layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 11, 2021
    Assignees: Chongqing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hongru Zhou, Yongliang Zhao, Zhonghao Huang, Zhaojun Wang, Chao Zhang
  • Patent number: 10957551
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10957536
    Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 23, 2021
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10957796
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani, Abhijit Jayant Pethe
  • Patent number: 10923475
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heonjong Shin, Sunghun Jung, Minchan Gwak, Yongsik Jeong, Sangwon Jee, Sora You, Doohyun Lee
  • Patent number: 10877340
    Abstract: A TFT array substrate, a fabrication method thereof and a LCD panel are provided. The TFT array substrate adopts the transparent silicon-based nanolines to form the semiconductor layer of the TFT, adopts the transparent material to form the gate electrode of the TFT, and has the pixel electrode covering the region occupied by the TFT, such that the illumination emitted by the backlight can pass through the whole TFT and the pixel electrode, i.e. the pixel portion occupied by the TFT 20 is also transparent, and thus the aperture ratio can be significantly increased to enhance transmittance and display effect of high PPI LCD panels.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 29, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Hongyuan Xu
  • Patent number: 10868121
    Abstract: A method and apparatus, the method comprising: forming a layer of two dimensional material (23), in particular graphene, on a first release layer; forming, possibly a (gate) insulating layer (35), and at least two, preferably three, electrodes (25); forming a second release layer overlaying at least a portion of the layer of two dimensional material; providing a mouldable polymer (24, 26, 28) overlaying the at least two electrodes and the second release layer; and removing the first and second release layers to provide a cavity (29) between the mouldable polymer (26) and the layer of two dimensional material (23).
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 15, 2020
    Assignee: Nokia Technologies Oy
    Inventors: Darryl Cotton, Yinglin Liu, Adam Robinson, Alexander Bessonov, Richard White
  • Patent number: 10868147
    Abstract: A method of forming a transistor from a stack of layers comprising at least one insulating layer topped by at least one active layer and at least one first and one second insulating trench defining in the active layer a reception area for receiving the transistor, the transistor comprising a conduction channel formed at least partially in the active layer, the method comprising at least the following steps: forming a grid stack extending over at least the conduction channel; forming a source zone and a drain zone; wherein the formation of the grid stack is carried out in such a way as to provide at least a first and a second portion of the reception zone, not covered by the grid stack.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: December 15, 2020
    Assignee: X-FAB FRANCE
    Inventor: Nicolas Pons
  • Patent number: 10854636
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 1, 2020
    Inventors: Koji Ono, Hideomi Suzawa
  • Patent number: 10847111
    Abstract: A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Jeon, Hyung Guel Kim, Dong Hwan Kim
  • Patent number: 10833074
    Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Cheng-Han Lee, Yi-Min Huang
  • Patent number: 10825716
    Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: November 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Moser, Matteo Dainese, Matthias Kuenle, Hans-Joachim Schulze
  • Patent number: 10818665
    Abstract: An array of recessed access devices comprises islands comprising semiconductive material surrounded by insulating material. The insulating material has a bottom adjacent individual of the islands. Rows of transistor gate lines individually cross multiple of the islands within the semiconductive material and cross within the insulating material between the individual islands. Individual of the gate lines are operatively adjacent a channel region of individual of the transistors within the individual islands and interconnect the transistors in that row. The individual transistors comprise a pair of source/drain regions on opposite sides of the individual gate lines in the individual islands. A lower portion of the individual islands proximate individual of the bottoms of the insulating material has less horizontal area than an uppermost portion of the individual islands. Additional embodiments are disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10818756
    Abstract: A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Patent number: 10770310
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Yukinori Shima, Masahiko Hayakawa, Takashi Hamochi, Suzunosuke Hiraishi
  • Patent number: 10770487
    Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 8, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Juncheng Xiao, Chao Tian
  • Patent number: 10749036
    Abstract: The invention provides an oxide semiconductor TFT and manufacturing method thereof. The oxide semiconductor TFT comprises: a substrate, a gate on the substrate, a gate insulating layer on the gate and substrate, an oxide semiconductor layer on the gate insulating layer, and a barrier layer on the semiconductor layer, and a source and a drain on the oxide semiconductor layer and gate insulating layer; the oxide semiconductor layer comprising: a channel region and two contact regions respectively located at two sides of the channel region, and the barrier layer being located on the channel region; the channel region comprising a plurality of channel strips spaced apart in a channel width direction, and the barrier layer comprising a plurality of barrier strips respectively corresponding to the plurality of channel strips. The invention can reduce power consumption of the oxide semiconductor TFT and improve and the stability in the winding state.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 18, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Qianyi Zhang
  • Patent number: 10741659
    Abstract: A semiconductor device comprising a first field insulating film around at least a part of a first fin type pattern and at least a part of a second fin type pattern, a second field insulating film between the first fin type pattern and the second fin type pattern and protruding from the first field insulating film and a first gate structure which extends over the first and second field insulating films in a second direction intersecting with a first direction, and includes a first portion on the first field insulating film, and a second portion on the second field insulating film, wherein a first width of the first portion of the first gate structure is greater than a second width of the second portion of the first gate structure.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Seop Yoon, Byoung Wook Jeong
  • Patent number: 10741606
    Abstract: An image sensor includes a plurality of pixels arranged in matrix, and each pixel includes a first TFT having a first gate electrode and a second gate electrode that are arranged on a substrate, a second TFT, and a photoelectric conversion element that has a first electrode electrically connected to a first surface of an a-Si thin film and the second gate electrode of the first TFT and a second electrode connected to a second control line, and that is arranged above the first TFT so as to be superposed on the first TFT in an laminated direction. Provided is a gas barrier film that is positioned between the first and the second TFTs and the photoelectric conversion element and that prevents hydrogen from permeating into the first and the second TFTs, the first electrode and the second gate electrode are constructed by the same layer, and the gas barrier film is not provided with an aperture in each of the pixels.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 11, 2020
    Assignee: TIANMA MICROELECTRONICS CO., LTD.
    Inventor: Hiroyuki Sekine
  • Patent number: 10707236
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a light-shielding pattern layer, a buffer layer, an active layer, a gate insulating layer and a gate electrode on a base substrate, which are away from the base substrate in sequence; depositing an amorphous silicon (a-Si) film on the base substrate in a temperature range of 15-150° C.; forming a first interlayer dielectric (ILD) at least disposed above the active layer by patterning the a-Si film; forming through holes in the first ILD, through which a source contact region and a drain contact region of the active layer are exposed; and forming a source electrode and a drain electrode on the first ILD, which are respectively connected with the source contact region and the drain contact region via the through holes.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang, Fengjuan Liu
  • Patent number: 10707353
    Abstract: A TFT, a method for fabricating the same, a display substrate, and a display device are disclosed. The TFT comprises a substrate, a gate, a gate insulating layer, semiconductor layer, a source, and a drain. The gate comprises a rough surface on a side facing the semiconductor layer. Since the surface of gate is uneven, the light which has been reflected on the surface of gate will no longer be reflected, or will be directly scattered to other directions. The incident light from the backlight source cannot impinge onto the semiconductor layer by continuous reflection. This reduces the possibility that the semiconductor layer is irradiated by light, and improves stability of TFT.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Qin
  • Patent number: 10700178
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10692973
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani, Harold W. Kennel
  • Patent number: 10672617
    Abstract: There is provided an etching method which includes supplying an etching gas including an H2 gas or an NH3 gas to a target substrate having a germanium portion in an excited state; and etching the germanium portion.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Murakami, Takahiro Miyahara
  • Patent number: 10663815
    Abstract: Provided is a substrate wiring path inspection system whereby, at the time of performing electrical inspection of a wiring path of a substrate having a surface on which a plurality of electrically independent wiring paths are formed, whether a probe is reliably electrically connected to the wiring path can be easily checked at a low equipment cost. The present invention is configured by being provided with: a probe set 2 to be in contact with end portions of a plurality of wiring paths 31-34 formed on a substrate 1; a flexible conductor 9 that short-circuits the wiring paths 31-34 at portions excluding the end portions; and an inspection device 4 which is provided with a determination section 8 that determines whether a resistance value between a pair of wiring lines is lower than a predetermined value, said pair of wiring lines having been selected from among the wiring lines 31-34 short-circuited by the flexible conductor 9.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 26, 2020
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Naoki Matsumoto
  • Patent number: 10629646
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 21, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Tzu Yin Chiu, Chong Wang, Haifang Zhang, Xuanjie Liu
  • Patent number: 10629739
    Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Tek Po Rinus Lee, Scott Beasor
  • Patent number: 10622481
    Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
  • Patent number: 10615051
    Abstract: In an embodiment, there is provided a method of manufacturing a thin-film transistor. The method includes steps of: forming a gate, a gate insulator layer and an active layer on a base substrate, wherein, the gate and the active layer are provided at upper and lower sides of the gate insulator layer, respectively, and the active layer contains impurity ions therein; and, while implementing an annealing on the active layer, applying a voltage between the active layer and the gate to generate an electrical field therebetween, a direction of the electrical field being configured such that the impurity ions move from the active layer into the gate insulator layer. Meanwhile, there are also provided a thin-film transistor, an array substrate and a display apparatus.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tongshang Su, Dongfang Wang, Jun Liu, Leilei Cheng, Wei Li, Qinghe Wang, Yang Zhang, Guangcai Yuan
  • Patent number: 10615193
    Abstract: An array substrate, a method for manufacturing the same, a display panel, and a display device are provided. In the method for manufacturing an array substrate provided by an embodiment of the present disclosure, the annealing process for the first active layer in the pixel area is performed by a high temperature required in the dehydrogenation process for the second active layer in the peripheral area.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 7, 2020
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Bingqiang Gui, Lianjie Qu, Yonglian Qi, Hebin Zhao, Xiaogai Chun
  • Patent number: 10611962
    Abstract: An etchant composition is presented. The composition includes: 18 wt % to 25 wt % of a first organic acid compound; 15 wt % to 20 wt % of a second organic acid compound; 8.1 wt % to 9.9 wt % of an inorganic acid compound; 1 wt % to 4.9 wt % of a sulfonic acid compound; 10 wt % to 20 wt % of a hydrogen sulfate salt compound; 1 wt % to 5 wt % of a nitrogen-containing dicarbonyl compound; 1 wt % to 5 wt % of an amino acid derivative compound; 0.1 wt % to 2 wt % of an iron-containing oxidizing agent compound; and a balance amount of water.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 7, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Hee Park, Ki Tae Kim, Jin Seock Kim, Gyu-Po Kim, Hyun-Cheol Shin, Dae-Woo Lee, Sang-Hyuk Lee
  • Patent number: 10600915
    Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 24, 2020
    Assignee: National Applied Research Laboratories
    Inventors: Wen-Hsien Huang, Jia-Min Shieh, Chang-Hong Shen
  • Patent number: 10593710
    Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 10580799
    Abstract: According to one embodiment, a thin film transistor includes an oxide semiconductor layer provided above an insulating substrate and including a channel region between a source region and a drain region, a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region, a gate electrode provided on the first insulating film, a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal, a second protective film provided on the first protective film and a third protective film provided on the second protective film, as an insulating film containing a metal.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 3, 2020
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Eiichi Sato, Masanori Miura
  • Patent number: 10566352
    Abstract: A method of manufacturing an array substrate is provided. The method divides an array substrate into a curing area and a stretchable area. A metal wiring corresponding to the stretchable area is made of a flexible conductive material, so as to reduce disconnection risk of the display panel during bending.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 18, 2020
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Hui Xia
  • Patent number: 10559639
    Abstract: Disclosed are an organic light-emitting display device and a method for manufacturing the same. In the organic light-emitting display device, a switching thin film field-effect transistor comprises a first active layer for reducing a sub-threshold swing of a transfer characteristic curve of the switching thin film field-effect transistor; and a driving thin film field-effect transistor comprises a second active layer for increasing a sub-threshold swing of a transfer characteristic curve of the drive film field-effect transistor.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 11, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Longqiang Shi
  • Patent number: 10559601
    Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 11, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tongshang Su, Jun Cheng, Ce Zhao, Bin Zhou, Dongfang Wang, Guangcai Yuan
  • Patent number: 10535743
    Abstract: A vertical power semiconductor component includes a semiconductor chip, the semiconductor chip having a top main surface and a bottom main surface. Each of said top main surface and said bottom main surface is in a heat exchanging relationship with a top metallization layer and a bottom metallization each of which serving as a heat sink. Each of said top metallization layer and said bottom metallization layer have a layer thickness of at least 15 ?m and have a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. Each of said top metallization layer and said bottom metallization layer serving as a heat sink contacts the respective main surface via a respective diffusion barrier layer.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Hans-Joachim Schulze
  • Patent number: 10529717
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Patent number: 10505014
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 10497759
    Abstract: An OLED display panel includes a cover and a backplane, a plurality of color filter (CF) units are arranged in an array on the cover; auxiliary cathodes are filled into gaps among the CF units; the auxiliary cathodes include a black matrix, a buffer layer and a metal layer; a planarization layer is disposed on the auxiliary cathodes and the CF units; a plurality of openings are disposed in the planarization layer at locations corresponding to the auxiliary cathodes; a plurality of spacers are disposed on the planarization layer at locations corresponding to the auxiliary cathodes; the spacers abut against and support the cover and the backplane; a transparent electrode layer is disposed on the planarization layer and the spacers and is communicated with the auxiliary cathodes via the openings; and the plurality of CF units of the cover and pixel regions of the backplane are oppositely arranged.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 3, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang, Fengjuan Liu
  • Patent number: 10468489
    Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Patrick Morrow, Kerryann Foley, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10468528
    Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Patent number: 10424674
    Abstract: To provide a liquid crystal display device suitable for a thin film transistor which uses an oxide semiconductor. In a liquid crystal display device which includes a thin film transistor including an oxide semiconductor layer, a film having a function of attenuating the intensity of transmitting visible light is used as an interlayer film which covers at least the oxide semiconductor layer. As the film having a function of attenuating the intensity of transmitting visible light, a coloring layer can be used and a light-transmitting chromatic color resin layer is preferably used. An interlayer film which includes a light-transmitting chromatic color resin layer and a light-blocking layer may be formed in order that the light-blocking layer is used as a film having a function of attenuating the intensity of transmitting visible light.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Ishitani, Daisuke Kubota
  • Patent number: 10418252
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu