Having Insulated Gate Patents (Class 438/151)
  • Patent number: 10367062
    Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Isaac Lauer, Nicolas J. Loubet
  • Patent number: 10367017
    Abstract: An array substrate and a method of manufacturing the array substrate are provided. The method includes providing a substrate, sequentially forming a light-shielding layer, a buffer layer, an active layer, a source, a drain, a gate insulating layer, and a gate on the substrate, performing a first conductorization process on a corresponding region of the active layer opposite to the source and the drain, and performing a second conductorization process on another corresponding region of the active layer between the source and the gate and between the drain and the gate.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 30, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Hongyuan Xu
  • Patent number: 10355035
    Abstract: A manufacturing method of the back-channel-etched (BCE) TFT substrate, able to prevent the passivation layer from curling up and forming bubbles, while not causing damaging to the channel region of the active layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 16, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chunsheng Jiang
  • Patent number: 10347657
    Abstract: A complimentary metal-oxide-semiconductor (CMOS) device includes a wafer having a bulk semiconductor layer. A fin-type semiconductor device is formed on a first portion of the wafer. The CMOS devices also includes a nanosheet semiconductor device formed on a second portion of the wafer different from the first portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10347721
    Abstract: There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: July 9, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Laurent Grenouillet, Raluca Tiron
  • Patent number: 10340291
    Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuo Tsuboi, Yoshiki Yamamoto
  • Patent number: 10319679
    Abstract: A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ILD layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ILD layer, in which a width of the second portion is greater than a width of the first portion.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Mengkai Zhu
  • Patent number: 10312278
    Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a pixel region formed in a substrate and a storage region formed in the substrate and adjacent to the pixel region. The FSI image sensor device structure includes a storage gate structure formed over the storage region, and the storage gate structure includes a top surface and sidewall surfaces. The FSI image sensor device structure includes a metal shield structure formed on the storage gate structure, and the top surface and the sidewall surfaces of the storage gate structure are covered by the metal shield structure.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Kai Tsao, Shih-Pei Chou, Jiech-Fun Lu
  • Patent number: 10304876
    Abstract: This disclosure relates to the field of display technologies, and discloses a method for manufacturing an array substrate, an array substrate, a grayscale mask plate and a display device. The method includes forming a transparent conductive layer and a metal layer sequentially on a base substrate. A photoresist pattern is formed on the base: substrate on which the transparent conductive layer and the metal layer have been formed The transparent conductive layer and the metal layer corresponding to a photoresist-free region are removed. The photoresist in a second photoresist region is removed. The metal layer corresponding to the second photoresist region is removed to expose a pixel electrode. Additionally, the photoresist in a first photoresist region is removed to expose a first electrode, a second electrode and a first data line.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 28, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yiping Dong, Lei Zhang, Tianyou Gao
  • Patent number: 10283367
    Abstract: Provided is a hydrogenation annealing method using a microwave, which performs hydrogenation annealing at a low temperature and with low power in a manufacturing process of a thin film transistor (TFT) for a display device. The hydrogenation annealing method is constituted by a loading step of loading a device requiring hydrogenation annealing into a chamber and an annealing step of irradiating a microwave having a frequency in an industrial scientific medical (ISM) band into the chamber into which the device is loaded. As hydrogenation annealing is performed at a low temperature by using the microwave for an oxide semiconductor TFT or LTPS having very large electron mobility, high integrated energy is transmitted to the device by the microwave, thereby implementing recoupling of hydrogen atoms which have been performed only at a high temperature, even at a low temperature.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: May 7, 2019
    Assignee: CMTECH21 Co., Ltd.
    Inventors: Hi Chang Kim, Won-Ju Cho
  • Patent number: 10276715
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 10269906
    Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The contact is electrically connected to the source/drain feature. The gate spacer is disposed on a sidewall of the gate structure and between the gate structure and the contact. The contact spacer is disposed on the gate spacer and on a sidewall of the contact. An interface is formed between the gate spacer and the contact spacer, and a bottom surface of the contact spacer is in contact with the contact.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Po-Hsueh Li
  • Patent number: 10263018
    Abstract: Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality of signal lines arranged adjacent to each other at the same layer; and at least one redundant wire at a different layer from the signal lines, wherein each redundant wire corresponds to two adjacent signal lines, and a positive projection of the each redundant wire onto the layer where the signal lines are located covers a part or all of a gap between the two adjacent signal lines corresponding to the each redundant wire.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chunping Long
  • Patent number: 10254866
    Abstract: A display device, including a first transparent magnetic layer; a display panel on the first transparent magnetic layer; an upper member on the display panel; and a second transparent magnetic layer on the upper member, the second transparent magnetic layer being penetrated by light.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Hwa Choi, Seung-Bae Lee
  • Patent number: 10256242
    Abstract: A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Etron Technology, Inc.
    Inventor: Li-Ping Huang
  • Patent number: 10224350
    Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sanghoon Kim
  • Patent number: 10217952
    Abstract: The present disclosure relates to a nano-scale transistor. The nano-scale transistor includes a source electrode, a drain electrode, a gate electrode and a nano-heterostructure. The nano-heterostructure is electrically coupled with the source electrode and the drain electrode. The gate electrode is insulated from the nano-heterostructure, the source electrode and the drain electrode via an insulating layer. The nano-heterostructure includes a first carbon nanotube, a second carbon nanotube and a semiconductor layer. The semiconductor layer includes a first surface and a second surface opposite to the first surface. The first carbon nanotube is located on the first surface, the second carbon nanotube is located on the second surface.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: February 26, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10217682
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 10204798
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Junichi Koezuka, Takashi Hamochi, Yasuharu Hosaka
  • Patent number: 10199406
    Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate manufacturing method comprises: forming a source electrode and a drain electrode on a gate insulating layer; forming photoresist above the gate insulating layer and the source electrode and the drain electrode; etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode; and forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., SHANGHAI JIAO TONG UNIVERSITY
    Inventors: Wei Huang, Jiaqing Zhao, Linrun Feng, Wei Tang, Xiaojun Guo
  • Patent number: 10153159
    Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Seyoung Kim, Yun Seog Lee, Devendra Sadana, Joel de Souza
  • Patent number: 10141352
    Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhanfeng Cao, Feng Zhang, Bin Zhang, Xiaolong He, Zhengliang Li, Wei Zhang, Feng Guan, Jincheng Gao
  • Patent number: 10115718
    Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Manjunatha Prabhu, Mahadeva Iyer Natarajan
  • Patent number: 10096688
    Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer st
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Gi-gwan Park, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Patent number: 10083997
    Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sanghoon Kim
  • Patent number: 10068932
    Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: September 4, 2018
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tetsufumi Kawamura, Takeshi Sato, Mutsuko Hatano, Yoshiaki Toyota
  • Patent number: 10050130
    Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 14, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guo Bin Yu, Xiao Ping Xu
  • Patent number: 10049876
    Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10020227
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Patent number: 10014470
    Abstract: The present disclosure discloses an organic light emitting diode substrate and a method for manufacturing the same. In one embodiment the present disclosure, an organic light emitting diode substrate includes a display region in which an organic film layer that is formed by curing an ink layer is provided, and a border region located outside the display region and including an exposed area in which no organic film layer is provided. The organic light emitting diode substrate further includes: a barrier structure located in the border region and adapted for preventing the ink layer from coming into contact with a surface of the exposed area.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 3, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingying Song, Li Sun
  • Patent number: 9991319
    Abstract: A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung-Geun Cha, Sang-Ho Park, Hyun-Jae Na, Yoon-Ho Khang, Dae-Ho Kim
  • Patent number: 9978855
    Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Suzunosuke Hiraishi
  • Patent number: 9978600
    Abstract: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 22, 2018
    Assignee: Pragmatic Printing Ltd.
    Inventors: Richard Price, Catherine Ramsdale
  • Patent number: 9972542
    Abstract: Semiconductor devices and methods of forming the same include forming stacks of alternating layers of first channel material and second channel material in a first device region and a second device region. A first layer cap is formed at ends of the layers of first channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in the first device region. The second layer caps are etched away in the second device region. First source/drain regions are grown in the first device region from exposed ends of the layers of the first channel material. Second source/drain regions are grown in the second device region from exposed ends of the layers of the second channel material.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Wenyu Xu
  • Patent number: 9966393
    Abstract: A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate insulating layer on the gate line and the first auxiliary pattern forming a data line in the display region and a second auxiliary pattern in the non-display region over the gate insulating layer, wherein the data line crosses the gate line to define a pixel region forming a passivation layer on the data line and the second auxiliary pattern, and the passivation layer including first and second contact holes respectively exposing the first and second auxiliary patterns forming a planarization layer and a bridge pattern on the passivation layer forming a pixel electrode on the planarization layer and in the pixel region, and a connection pattern on the bridge pattern, wherein the connection pattern contacts the first and second auxiliary patterns.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 8, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jin-Su Kim, Sung-Jin Um, Jin-Hyung Jung
  • Patent number: 9960279
    Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: May 1, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Kosei Noda, Yuhei Sato, Yuta Endo
  • Patent number: 9954084
    Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9929276
    Abstract: A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. Specifically, a transistor having a multi-layer structure is manufactured in which a second oxide semiconductor film having a crystalline structure is stacked over a first oxide semiconductor film, and at least a third oxide semiconductor film is provided over the second oxide semiconductor film. When a buried channel is formed in the transistor, few oxygen vacancies are generated and the reliability of the transistor is improved.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9904134
    Abstract: A liquid crystal display device (LCD) includes gate lines and data lines extending in a first direction and a second direction crossing the first direction, respectively, on a substrate that includes a display region, where a plurality pixel regions are arranged in row lines and column lines, and a non-display region; a common transfer line extending in the second direction in the non-display region; a gate link line traversing the common transfer line and connected to the gate line at a connection region that is located at an inner side of the common transfer line; and a first blocking portion extending from the common transfer line to a space between the connection region and the display region.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 27, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Dong-Woo Park, Du-Hyun Na
  • Patent number: 9882062
    Abstract: A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: January 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9871139
    Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Joon Goo Hong, Dharmendar Reddy Palle, Mark S. Rodder
  • Patent number: 9847354
    Abstract: A thin film transistor liquid crystal display (TFT-LCD) array substrate is provided, including a base substrate; a first transparent conductive film formed on the base substrate; for each pixel unit of the array substrate the first transparent conductive film comprises at least a first part and a second part that do not contact with each other, and the first part is located under an area of the data line, without contacting the gate line and the common electrode line. When a data line in the array substrate has an open failure, this part of the transparent conductive film can be welded together with the data line using laser welding so as to repair the data line.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Baoquan Zhou
  • Patent number: 9806137
    Abstract: A display substrate includes a base substrate, a switching device on the base substrate and an alignment pattern. The switching device includes an active pattern, a gate insulation layer pattern partially covering the active pattern, a gate electrode on the gate insulation layer pattern, and a source electrode and a drain electrode electrically connected to the active pattern. The alignment pattern has a multi-layered structure and is spaced apart from the switching device on the base substrate. The alignment pattern includes materials which have different transmittances.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Ho Kim, Jong-Moo Huh
  • Patent number: 9805927
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: October 31, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shosuke Fujii, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 9780201
    Abstract: To improve the electrical characteristics of a semiconductor device including an oxide semiconductor, and to provide a highly reliable semiconductor device with a small variation in electrical characteristics. The semiconductor device includes a first insulating film, a first barrier film over the first insulating film, a second insulating film over the first barrier film, and a first transistor including a first oxide semiconductor film over the second insulating film. The amount of hydrogen molecules released from the first insulating film at a given temperature higher than or equal to 400° C., which is measured by thermal desorption spectroscopy, is less than or equal to 130% of the amount of released hydrogen molecules at 300° C. The second insulating film includes a region containing oxygen at a higher proportion than oxygen in the stoichiometric composition.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ando, Hidekazu Miyairi, Naoto Yamade, Asako Higa, Miki Suzuki, Yoshinori Ieda, Yasutaka Suzuki, Kosei Nei, Shunpei Yamazaki
  • Patent number: 9780229
    Abstract: An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 9754943
    Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: September 5, 2017
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Wei-Hsin Liu, Jui-Min Lee, Chia-Lung Chang
  • Patent number: 9754965
    Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9735380
    Abstract: A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer so as to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 15, 2017
    Assignee: NIKON CORPORATION
    Inventors: Shohei Koizumi, Takashi Sugizaki, Yusuke Kawakami
  • Patent number: 9704985
    Abstract: A semiconductor device of the present invention includes a semiconductor layer, a source region and a drain region formed in a surface of the semiconductor layer, both having a first conductivity type, a plurality of gate trenches each formed so as to extend across the source region and the drain region, in a plan view observed in a direction of a normal to the surface of the semiconductor layer, a channel region of a first conductivity type made of the semiconductor layer sandwiched by the gate trenches adjacent to each other, having a channel length along a direction extending from the drain region to the source region, and a gate electrode buried in the gate trench via a gate insulating film, and the channel region has a thickness in the plan view not more than two times a width of a depletion layer to be generated due to a built-in potential between the channel region and the gate electrode.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 11, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Yasushi Hamazawa