Having Insulated Gate Patents (Class 438/151)
  • Patent number: 10707236
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a light-shielding pattern layer, a buffer layer, an active layer, a gate insulating layer and a gate electrode on a base substrate, which are away from the base substrate in sequence; depositing an amorphous silicon (a-Si) film on the base substrate in a temperature range of 15-150° C.; forming a first interlayer dielectric (ILD) at least disposed above the active layer by patterning the a-Si film; forming through holes in the first ILD, through which a source contact region and a drain contact region of the active layer are exposed; and forming a source electrode and a drain electrode on the first ILD, which are respectively connected with the source contact region and the drain contact region via the through holes.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang, Fengjuan Liu
  • Patent number: 10707353
    Abstract: A TFT, a method for fabricating the same, a display substrate, and a display device are disclosed. The TFT comprises a substrate, a gate, a gate insulating layer, semiconductor layer, a source, and a drain. The gate comprises a rough surface on a side facing the semiconductor layer. Since the surface of gate is uneven, the light which has been reflected on the surface of gate will no longer be reflected, or will be directly scattered to other directions. The incident light from the backlight source cannot impinge onto the semiconductor layer by continuous reflection. This reduces the possibility that the semiconductor layer is irradiated by light, and improves stability of TFT.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Qin
  • Patent number: 10700178
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10692973
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani, Harold W. Kennel
  • Patent number: 10672617
    Abstract: There is provided an etching method which includes supplying an etching gas including an H2 gas or an NH3 gas to a target substrate having a germanium portion in an excited state; and etching the germanium portion.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Murakami, Takahiro Miyahara
  • Patent number: 10663815
    Abstract: Provided is a substrate wiring path inspection system whereby, at the time of performing electrical inspection of a wiring path of a substrate having a surface on which a plurality of electrically independent wiring paths are formed, whether a probe is reliably electrically connected to the wiring path can be easily checked at a low equipment cost. The present invention is configured by being provided with: a probe set 2 to be in contact with end portions of a plurality of wiring paths 31-34 formed on a substrate 1; a flexible conductor 9 that short-circuits the wiring paths 31-34 at portions excluding the end portions; and an inspection device 4 which is provided with a determination section 8 that determines whether a resistance value between a pair of wiring lines is lower than a predetermined value, said pair of wiring lines having been selected from among the wiring lines 31-34 short-circuited by the flexible conductor 9.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 26, 2020
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Naoki Matsumoto
  • Patent number: 10629739
    Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Tek Po Rinus Lee, Scott Beasor
  • Patent number: 10629646
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 21, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Tzu Yin Chiu, Chong Wang, Haifang Zhang, Xuanjie Liu
  • Patent number: 10622481
    Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
  • Patent number: 10615193
    Abstract: An array substrate, a method for manufacturing the same, a display panel, and a display device are provided. In the method for manufacturing an array substrate provided by an embodiment of the present disclosure, the annealing process for the first active layer in the pixel area is performed by a high temperature required in the dehydrogenation process for the second active layer in the peripheral area.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 7, 2020
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Bingqiang Gui, Lianjie Qu, Yonglian Qi, Hebin Zhao, Xiaogai Chun
  • Patent number: 10615051
    Abstract: In an embodiment, there is provided a method of manufacturing a thin-film transistor. The method includes steps of: forming a gate, a gate insulator layer and an active layer on a base substrate, wherein, the gate and the active layer are provided at upper and lower sides of the gate insulator layer, respectively, and the active layer contains impurity ions therein; and, while implementing an annealing on the active layer, applying a voltage between the active layer and the gate to generate an electrical field therebetween, a direction of the electrical field being configured such that the impurity ions move from the active layer into the gate insulator layer. Meanwhile, there are also provided a thin-film transistor, an array substrate and a display apparatus.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tongshang Su, Dongfang Wang, Jun Liu, Leilei Cheng, Wei Li, Qinghe Wang, Yang Zhang, Guangcai Yuan
  • Patent number: 10611962
    Abstract: An etchant composition is presented. The composition includes: 18 wt % to 25 wt % of a first organic acid compound; 15 wt % to 20 wt % of a second organic acid compound; 8.1 wt % to 9.9 wt % of an inorganic acid compound; 1 wt % to 4.9 wt % of a sulfonic acid compound; 10 wt % to 20 wt % of a hydrogen sulfate salt compound; 1 wt % to 5 wt % of a nitrogen-containing dicarbonyl compound; 1 wt % to 5 wt % of an amino acid derivative compound; 0.1 wt % to 2 wt % of an iron-containing oxidizing agent compound; and a balance amount of water.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 7, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Hee Park, Ki Tae Kim, Jin Seock Kim, Gyu-Po Kim, Hyun-Cheol Shin, Dae-Woo Lee, Sang-Hyuk Lee
  • Patent number: 10600915
    Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 24, 2020
    Assignee: National Applied Research Laboratories
    Inventors: Wen-Hsien Huang, Jia-Min Shieh, Chang-Hong Shen
  • Patent number: 10593710
    Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 10580799
    Abstract: According to one embodiment, a thin film transistor includes an oxide semiconductor layer provided above an insulating substrate and including a channel region between a source region and a drain region, a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region, a gate electrode provided on the first insulating film, a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal, a second protective film provided on the first protective film and a third protective film provided on the second protective film, as an insulating film containing a metal.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 3, 2020
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Eiichi Sato, Masanori Miura
  • Patent number: 10566352
    Abstract: A method of manufacturing an array substrate is provided. The method divides an array substrate into a curing area and a stretchable area. A metal wiring corresponding to the stretchable area is made of a flexible conductive material, so as to reduce disconnection risk of the display panel during bending.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 18, 2020
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Hui Xia
  • Patent number: 10559601
    Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 11, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tongshang Su, Jun Cheng, Ce Zhao, Bin Zhou, Dongfang Wang, Guangcai Yuan
  • Patent number: 10559639
    Abstract: Disclosed are an organic light-emitting display device and a method for manufacturing the same. In the organic light-emitting display device, a switching thin film field-effect transistor comprises a first active layer for reducing a sub-threshold swing of a transfer characteristic curve of the switching thin film field-effect transistor; and a driving thin film field-effect transistor comprises a second active layer for increasing a sub-threshold swing of a transfer characteristic curve of the drive film field-effect transistor.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 11, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Longqiang Shi
  • Patent number: 10535743
    Abstract: A vertical power semiconductor component includes a semiconductor chip, the semiconductor chip having a top main surface and a bottom main surface. Each of said top main surface and said bottom main surface is in a heat exchanging relationship with a top metallization layer and a bottom metallization each of which serving as a heat sink. Each of said top metallization layer and said bottom metallization layer have a layer thickness of at least 15 ?m and have a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. Each of said top metallization layer and said bottom metallization layer serving as a heat sink contacts the respective main surface via a respective diffusion barrier layer.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Hans-Joachim Schulze
  • Patent number: 10529717
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Patent number: 10505014
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 10497759
    Abstract: An OLED display panel includes a cover and a backplane, a plurality of color filter (CF) units are arranged in an array on the cover; auxiliary cathodes are filled into gaps among the CF units; the auxiliary cathodes include a black matrix, a buffer layer and a metal layer; a planarization layer is disposed on the auxiliary cathodes and the CF units; a plurality of openings are disposed in the planarization layer at locations corresponding to the auxiliary cathodes; a plurality of spacers are disposed on the planarization layer at locations corresponding to the auxiliary cathodes; the spacers abut against and support the cover and the backplane; a transparent electrode layer is disposed on the planarization layer and the spacers and is communicated with the auxiliary cathodes via the openings; and the plurality of CF units of the cover and pixel regions of the backplane are oppositely arranged.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 3, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang, Fengjuan Liu
  • Patent number: 10468489
    Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Patrick Morrow, Kerryann Foley, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10468528
    Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Patent number: 10424674
    Abstract: To provide a liquid crystal display device suitable for a thin film transistor which uses an oxide semiconductor. In a liquid crystal display device which includes a thin film transistor including an oxide semiconductor layer, a film having a function of attenuating the intensity of transmitting visible light is used as an interlayer film which covers at least the oxide semiconductor layer. As the film having a function of attenuating the intensity of transmitting visible light, a coloring layer can be used and a light-transmitting chromatic color resin layer is preferably used. An interlayer film which includes a light-transmitting chromatic color resin layer and a light-blocking layer may be formed in order that the light-blocking layer is used as a film having a function of attenuating the intensity of transmitting visible light.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Ishitani, Daisuke Kubota
  • Patent number: 10418252
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10403554
    Abstract: A method for manufacturing a semiconductor device includes: digging first and second trenches at the top surface of a plate-like base-body portion; forming an insulating film in the inside of each of the first and second trenches; laminating a conductive film on the top surface of the base-body portion so as to bury the first and second trenches with the conductive film via the insulating film; testing insulation-characteristics of the insulating film by applying a voltage between the conductive film and the bottom surface of the base-body portion; and after testing the insulation-characteristics, selectively removing the conductive film from the top surface of the base-body portion, so as to define a gate electrode in the first trench and an separated-electrode in the second trench, the separated-electrode being separated from the gate electrode.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 3, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 10396180
    Abstract: A method and apparatus, the method comprising: forming at least two electrodes (23) on a release layer wherein the at least two electrodes are configured to enable a layer of two dimensional material (25) to be provided between the at least two electrodes; providing moldable polymer (27) overlaying the at least two electrodes; wherein the at least two electrodes and the moldable polymer form at least part of a planar surface (29).
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 27, 2019
    Assignee: EMBERION OY
    Inventors: Adam Robinson, Darryl Cotton, Alexander Bessonov, Richard White, Yinglin Liu
  • Patent number: 10367062
    Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Isaac Lauer, Nicolas J. Loubet
  • Patent number: 10367017
    Abstract: An array substrate and a method of manufacturing the array substrate are provided. The method includes providing a substrate, sequentially forming a light-shielding layer, a buffer layer, an active layer, a source, a drain, a gate insulating layer, and a gate on the substrate, performing a first conductorization process on a corresponding region of the active layer opposite to the source and the drain, and performing a second conductorization process on another corresponding region of the active layer between the source and the gate and between the drain and the gate.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 30, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Hongyuan Xu
  • Patent number: 10355035
    Abstract: A manufacturing method of the back-channel-etched (BCE) TFT substrate, able to prevent the passivation layer from curling up and forming bubbles, while not causing damaging to the channel region of the active layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 16, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chunsheng Jiang
  • Patent number: 10347657
    Abstract: A complimentary metal-oxide-semiconductor (CMOS) device includes a wafer having a bulk semiconductor layer. A fin-type semiconductor device is formed on a first portion of the wafer. The CMOS devices also includes a nanosheet semiconductor device formed on a second portion of the wafer different from the first portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10347721
    Abstract: There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: July 9, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Laurent Grenouillet, Raluca Tiron
  • Patent number: 10340291
    Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuo Tsuboi, Yoshiki Yamamoto
  • Patent number: 10319679
    Abstract: A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ILD layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ILD layer, in which a width of the second portion is greater than a width of the first portion.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Mengkai Zhu
  • Patent number: 10312278
    Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a pixel region formed in a substrate and a storage region formed in the substrate and adjacent to the pixel region. The FSI image sensor device structure includes a storage gate structure formed over the storage region, and the storage gate structure includes a top surface and sidewall surfaces. The FSI image sensor device structure includes a metal shield structure formed on the storage gate structure, and the top surface and the sidewall surfaces of the storage gate structure are covered by the metal shield structure.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Kai Tsao, Shih-Pei Chou, Jiech-Fun Lu
  • Patent number: 10304876
    Abstract: This disclosure relates to the field of display technologies, and discloses a method for manufacturing an array substrate, an array substrate, a grayscale mask plate and a display device. The method includes forming a transparent conductive layer and a metal layer sequentially on a base substrate. A photoresist pattern is formed on the base: substrate on which the transparent conductive layer and the metal layer have been formed The transparent conductive layer and the metal layer corresponding to a photoresist-free region are removed. The photoresist in a second photoresist region is removed. The metal layer corresponding to the second photoresist region is removed to expose a pixel electrode. Additionally, the photoresist in a first photoresist region is removed to expose a first electrode, a second electrode and a first data line.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 28, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yiping Dong, Lei Zhang, Tianyou Gao
  • Patent number: 10283367
    Abstract: Provided is a hydrogenation annealing method using a microwave, which performs hydrogenation annealing at a low temperature and with low power in a manufacturing process of a thin film transistor (TFT) for a display device. The hydrogenation annealing method is constituted by a loading step of loading a device requiring hydrogenation annealing into a chamber and an annealing step of irradiating a microwave having a frequency in an industrial scientific medical (ISM) band into the chamber into which the device is loaded. As hydrogenation annealing is performed at a low temperature by using the microwave for an oxide semiconductor TFT or LTPS having very large electron mobility, high integrated energy is transmitted to the device by the microwave, thereby implementing recoupling of hydrogen atoms which have been performed only at a high temperature, even at a low temperature.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: May 7, 2019
    Assignee: CMTECH21 Co., Ltd.
    Inventors: Hi Chang Kim, Won-Ju Cho
  • Patent number: 10276715
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 10269906
    Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The contact is electrically connected to the source/drain feature. The gate spacer is disposed on a sidewall of the gate structure and between the gate structure and the contact. The contact spacer is disposed on the gate spacer and on a sidewall of the contact. An interface is formed between the gate spacer and the contact spacer, and a bottom surface of the contact spacer is in contact with the contact.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Po-Hsueh Li
  • Patent number: 10263018
    Abstract: Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality of signal lines arranged adjacent to each other at the same layer; and at least one redundant wire at a different layer from the signal lines, wherein each redundant wire corresponds to two adjacent signal lines, and a positive projection of the each redundant wire onto the layer where the signal lines are located covers a part or all of a gap between the two adjacent signal lines corresponding to the each redundant wire.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chunping Long
  • Patent number: 10254866
    Abstract: A display device, including a first transparent magnetic layer; a display panel on the first transparent magnetic layer; an upper member on the display panel; and a second transparent magnetic layer on the upper member, the second transparent magnetic layer being penetrated by light.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Hwa Choi, Seung-Bae Lee
  • Patent number: 10256242
    Abstract: A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Etron Technology, Inc.
    Inventor: Li-Ping Huang
  • Patent number: 10224350
    Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sanghoon Kim
  • Patent number: 10217682
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 10217952
    Abstract: The present disclosure relates to a nano-scale transistor. The nano-scale transistor includes a source electrode, a drain electrode, a gate electrode and a nano-heterostructure. The nano-heterostructure is electrically coupled with the source electrode and the drain electrode. The gate electrode is insulated from the nano-heterostructure, the source electrode and the drain electrode via an insulating layer. The nano-heterostructure includes a first carbon nanotube, a second carbon nanotube and a semiconductor layer. The semiconductor layer includes a first surface and a second surface opposite to the first surface. The first carbon nanotube is located on the first surface, the second carbon nanotube is located on the second surface.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: February 26, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10204798
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Junichi Koezuka, Takashi Hamochi, Yasuharu Hosaka
  • Patent number: 10199406
    Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate manufacturing method comprises: forming a source electrode and a drain electrode on a gate insulating layer; forming photoresist above the gate insulating layer and the source electrode and the drain electrode; etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode; and forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., SHANGHAI JIAO TONG UNIVERSITY
    Inventors: Wei Huang, Jiaqing Zhao, Linrun Feng, Wei Tang, Xiaojun Guo
  • Patent number: 10153159
    Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Seyoung Kim, Yun Seog Lee, Devendra Sadana, Joel de Souza
  • Patent number: 10141352
    Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhanfeng Cao, Feng Zhang, Bin Zhang, Xiaolong He, Zhengliang Li, Wei Zhang, Feng Guan, Jincheng Gao