Plural Gate Electrodes (e.g., Dual Gate, Etc.) Patents (Class 438/157)
  • Patent number: 11515421
    Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junggun You, Joohee Jung, Jaehyeoung Ma, Namhyun Lee
  • Patent number: 11495688
    Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu, Zhenxing Bi
  • Patent number: 11456385
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 27, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 11444083
    Abstract: A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: September 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 11424347
    Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ssu-Yu Liao, Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11417781
    Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan Kolluru, Biswajeet Guha, Chung-Hsun Lin, Brian Greene, Tahir Ghani
  • Patent number: 11417775
    Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Shriram Shivaraman, Van H. Le, Abhishek A. Sharma, Gilbert W. Dewey, Benjamin Chu-Kung, Miriam R. Reshotko, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 11398482
    Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Huai-Tei Yang
  • Patent number: 11387148
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 11380548
    Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantations in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chung Chen, Chung-Hao Chu, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 11335639
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 11271110
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 8, 2022
    Inventors: Tae-Jong Lee, Sanghyuk Hong, TaeYong Kwon, Sunjung Kim, Cheol Kim
  • Patent number: 11270891
    Abstract: The disclosure provides a method for making a self-aligned double pattern, A silicon substrate with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer, and covering them with a first silicon nitride layer; remove the first silicon nitride layer in the amorphous silicon pattern, forming first silicon nitride sidewall patterns on the amorphous silicon pattern's sidewalls; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin field-effect transistor, form core patterns and covering them with a thin silicon nitride layer; depositing a second oxide layer; defining the fin field-effect transistor's height, and etching back the second oxide layer till the height of the core patterns satisfies the defined fin field-effect transistor height; removing the thin silicon nitride layer, depositing a third oxide layer to cover the core patterns.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 8, 2022
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Yenchan Chiu, Yingju Chen, Liyao Liu, Chanyuan Hu
  • Patent number: 11205702
    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0?x?1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 21, 2021
    Assignee: Soitec
    Inventors: Christophe Figuet, Ludovic Ecarnot, Bich-Yen Nguyen, Walter Schwarzenbach, Daniel Delprat, Ionut Radu
  • Patent number: 11164973
    Abstract: The present disclosure is directed to a semiconductor device and a manufacturing method therefor. In one implementations, a method includes: providing a semiconductor structure, where the semiconductor structure includes: a substrate, and a first fin and a second fin spaced on the substrate; depositing a first interlayer dielectric layer on the semiconductor structure; performing first partial etching on the first interlayer dielectric layer to expose a top of the first fin; after the top of the first fin is exposed, removing a part of the first fin to form a first groove; epitaxially growing a first electrode in the first groove; performing second partial etching on the first interlayer dielectric layer to expose a top of the second fin; after the top of the second fin is exposed, removing a part of the second fin to form a second groove, where the second groove is separated from the first groove; and epitaxially growing a second electrode in the second groove.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: November 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 11139399
    Abstract: A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 11101366
    Abstract: A remotely generated plasma energizes radicals of a process gas. The radicals of the process gas may interact with a precursor gas to cause a reaction to form an oxide on a region of a workpiece. The formation of the oxide is formed without damaging an underlying layer, such as a low-k dielectric layer. The oxide layer may correspond to a main sidewall oxide over a gate spacer in the formation of a FinFET device.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Iwen Hsu, Jei Ming Chen
  • Patent number: 11088265
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a base substrate; and a first doped epitaxial layer and a second doped epitaxial layer in the base substrate. Each of the first and second doped epitaxial layers is corresponding to a different gate structure on the base substrate. The semiconductor structure further includes a repaired dielectric layer formed on and surrounding each of the first and second doped epitaxial layer; a metal layer on the repaired dielectric layer; an interlayer dielectric layer over the base substrate and covering tops of gate structures; and a conductive plug on the metal layer and through the interlayer dielectric layer.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 10, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 11081398
    Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: August 3, 2021
    Assignee: GLOBALEOUNDRIES U.S. INC.
    Inventors: Xusheng Wu, David Paul Brunco
  • Patent number: 11043597
    Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz
  • Patent number: 11018224
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 11018061
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 11011581
    Abstract: First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures. Each of the elongated loop-shaped conductive material potions includes a respective pair of line segments and a respective pair of end segments adjoined to ends of the respective pair of line segments. A moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures can be formed by performing an anisotropic etch process that removes parts of the first and second elongated loop-shaped conductive material portions, thereby separating each loop-shaped conductive material portion into two disjoined line segments.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuji Takahashi, Jo Sato, Wei Kuo Shih
  • Patent number: 10861850
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Byron Ho, Chun-Kuo Huang, Erica Thompson, Jeanne Luce, Michael L. Hattendorf, Christopher P. Auth, Ebony L. Mays
  • Patent number: 10804394
    Abstract: A transistor includes at least one fin structure (e.g., three fin structures) and a gate. The fin structure is disposed above a semiconductor layer above an insulator layer of a semiconductor on insulator substrate. The gate is disposed over at least three sides of the fin structure and a portion of the semiconductor layer. A channel for the transistor is disposed in fin structure and the portion under the gate.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 13, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Qing Liu
  • Patent number: 10797179
    Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 6, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10714598
    Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsan-Chun Wang, Chun-Feng Nieh, Chiao-Ting Tai
  • Patent number: 10700209
    Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 10692777
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: June 23, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 10615265
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10608121
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu
  • Patent number: 10551709
    Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes an array substrate and an opposing substrate which are disposed opposite to each other; the array substrate includes a first base substrate and a source electrode, a drain electrode and an active layer which are disposed on the first base substrate, and a passivation layer disposed on the source electrode, the drain electrode and the active layer; the opposing substrate includes a second base substrate and a gate electrode disposed on the second base substrate; the active layer includes a source electrode region, a drain electrode region and a channel region between the source electrode region and the drain electrode region, the gate electrode is disposed opposite to and spaced apart from the passivation layer at a position where the channel region is located.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 4, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ke Cao, Chengshao Yang, Binbin Cao, Ling Han
  • Patent number: 10546850
    Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
  • Patent number: 10534393
    Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yvonne Lin, Da-Wen Lin, Peter Huang, Paul Rousseau, Sheng-Jier Yang
  • Patent number: 10522691
    Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoko Tsukamoto
  • Patent number: 10517179
    Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Siao-Shan Wang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10497611
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 10461165
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Ming-Han Liao
  • Patent number: 10418462
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10418283
    Abstract: A method for manufacturing a semiconductor device having a shallow trench isolation structure includes providing a semiconductor substrate having first and second regions, multiple fins disposed on the first and second regions, and a hardmask layer on an upper surface of the fins, forming a first dielectric layer on the semiconductor substrate covering the fins, forming a first mask layer including an opening exposing a portion of the first dielectric layer between the first and second regions, implanting dopant ions into the exposed portion of the first dielectric layer, removing the first mask layer, and performing an etching process on the first dielectric layer to form a first isolation region between the first and second regions and a second isolation region between the fins. The doped portion has a reduced etch rate so that the thickness of the first isolation region is thicker than the second isolation region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 17, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10319839
    Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 11, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Zhong Shan Hong, Ke Lu Hua, Jin Peng
  • Patent number: 10276720
    Abstract: A FinFET device structure and method for forming the same are provided. The method includes forming a plurality of fin structures over a substrate, and the substrate includes a first region and a second region. The method includes forming a plurality of isolation structures surrounding the fin structures, and a top surface of each of the isolation structures is lower than a top surface of each of the fin structures, and the isolation structures include first isolation structures over the first region and second isolation structures over the second region. The method includes forming a mask layer on the first isolation structures to expose the second isolation structures and removing a portion of the second isolation structures, such that a top surface of each of the second isolation structures is lower than a top surface of each of the first isolation structures.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng
  • Patent number: 10256341
    Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 9, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10242867
    Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventors: Guillaume Bouche, Vimal Kamineni
  • Patent number: 10224248
    Abstract: In various embodiments of the disclosed subject matter, a semiconductor structure, and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: providing a substrate; implanting first punch-through preventing ions into an NMOS region of the substrate to form a first implantation layer; implanting second punch-through preventing ions into a PMOS region of the substrate to form a second implantation layer; etching the substrate to form first fin portions in the NMOS region, and second fin portions in the PMOS region, the remaining first implantation layer forms a first punch-through preventing layer, the remaining second implantation layer forms a second punch-through preventing layer; forming insulating structures between adjacent first fin portions and second fin portions; and performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: March 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10211316
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10084085
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10049918
    Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Hung, Ru-Gun Liu, Wei-Liang Lin, Ta-Ching Yu, Yung-Sung Yen, Ziwei Fang, Tsai-Sheng Gau, Chin-Hsiang Lin, Kuei-Shun Chen
  • Patent number: 10043759
    Abstract: An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The length of the first feature is greater than the width of the first feature. The overlay mark also comprises a second feature in a second layer over the first layer. The second feature has a length extending in the second longitudinal direction and a width extending in the first longitudinal direction. The length of the second feature is greater than the width of the second feature. The overlay mark further comprises a third feature in a third layer over the second layer. The third feature is a box-shaped opening in the third layer.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Yu Chen, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 9899216
    Abstract: The present invention provides a semiconductor device manufacturing method for lowering the technical difficulties of a process forming a horizontal single crystal nanowire and a manufacturing cost, the semiconductor device manufacturing method comprising the steps of: preparing a substrate including a first area and a second area; determining a position at which a nanowire is to be formed on the substrate of the first area and arranging an empty space in which the nanowire is to be filled; exposing a substrate surface of a part adjacent to the first area; causing selective single crystal growth from the exposed substrate surface; and forming a nanowire by a self-aligned method through an etching process within the first area, and removing, from outside the first area, a single crystal growth layer of the remaining areas excluding a part necessary for the wiring of the second area.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 20, 2018
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jeoungwoo Kim, Wangyu Lee, Hoseung Jeon, Junghwan Hyung, Jaehong Park