Plural Gate Electrodes (e.g., Dual Gate, Etc.) Patents (Class 438/157)
  • Patent number: 10714598
    Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsan-Chun Wang, Chun-Feng Nieh, Chiao-Ting Tai
  • Patent number: 10700209
    Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 10692777
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: June 23, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 10615265
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10608121
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu
  • Patent number: 10551709
    Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes an array substrate and an opposing substrate which are disposed opposite to each other; the array substrate includes a first base substrate and a source electrode, a drain electrode and an active layer which are disposed on the first base substrate, and a passivation layer disposed on the source electrode, the drain electrode and the active layer; the opposing substrate includes a second base substrate and a gate electrode disposed on the second base substrate; the active layer includes a source electrode region, a drain electrode region and a channel region between the source electrode region and the drain electrode region, the gate electrode is disposed opposite to and spaced apart from the passivation layer at a position where the channel region is located.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 4, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ke Cao, Chengshao Yang, Binbin Cao, Ling Han
  • Patent number: 10546850
    Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
  • Patent number: 10534393
    Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yvonne Lin, Da-Wen Lin, Peter Huang, Paul Rousseau, Sheng-Jier Yang
  • Patent number: 10522691
    Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoko Tsukamoto
  • Patent number: 10517179
    Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Siao-Shan Wang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10497611
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 10461165
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Ming-Han Liao
  • Patent number: 10418283
    Abstract: A method for manufacturing a semiconductor device having a shallow trench isolation structure includes providing a semiconductor substrate having first and second regions, multiple fins disposed on the first and second regions, and a hardmask layer on an upper surface of the fins, forming a first dielectric layer on the semiconductor substrate covering the fins, forming a first mask layer including an opening exposing a portion of the first dielectric layer between the first and second regions, implanting dopant ions into the exposed portion of the first dielectric layer, removing the first mask layer, and performing an etching process on the first dielectric layer to form a first isolation region between the first and second regions and a second isolation region between the fins. The doped portion has a reduced etch rate so that the thickness of the first isolation region is thicker than the second isolation region.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 17, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10418462
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10319839
    Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 11, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Zhong Shan Hong, Ke Lu Hua, Jin Peng
  • Patent number: 10276720
    Abstract: A FinFET device structure and method for forming the same are provided. The method includes forming a plurality of fin structures over a substrate, and the substrate includes a first region and a second region. The method includes forming a plurality of isolation structures surrounding the fin structures, and a top surface of each of the isolation structures is lower than a top surface of each of the fin structures, and the isolation structures include first isolation structures over the first region and second isolation structures over the second region. The method includes forming a mask layer on the first isolation structures to expose the second isolation structures and removing a portion of the second isolation structures, such that a top surface of each of the second isolation structures is lower than a top surface of each of the first isolation structures.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng
  • Patent number: 10256341
    Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 9, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10242867
    Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventors: Guillaume Bouche, Vimal Kamineni
  • Patent number: 10224248
    Abstract: In various embodiments of the disclosed subject matter, a semiconductor structure, and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: providing a substrate; implanting first punch-through preventing ions into an NMOS region of the substrate to form a first implantation layer; implanting second punch-through preventing ions into a PMOS region of the substrate to form a second implantation layer; etching the substrate to form first fin portions in the NMOS region, and second fin portions in the PMOS region, the remaining first implantation layer forms a first punch-through preventing layer, the remaining second implantation layer forms a second punch-through preventing layer; forming insulating structures between adjacent first fin portions and second fin portions; and performing an annealing process to activate the first punch-through preventing layer and the second punch-through preventing layer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: March 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10211316
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10084085
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10049918
    Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Hung, Ru-Gun Liu, Wei-Liang Lin, Ta-Ching Yu, Yung-Sung Yen, Ziwei Fang, Tsai-Sheng Gau, Chin-Hsiang Lin, Kuei-Shun Chen
  • Patent number: 10043759
    Abstract: An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The length of the first feature is greater than the width of the first feature. The overlay mark also comprises a second feature in a second layer over the first layer. The second feature has a length extending in the second longitudinal direction and a width extending in the first longitudinal direction. The length of the second feature is greater than the width of the second feature. The overlay mark further comprises a third feature in a third layer over the second layer. The third feature is a box-shaped opening in the third layer.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Yu Chen, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 9899216
    Abstract: The present invention provides a semiconductor device manufacturing method for lowering the technical difficulties of a process forming a horizontal single crystal nanowire and a manufacturing cost, the semiconductor device manufacturing method comprising the steps of: preparing a substrate including a first area and a second area; determining a position at which a nanowire is to be formed on the substrate of the first area and arranging an empty space in which the nanowire is to be filled; exposing a substrate surface of a part adjacent to the first area; causing selective single crystal growth from the exposed substrate surface; and forming a nanowire by a self-aligned method through an etching process within the first area, and removing, from outside the first area, a single crystal growth layer of the remaining areas excluding a part necessary for the wiring of the second area.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 20, 2018
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jeoungwoo Kim, Wangyu Lee, Hoseung Jeon, Junghwan Hyung, Jaehong Park
  • Patent number: 9876085
    Abstract: An array substrate comprises a base substrate on which data lines and gate lines intersecting with each other are formed to define pixel units, and a switching element is provided in each of the pixel units and comprises a gate electrode, an active layer, a source electrode and a drain electrode, and end parts of the source electrode and the drain electrode located directly on the active layer are opposite to each other to define a channel region. An extension conductive part is formed close to the source electrode or the drain electrode and to electrically contact the source electrode or the drain electrode, one end of the extension conductive part extends toward the channel to protrude from the source electrode or the drain electrode contacting with the extension conductive part and to contact the active layer at least within the channel region.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 23, 2018
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Sang Jin Park
  • Patent number: 9853127
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 9842739
    Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 9818748
    Abstract: A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Patent number: 9748352
    Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 29, 2017
    Assignees: STMicroelectronics, Inc, GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh, Xiuyu Cai
  • Patent number: 9741807
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9691664
    Abstract: A method of forming a thick oxide layer over fins for EG devices and a thinner oxide layer over fins for SG devices on the same substrate and the resulting device are provided. Embodiments include forming a first set of fins over a first portion of a Si substrate; forming a second set of fins over a second portion of the Si substrate spaced from the first portion; forming an iRAD SiO2 layer over the first and second sets of fins; forming a polysilicon layer over the iRAD SiO2 layer over the first set of fins; forming a radical SiO2 layer over the iRAD SiO2 layer over the second set of fins and over the polysilicon layer; forming a mask over the radical SiO2 layer over the second set of fins; removing the polysilicon layer; and removing the mask and the iRAD SiO2 layer from the first set of fins.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie
  • Patent number: 9685501
    Abstract: Embodiments in accordance with the present invention include a method of fabricating a finFET device comprising forming a dielectric layer over the top surface of a semiconductor substrate. A first semiconductor layer is deposited over the dielectric layer. A second semiconductor layer is then deposited over the first semiconductor layer, such that the first semiconductor layer can be preferentially etched with respect to the second semiconductor layer. At least a fin is formed in the second semiconductor layer. A portion of the first semiconductor layer is removed from beneath a portion of the fin such that the bottom surface of the fin is exposed. A gate oxide layer is deposited over the fin such that the gate oxide layer surrounds a portion of the fin, and a gate structure is deposited over at least a portion of the gate oxide layer such that the gate structure surrounds the fin.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9679961
    Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 13, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu, Samuel C. Pan
  • Patent number: 9679993
    Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran, Reinaldo A. Vega
  • Patent number: 9673301
    Abstract: One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Fuad Al-Amoody, Jinping Liu, Haifeng Sheng
  • Patent number: 9653284
    Abstract: A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor comprises: a gate electrode (11), a source electrode (15) and a drain electrode (16), and the thin film transistor further comprises a buffer layer (11) which is directly provided at one side or both sides of at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16), wherein, the buffer layer (11) and at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16) directly contacting the buffer layer (11) are conformal. Therefore, the adhesion between an electrode of the thin film transistor and a film layer contacting it is improved and at the same time an atom in the electrode of the thin film transistor is effectively prevented from diffusing to the film layer connected with it, and the reliability of the thin film transistor is improved and the production cost is reduced.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 16, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhengliang Li, Zhen Liu, Luke Ding, Bin Zhang, Zhanfeng Cao, Guanbao Hui
  • Patent number: 9647091
    Abstract: A method of forming a field effect transistor is provided. The method of forming a field effect transistor may include forming a dummy gate perpendicular to and covering a channel region of a semiconductor fin, such that a source drain region of the semiconductor fin remains uncovered, depositing a metal layer above and in direct contact with a sidewall of the dummy gate, and above and in direct contact with a top and a sidewall of the source drain region, and forming a metal silicide source drain in the source drain region by annealing the metal layer and the semiconductor fin, such that the metal silicide source drain overlaps the dummy gate.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9577066
    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, forming a liner layer above at least a first upper surface of the first fin and a second upper surface of the second fin, and forming an ion-containing region in the first portion of the liner layer while not forming the ion-containing region in second portion of the liner layer. The method also includes performing a liner etching process so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned above the first fin, and performing at least one etching process to define a reduced-height second fin that is less than an initial first height of the first fin.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Fuad Al-Amoody, Jinping Liu
  • Patent number: 9543039
    Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Hiroyuki Miyake
  • Patent number: 9502561
    Abstract: An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained materials disposed on each of the plurality of the fin structures; a plurality of cap layers individually formed on each of the plurality of first strained materials, wherein at least two cap layers are connected to each other; a second strained material disposed on the at least two cap layers which are connected to each other.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Chang, Hsueh-Chang Sung, Kun-Mu Li, Ming-Hua Yu
  • Patent number: 9466673
    Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gen P. Lauer, Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight
  • Patent number: 9443945
    Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel
  • Patent number: 9443951
    Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 9431514
    Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 30, 2016
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Bruce Doris, Gauri Karve
  • Patent number: 9368574
    Abstract: A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner gate. The first epitaxial dielectric layer is surrounded by an epitaxial semiconductor channel. The epitaxial semiconductor channel surrounds a second dielectric layer. A gate conductor surrounds the second dielectric layer. The gate conductor is patterned into a gate line and defines a channel region overlapping the gate line. The semiconductor device contains source and drain regions adjacent to the gate line.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: June 14, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy M. Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9362136
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 7, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 9318567
    Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • Patent number: 9318334
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Shih-Hung Tsai, Jyh-Shyang Jenq, Chih-Kai Hsu
  • Patent number: 9306070
    Abstract: A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Hyun Baek, Sung-Hyun Park, Sang-Hoon Baek, Tae-Joong Song
  • Patent number: 9305930
    Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ramachandra Divakaruni, Arvind Kumar, Carl J. Radens