Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.

Abstract: A method of preparing a boron allotrope-organic lateral heterostructural article includes providing an article comprising a substrate comprising a portion thereof coupled to a boron allotrope comprising an elemental boron layer; generating an organic compound vapor from a solid organic compound source, said organic compound vapor having a higher enthalpy of adsorption on said substrate compared to enthalpy of adsorption on said boron allotrope; and contacting said organic compound vapor with said article to selectively deposit said organic compound on a substrate portion not coupled to said boron allotrope to provide a heterostructural article comprising said organic compound and said boron allotrope laterally adjacent one to the other and providing a lateral interface one with the other.

Abstract: A stack is formed on a substrate. The stack includes plural first epitaxial layers and plural second epitaxial layers alternatingly stacked over each other. The first epitaxial layers include sulfur, phosphorous, selenium, arsenic, or combinations thereof. A first etching process is performed on the stack to form a fin. A dielectric layer is formed over the fin. A channel region of the fin is exposed. A second etching process is performed on a first portion of each of the first epitaxial layers in the channel region of the fin using a hydrocarbon etch chemistry. The second etching process etches the first epitaxial layers at a higher etch rate than the second etching process etches the second epitaxial layers. A gate structure is formed around a first portion of each of the second epitaxial layers in the channel region of the fin.

Abstract: Articles comprising a boron allotrope and an organic compound having a lateral interface one with the other, together with method(s) of preparation of such articles.

Abstract: The present disclosure provides a defect repairing method of a flexible display panel including: providing a transparent substrate, the transparent substrate including a first surface and a second surface opposite to each other; forming a flexible substrate on the first surface; forming an array substrate layer on the surface of the flexible substrate, wherein the array substrate layer includes a display area and a peripheral area; irradiating the display area with a patterned laser on the second surface; and annealing the transparent substrate on which the array substrate layer and the flexible substrate are formed. The defect repairing method of the flexible display panel can quickly and easily repair various defects caused by the laser irradiation of the flexible display panel so as to optimize the display effect of the flexible display panel and improve the yield of the flexible display panel.

Abstract: Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

Abstract: A semiconductor element and a method for producing the same are provided. A semiconductor element includes an active region comprising trenches, a termination region outside the active region, a transient region disposed between the active region and the termination region, the transient region including an inside trench, in which a center poly electrode is disposed inside at least one of the trenches of the active region, at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode, a p-body region is disposed between upper portions of the trenches, and a source region is disposed at a side of the gate poly electrodes.

Abstract: A method for placing a resist film of a region having a small film thickness with good shape accuracy is provided. The method has processes of placing a photoresist film 15 on a substrate body 10, exposing the photoresist film 15 using a halftone mask 30 having light transmittances of three or more tones, and developing the photoresist film 15. The photoresist film 15 after the development has a first photoresist film 16 and a second photoresist film 17 that is thicker than the first photoresist film 16. On the substrate body 10 after the development, the second photoresist film 17 is placed at a location where the second photoresist film 17 can be placed without removing the photoresist film 15.

Abstract: Disclosed is a method for manufacturing a TFT substrate, which uses one partial transmitting mask to form patterns of an active layer, a gate insulation layer, and a gate electrode through photolithography such that the entire process for manufacturing TFT substrate can be completely conducted by using only three masks. Compared to the prior art, one mask is save so that the operation is simplified and the manufacturing cost is reduced.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a material layer on the substrate; forming a plurality of first mandrels on the material layer of the first region and the second region; forming first spacers adjacent to the first mandrels; forming a hard mask on the first region; trimming the first spacers on the second region; removing the first mandrels; using the first spacers to remove part of the material layer for forming a plurality of second mandrels; forming second spacers adjacent to the second mandrels; removing the second mandrels; and using the second spacers to remove part of the substrate for forming a plurality of fin-shaped structures.

Abstract: Methods for forming a semiconductor gate electrode with a reflowed Co layer and the resulting device are disclosed. Embodiments include forming a trench in an ILD on a substrate; forming a high-k dielectric layer, a WF layer, and a Co layer sequentially on sidewall and bottom surfaces of the trench; reflowing a portion of the Co layer from the WF layer on the sidewall surfaces of the trench to the WF layer on the bottom surface of the trench; removing a remainder of the Co layer from the WF layer on the sidewall surfaces of the trench, above an upper surface of the reflowed Co; recessing the WF layer to the upper surface of the reflowed Co layer, forming a cavity above the reflowed Co layer; and filling the cavity with metal to form a gate electrode.

Abstract: A display device includes a driver circuit including a logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor; a signal line which is electrically connected to the driver circuit; a pixel portion including a pixel whose display state is controlled by input of a signal including image data from the driver circuit through the signal line; a reference voltage line to which reference voltage is applied; and a third transistor which is a depletion type transistor and controls electrical connection between the signal line and the reference voltage line. The first to the third transistors each include an oxide semiconductor layer including a channel formation region.

Abstract: A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at least a part of the non-doped polysilicon layer is covered by an above metal layer. With effects of the metal layer which is applied with a RF signal or a superposed signal, and fixed charges in the BOX layer, an inversion layer may be formed at a surface of the non-doped polysilicon layer. Since carriers may easily recombine at the grain boundaries of polysilicon, eddy current generated on a surface of the high resistivity silicon base is reduced, loss of the RF signal is reduced, and linearity of the RF signal device is improved.

Abstract: A performance of a semiconductor device is improved. A gate electrode is formed on an SOI substrate via a gate insulating film, and a laminated film including an insulating film IL2 and an insulating film IL3 on the insulating film IL2 is formed on the SOI substrate so as to cover the gate electrode, and then, a sidewall spacer formed of the laminated film is formed on a side wall of the gate electrode by etching back the laminated film. Then, a semiconductor layer is epitaxially grown on a semiconductor layer of the SOI substrate SUB which is not covered with the gate electrode and the sidewall spacer but is exposed, and then, an oxide film is formed on a surface of the semiconductor layer by oxidizing the surface of the semiconductor layer. Then, the insulating film IL3 forming the sidewall spacer is removed.

Abstract: A method of forming a field effect transistor (FET) device includes forming a diffusion facilitation layer on top of a semiconductor substrate; forming a doped, raised source/drain (RSD) layer on the diffusion facilitation layer; removing a portion of the diffusion facilitation layer, corresponding to a region directly above a channel region of the FET device; and performing an anneal so as to define abrupt source and drain junctions in the semiconductor substrate, wherein dopant atoms from the doped RSD layer diffuse within the diffusion facilitation layer at a faster rate than with respect to the semiconductor substrate.

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract: In a thin film transistor and a display device provided with the same, a thin film transistor according to an exemplary embodiment includes: a semiconductor layer including a channel region, a source region, a drain region, a light-doped source region, and a light-doped drain region; a gate electrode overlapping the channel region; a source electrode contacting the source region; and a drain electrode contacting the drain region. The channel region includes a main channel portion, a source channel portion, and a drain channel portion, and the source channel portion and the drain channel portion are extended from the main channel portion and separated from each other. The light-doped source region is disposed between the source channel portion and the source region and the light-doped drain region is disposed between the drain channel portion and the drain region.

Abstract: A method of selectively etching a three-dimensional (3-D) structure includes generating a plasma in contact with the 3-D structure, and illuminating a designated portion of the 3-D structure with a laser beam while the plasma is being generated. Nonilluminated portions of the 3-D structure are etched at a first etch rate, and the designated portion of the 3-D structure is etched at a second etch rate, where the second etch rate is different from the first etch rate.

Abstract: A semiconductor device in which a semiconductor layer is formed over a gate electrode with a large aspect ratio, thereby obtaining a channel length of a transistor which hardly causes a short-channel effect even when the transistor is miniaturized. A lower electrode is provided under the gate electrode with an insulating layer provided therebetween so that the electrode overlaps with the semiconductor layer. A potential (electric field) of the lower electrode imparts a conductivity type to the semiconductor layer overlapping with the lower electrode, so that a source region and a drain region are formed in the semiconductor layer. The gate electrode serves as a shield, so that a region in the semiconductor layer, which faces the gate electrode with the gate insulating layer provided therebetween, is not influenced by the electric field from the lower electrode.

Abstract: The N-type poly-silicon is applied in the LTPS productions. The LTPS productions comprise an N-type poly-silicon and a P-type poly-silicon. The N-type poly-silicon, from bottom to top, successively includes a substrate layer, a SiOx layer, a SiNx layer, a metal layer and a photoresist. The substrate layer is an A-type silicon layer. Wherein, the method for controlling the threshold voltage of the N-type poly-silicon specifically comprise the following steps: (a) etching the metal layer and the SiNx layer, and over etching the SiOx layer in a small quantity; (b) over etching the metal layer, and etching a portion of the SiOx layer, and the SiOx layer is not etched through.

Abstract: An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.

Abstract: The present invention relates to combinations of materials and fabrication techniques which are useful in the fabrication of filled, metal-comprising gates for use in planar and 3D Field Effect Transistor (FET) structures. The FET structures described are of the kind needed for improved performance in semiconductor device structures produced at manufacturing nodes which implement semiconductor feature sizes in the 15 nm range or lower.

Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.

Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Abstract: A method of manufacturing a three dimensional FET device structure includes: providing a substrate having a semiconductor layer on an insulator layer; forming three dimensional fins in the semiconductor layer; applying a masking material to a first fin while exposing a second fin; applying a hydrogen atmosphere to the substrate and exposed second fin, the hydrogen atmosphere causing the exposed second fin to reflow and change shape; removing the masking material from the first fin; and forming a gate to wrap around each of the first and second fins. The first and second fins are formed having a device width such that the first fin having a first device width and a second fin having a second device width with the first device width being different than the second device width.

Abstract: Embodiments of the invention provide a thin film transistor, an array substrate and a manufacturing method thereof, and a display panel. The thin film transistor comprises: an active layer pattern, a source electrode, a drain electrode and a gate electrode. The gate electrode is positioned above the active layer pattern, the source electrode is connected with the active layer pattern, the drain electrode is connected with the active layer pattern, and the source electrode and the drain electrode are disposed in an adjacent layer of the active layer pattern.

Abstract: To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.

Abstract: A method for fabricating a thin-film transistor is disclosed. Firstly, a patterned dielectric mask structure with a bottom thereof having a gate dielectric layer is formed on a gate-stacked structure so that the gate dielectric layer covers a gate of the gate-stacked structure. Top surface of the patterned dielectric mask structure has at least two openings. A semiconductor layer is formed on the gate-stacked structure via the openings by a sputtering method. The semiconductor layer comprises a channel above the gate, a source and a drain below the openings. The channel has a thickness which sequentially decreases from edge to center.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.

Abstract: An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first. Gate is provided above the N-well and P-well on substrate. Spin coating a layer of photoresist in the first spacer, patterning the photoresist, and the gate structure above the N-well or P-well is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the first spacer layer, form the second spacer layer by depositing on the surface of the si substrate and gate, and spin coating another photoresist layer on the second spacer layer. Pattern the another photoresist layer, and another side of the gate structure is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the second spacer layer, form the third spacer layer and SiN layer by depositing on the gate and the Si substrate in turn.

Abstract: A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin.

Abstract: An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.

Abstract: The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract: A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

Abstract: A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.

Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.

Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

Abstract: An integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.

Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

Abstract: Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors.

Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.