Abstract: A method for forming a dual damascene structure is disclosed. First a substrate is provided. There are an etching stop layer and an interlayer dielectric layer disposed on the substrate in order. The interlayer dielectric layer has a thickness A. Second, the interlayer dielectric layer is patterned to form a first opening. Later, a photo resist layer with a thickness B is formed on the interlayer dielectric layer. Then, the photo resist layer is patterned by a light source to construct a patterned photo resist layer. Later, the interlayer dielectric layer is again patterned by the patterned photo resist to pattern the interlayer dielectric layer to construct a second opening on the first opening by means of a light source and the photo resist layer so as to form a dual damascene structure. The light source has a periodic parameter C so that (A+B)/C?X/2, where X is an odd number.

Abstract: Method for manufacturing a semiconductor optical device includes forming an epitaxial structure containing at least an active layer which can emit light, of a III-V group semiconductor material; forming an insulating layer over the epitaxial structure, which prevents the V group element from escaping from the epitaxial structure during heat treatment; heat treating the epitaxial structure at at least 800 degrees C.; and removing the insulating layer, thereby enhancing the reliability of the device.

Abstract: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing or active elements, or may selectively cover only certain of the device's elements. Further, coupling the metal or mechanical-quality, doped polysilicon to the same voltage source as the device's substrate contact may place the conductive layer at the voltage of the substrate, which may function as a Faraday shield, attracting undesired, migrating ions from interfering with the output of the device.

Abstract: A method for manufacturing a semiconductor optical device includes: forming a laminated semiconductor structure of GaN-based materials on a semiconductor wafer, the laminated semiconductor structure forming a laser diode of GaN-based materials, including an active layer having a quantum well structure; cleaving the semiconductor wafer including the laminated semiconductor structure to expose a cleaved end face of the laminated semiconductor structure; and forming an SiO2 film on the cleaved end face and performing a heat treatment to cause Ga vacancy diffusion in the active layer to disorder the quantum well structure of the active layer.

Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.

Abstract: A template inspection method for performing defect inspection of a template, by bringing a pattern formation surface of a template used to form a pattern close to a first fluid coated on a flat substrate, filling the first fluid into a pattern of the template, and by performing optical observation of the template in a state that the first fluid is sandwiched between the template and the substrate, wherein a difference between an optical constant of the first fluid and an optical constant of the template is larger than a difference between an optical constant of air and the optical constant of the template.

Abstract: Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate.

Abstract: A silicon substrate processing method for reducing the thickness of an area of a silicon substrate on which a metal layer is formed to implement a semiconductor integrated circuit is disclosed. The method includes: (A) a process which evenly reduces the thickness of the backside of a silicon substrate to an extent where mechanical strength is maintained and the metal layer on the silicon substrate remains intact; (B) a process which detects defects from the backside of the silicon substrate after the process (A); (C) a process which further reduces the thickness of a defect-containing area of the silicon substrate by processing the backside of the silicon substrate; and (D) a process which measures the thickness of the area of the silicon substrate which is reduced in the process (C).

Abstract: An edge bead removal measurement method includes determining an edge of a wafer about a circumference of the wafer. A location of a wafer notch on the edge of the wafer is determined. A location of a center of the wafer is determined. A distance from the edge of the wafer to an edge bead removal line about the circumference of the wafer is determined.

Abstract: A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

Abstract: A method for the protection of the information in a multi-project wafer (MPW) is provided. First, a substrate is provided. There are a first die and a second die on the substrate. Second, a first wafer process is performed on the substrate. The first wafer process includes performing a wafer procedure by using a non-destructive energy source and destroying the first die by using a destructive energy source. Later, a second wafer process is performed to finish the second die.

Abstract: A system of testing semiconductor devices includes a classification module configured to classify a plurality of lots into a plurality of groups; an apparatus assignment module configured to assign a plurality of testing apparatuses to each of the groups; and a test recipe creation module configured to create a test recipe to test defects in a second group other than a first group specified in the groups, the test recipe including a definition of testing positions in the second group defined by a rule different from the first group.

Abstract: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement.

Abstract: A rework station and a metrology device(s) are incorporated into a lithographic processing cell so that a faulty substrate can be reworked directly and reprocessed without, for example, an overhead involved in changing masks, etc.

Abstract: An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve.

Abstract: One embodiment of the present invention sets forth a computer-implemented method for tuning laser scribe parameters during the fabrication of a solar module. The method includes analyzing the visual appearance of a laser scribe to extract various morphological parameters related to the quality of a laser scribe process used to produce the scribe. Based on the morphological parameters, the laser scribe parameters may be modified in-situ to achieve settings that are optimal for performing laser scribing in each layer of the solar module. As a result, laser scribe process cycle time may be minimized while providing better indication of the laser scribe process stability and quality relative to the prior art approaches.

Abstract: A non-volatile memory semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a PN junction diode formed over a semiconductor substrate. Insulating films may be formed over the PN junction diode and patterned to have via holes. A resistive random access memory including a first metal pattern may be in contact with a first region of the PN junction diode. An oxide film pattern may be formed over the first metal pattern and a second metal pattern formed over the oxide film pattern. The first metal pattern, the oxide film pattern and the second metal pattern may be formed in the via holes.

Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.

Abstract: [Problems] To perform predetermined processing such as annealing and coating application of a semiconductor material with high accuracy on a number of semiconductor formation areas formed over a wide region on a surface of a substrate having elasticity such as a plastic substrate even when the substrate expands and contracts.

Abstract: A pattern inspection apparatus includes an optical image acquiring unit that acquires optical image data of a target plate formed as a pattern. The pattern inspection apparatus also includes a design image data generating unit that generates first design image data based on a first design pattern serving as a base of pattern formation of the target plate. The pattern inspection apparatus additionally includes a comparing unit that compares the optical image data and the first design image data with each other. Further, information of a second design pattern is input in parallel with information of the first design pattern to the pattern inspection apparatus. In the comparing unit, second design image data generated based on the second design pattern is further input, and the optical image data is compared with the second design image data in place of the first design image data.

Abstract: The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.

Abstract: A method of inspecting defect of a mask is provided. In this method, a database for storing a plurality of virtual simulation models is created. The virtual simulation models are determined by a plurality of factors including an optical effect and a chemical effect during the transferring the pattern of a mask to the photoresist layer on a wafer. A mask defect image is acquired. A simulation contour of the mask defect image is generated from at least one virtual simulation model in the database. Next, the acceptability of the mask is determined.

Abstract: A method and apparatus for calibrating a metrology tool are disclosed. The apparatus includes a substrate having at least one calibration site formed thereon. The calibration site includes a pattern of cells that have at least one feature disposed in a surface of the substrate. The feature provided for measurement by a step height metrology tool and a phase metrology tool to calibrate the step height and phase metrology tools.

Abstract: A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history.

Abstract: Measuring the amount of unreacted polysilicon gate material in a fully silicided (FUSI) nickel silicide gate process for metal oxide semiconductor (MOS) transistors in an integrated circuit (IC) to guide process development and monitor IC production requires a statistically significant sample size and an economical procedure. A method is disclosed which includes a novel deprocessing sequence of oxidizing the nickel followed by removing the nickel silicide by acid etching, acquiring an SEM image of a deprocessed area encompassing a multitude of gates, forming a quantifiable mask of the original gate area in the SEM image, forming a quantifiable image of the unreacted polysilicon area in the SEM image, and computing a fraction of unreacted polysilicon.

Abstract: Provided is an apparatus for auto focusing a workpiece for optical metrology measurements using an optical metrology system. The auto focusing subsystem includes a focus detector having a tilt angle, a capture range, and a plurality of sensors. A processor coupled to the focus detector is configured to utilize the plurality of focus signals measured using the focus detector to determine two or more focus parameters. The two or more focus parameters and calibration data are used to determine an initial position of the workpiece and to generate instructions to move the workpiece to a best focus position. A diffraction signal is measured off a structure on the workpiece using the optical metrology system to determine at least one profile parameter of the structure. The at least one profile parameter is used to modify at least one process variable or equipment setting of a semiconductor fabrication cluster.

Abstract: The invention provides a plasma processing method capable of reducing the damage applied to the low-k film or the underlayer.

Abstract: A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second semiconductor chip, and the first marks and the second marks are different from each other in at least either one of size and geometry.

Abstract: A method of determining defects in a plurality of images having essentially the same image contents is disclosed. A comparison operation is carried out once three fully comparable images having essentially the same image contents are present in the intermediate memory. The stored individual images are accessed randomly. A paired comparison operation between the three difference images is carried out.

Abstract: Test substrates used to test semiconductor fabrication tools are reclaimed by reading from a database the process steps performed on each test substrate and selecting a reclamation process from a plurality of reclamation processes. The reclamation process can include crystal lattice defect or metallic contaminant reduction treatments for reclaiming each test substrate. Each test substrate is sorted and placed into a group of test substrates having a common defect or contaminant reduction treatment assigned to the test substrates of the group. Additional features are described and claimed.

Abstract: According to an aspect of the present invention, there is provided a template including: a template substrate; patterns for forming device patterns on a wafer substrate; and a charging monitoring pattern, a size of the charging monitoring pattern being equal to a largest pattern in the patterns for forming the device patterns.

Abstract: A method for fabricating a CMOS image sensor includes developing a semiconductor substrate provided with metal pads with tetramethylammonium hydroxide (TMAH), to etch the metal pads. In accordance with the method, it is possible to realize normal output of materials, which were previously scrapped due to problems including pad corrosion, appearance defects and bonding pad issues which may occur in the process of fabricating CMOS image sensors. As a result, advantageously, it is possible to reduce wafer scrap and improve product yield.

Abstract: The invention relates to a method and to an arrangement for localizing production errors in a semiconductor component part by generating excess charge carriers in the semiconductor component part and by determining the electric potential in said part. In order to be able to localize production errors with simple measures and without damaging the semiconductor component part, it is suggested that the semiconductor component part be stimulated to become luminescent and that the locally resolved luminescence intensity distribution be determined in order to determine the locally resolved distribution of the electric potential in the semiconductor component part.

Abstract: In an optical pulse generating apparatus including a metal layer having an incident/reflective surface adapted to receive incident light and output its reflective light as an optical pulse signal, a dielectric layer formed on an opposite surface of the metal layer opposing the incident/reflective surface, and a dielectric layer exciting unit for exciting the dielectric layer on a time basis, the incident light exciting surface plasmon resonance light in the metal layer while the dielectric layer is excited on a time basis, so that an extinction coefficient of the dielectric layer is made negative.

Abstract: A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of the shell. The method may include the step of testing the embedded first electrical part to determine whether the first electrical part is defective or functional. The method may also include the steps of providing a second electrical part, inserting the second electrical part within the cavity of the shell second side portion, establishing electrical communication between the first and second electrical parts if a test result of the first electrical part indicates that the first electrical part is functional, and finishing the chip. Also, the method may include the step of rejecting the first electrical part if the test result of the first electrical part indicates that the first electrical part is defective.

Abstract: An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability.

Abstract: A classification apparatus for the semiconductor substrate is provided with a bow measuring section which accepts silicon substrates and measures respective bows thereof. The classification apparatus is also provided with a bow judging section which, based on one or more standard value(s) set in advance, checks a measurement result by the bow measuring section against the standard value(s). The bow judging section judges to which of ranges defined based on the standard value(s) of the bow the measurement result by the bow measuring section belongs. Further, the classification apparatus is provided with a sorting section which accepts the silicon substrate having been measured by the bow measuring section and sorts the accepted silicon substrates based on the judgment results by the bow judging section. In other words, silicon substrates are grouped according to the bows by the sorting section. Then, respective silicon substrates are discharged in a grouped state.

Abstract: The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis.

Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.

Abstract: A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: Apparatus and method for manufacturing a semiconductor device through a layer material dimension analysis increase productivity. The method includes performing a semiconductor manufacturing process of at least one reference substrate and at least one target substrate in a semiconductor process device, detecting a reference spectrum and a reference profile for the reference substrate, determining a relation function between the detected reference spectrum and reference profile, detecting a real-time spectrum of the target substrate, and determining in real time a real-time profile of the target substrate processed in the semiconductor process device by using the detected real-time spectrum as a variable in the determined relation function.

Abstract: By using powerful data analysis techniques, such as PCR, PLS, CLS and the like, in combination with measurement techniques providing structural information, gradually varying material characteristics may be determined during semiconductor fabrication, thereby also enabling the monitoring of complex manufacturing sequences. For instance, the material characteristics of sensitive dielectric materials, such as ULK material, may be detected, for instance with respect to an extension of a damage zone, in order to monitor the quality of metallization systems of sophisticated semiconductor devices. The inline measurement data may be obtained on the basis of infrared spectroscopy, for instance using FTIR and the like, which may even allow directly obtaining the measurement data at process chambers, substantially without affecting the overall process throughput.

Abstract: An optical metrology model for the structure is obtained. The optical metrology model comprising one or more profile parameters, one or more process parameters, and a dispersion. A dispersion function that relates the dispersion to at least one of the one or more process parameters is obtained. A simulated diffraction signal is generated using the optical metrology model and a value for the at least one of the process parameters and a value for the dispersion. The value for the dispersion is calculated using the value for the at least one of the process parameter and the dispersion function. A measured diffraction signal of the structure is obtained using an optical metrology tool. The measured diffraction signal is compared to the simulated diffraction signal to determine one or more profile parameters of the structure. The fabrication tool is controlled based on the determined one or more profile parameters of the structure.

Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.

Abstract: A film thickness measurement method for measuring a change in film thickness of 0.3 ?m or less in a silicon wafer by FTIR, having an auxiliary film formation step for depositing an auxiliary film for measurement on a surface to be measured for the change in film thickness, an auxiliary film thickness measurement step for measuring the film thickness of the auxiliary film, a measurement step for measuring the film thickness of the auxiliary film after the change in film thickness, and a calculation step for calculating a change in film thickness of a back surface deposit from the result of the measurement step and the result of the auxiliary film thickness measurement step.

Abstract: Embodiments of the present invention provide an apparatus and method for processing substrates using a multiple screen printing chamber processing system that has an increased system throughput, improved system uptime, and improved device yield performance, while maintaining a repeatable and accurate screen printing process on the processed substrates. In one embodiment, the multiple screen printing chamber processing system is adapted to perform a screen printing process within a portion of a crystalline silicon solar cell production line in which a substrate is patterned with a desired material, and then processed in one or more subsequent processing chambers.

Abstract: A method and a system of alignment of an integrated circuit chip pick-and-place equipment with an origin of a wafer supporting these circuits, comprising optically searching on the wafer at least one reference pattern formed, on manufacturing of the integrated circuits, in a reference chip, the reference pattern being different from optically-recognizable patterns of the other chips.

Abstract: A method of forming a semiconductor thin film includes: a step of forming an amorphous semiconductor thin film over a transparent substrate; a step of forming a crystalline semiconductor thin film by irradiating the amorphous semiconductor thin film with laser light to provide heat treatment and thereby crystallizing the amorphous semiconductor thin film; and an inspection step of inspecting the crystalline semiconductor thin film. The inspection step includes a step of obtaining a transmission image of the crystalline semiconductor thin film by irradiating the crystalline semiconductor thin film with light from a rear side of the transparent substrate and taking an image, and a screening step of performing screening of the crystalline semiconductor thin film based on the obtained transmission image.