Abstract: The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and dielectrics, and segments of materials, such as magnetic materials and crystalline materials onto a variety of receiving substrates using energetic beam transfer methods. Also provided is a consumable intermediate comprising a transfer substrate and a transfer material coated thereon, wherein the transfer material may be comprised of pre-formed electronic devices or magnetic materials and crystalline materials that may be transferred to a variety of receiving substrates. Aspects of the present invention may also be used to form multi-device electronic components such as sensor devices, electro-optical devices, communications devices, transmit-receive modules, and phased arrays using the consumable intermediates and transfer methods described herein.

Abstract: A method for evaluating a semiconductor substrate is provided that can evaluate even a thin semiconductor substrate or a substrate with untreated surfaces, can evaluate a large quantity of semiconductor substrates for solar cells in a short time and can be used as in-line inspection in a production process of solar cells or the like. The method for evaluating a semiconductor substrate comprises a step of immersing a semiconductor substrate in an etching solution filled in a container, a step of irradiating the substrate being immersed in the etching solution with light via the etching solution to cause the substrate to emit photoluminescence, and a step of observing the emitted photoluminescence.

Abstract: In a workpiece process end point detection system, light is diffused and then light intensity or color is sensed. Optical noise is greatly reduced and more accurate end point detection can be made. A light emitter and a light sensor may be located within a workpiece process chamber. A housing around the light emitter and the light sensor seals out process fluids and also diffuses light passing through. The diffused light may be optically filtered before reaching the light sensor.

Abstract: Excitation light is irradiated onto a GaN layer on a silicon carbide substrate constituting a layered product that is set on a stage. Then light is emitted from a defective part caused by a structural defect of the silicon carbide substrate out of the GaN layer. By using this light luminescence phenomena, a position of a defective part of the silicon carbide substrate can be detected.

Abstract: During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.

Abstract: Structures formed on a semiconductor wafer are consecutively measured by obtaining first and second measured diffraction signals of a first structure and a second structure formed abutting the first structure. The first and second measured diffraction signals were consecutively measured using an angle-resolved spectroscopic scatterometer. The first measured diffraction signal is compared to a first simulated diffraction signal generated using a profile model of the first structure. The profile model has profile parameters, characterize geometries of the first structure, and an azimuth angle parameter, which define the angle between the plane of incidence beam and direction of periodicity of the first or second structure. One or more features of the first structure are determined based on the comparison.

Abstract: An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. Measures are: obtaining an image of a region PCA within the surface of a wafer including a region OGA pressed by a pressing member, at the center of which a chip just after probe-tested is located, by an imaging means such as a camera; comparing an image of a normal chip obtained in advance and an image of all the chips within the region PCA; and judging thereby whether an abnormal shape is caused or not in all the chips within the region PCA.

Abstract: An in-line, in-process or in-situ and non-destructive metrology system, apparatus and method provides composition, quality and/or thickness measurement of a thin film or multi-layer thin film formed on a substrate in a thin film processing system. Particularly, the subject invention provides a spectroscopic ellipsometer performing spectroscopic ellipsometry while the wafer is in a thin film processing system. In one form, the spectroscopic ellipsometer is associated with a wet bench system portion of the thin film processing system. The spectroscopic ellipsometer obtains characteristic data regarding the formed thin film to calculate penetration depth (Dp) for a thin film formed on the substrate. Particularly, the ellipsometer obtains an extinction coefficient (k) which is used to calculate penetration depth (Dp). Penetration depth (Dp), being a unique function of the extinction coefficient (k) provides the information for the composition, quality and/or thickness monitoring of the thin film.

Abstract: Methods and apparatus for assessing a constituent in a semiconductor substrate. Several embodiments of the invention are directed toward non-contact methods and systems for identifying an atom specie of a dopant implanted into the semiconductor substrate using techniques that do not mechanically contact the substrate with electrical leads or other types of mechanical measuring instruments. For example, one embodiment of a non-contact method of assessing a constituent in a semiconductor substrate in accordance with the invention comprises obtaining an actual reflectance spectrum of infrared radiation reflected from the semiconductor substrate, and ascertaining a plasma frequency value (?p) and a collision frequency value (?) for the semiconductor substrate based on the actual reflectance spectrum. This method can further include identifying a dopant type based on a relationship between dopant types and (a) plasma frequency values and (b) collision frequency values.

Abstract: One embodiment of the present invention includes a method for aligning a wafermap with a semiconductor wafer. The method may comprise assigning a location code to each of a plurality of dies on the wafermap. Each of the plurality of dies on the wafermap can correspond to each of a plurality of dies on the semiconductor wafer. The method may also comprise scanning an approximate location of a reference die on the semiconductor wafer with a die detection sensor based on the location code corresponding to a location of the reference die on the wafermap and determining a physical location of the reference die on the semiconductor wafer using the die detection sensor. The method may further comprise correlating the physical location of the reference die on the semiconductor wafer with the respective location code corresponding to the reference die on the wafermap.

Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.

Abstract: The invention provides an inspection apparatus and an inspection method for detecting defects, a punching apparatus, and a method for controlling a punching apparatus, for the purpose of immediate detection of debris from being lifted toward the surface of an insulating film for film carrier tape, which debris tends to occur during punching of the insulating film for film carrier tape by use of a punching mold, whereby the number of pieces having defects on the film surface caused by attachment of debris from being lifted or foreign matter is reduced to a minimum possible number.

Abstract: A subject of the present invention is to realize an impurity doping not to bring about a rise of a substrate temperature. Another subject of the present invention is to measure optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized. An impurity doping method, includes a step of doping an impurity into a surface of a solid state base body, a step of measuring an optical characteristic of an area into which the impurity is doped, a step of selecting annealing conditions based on a measurement result to meet the optical characteristic of the area into which the impurity is doped, and a step of annealing the area into which the impurity is doped, based on the selected annealing conditions.

Abstract: A method for thinning a semiconductor wafer, the method includes selecting a semiconductor wafer having a buried stop layer; and planarizing the semiconductor wafer to the buried stop layer to produce a thin semiconductor wafer.

Abstract: A rework station and a metrology device(s) are incorporated into a lithographic processing cell so that a faulty substrate can be reworked directly and reprocessed without, for example, an overhead involved in changing masks, etc.

Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.

Abstract: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.

Abstract: A method, apparatus, and computer program product for implementing inspection recipe services are provided. The apparatus includes a test structure including a semiconductor substrate and a number of arrays disposed on the semiconductor substrate. The arrays are linearly arranged and spaced equidistant. Each of the arrays corresponds to a reticle field and includes a number of cells. The test structure also includes a defect programmed into every third array. The defect is programmed in the same location on each third array. The test structure further includes an alignment site defined on the test structure for providing a point of reference upon inspection. The alignment site, in conjunction with a modified reticle pitch extending the distance of one reticle field plus a portion of an adjacent reticle field, are used to perform a random mode inspection of selected arrays in the test structure.

Abstract: A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures extending substantially perpendicular from an upper surface of the substrate, directing an ion beam toward the substrate, the plurality of shadowing structures interrupting an incident angle of the ion beam to define implanted and non-implanted portions of the substrate. The method further includes measuring the dose of implanted species within the substrate, determining an implanted surface area as a function of measuring the dose of implant, determining non-implanted surface area based on the implanted surface area, and obtaining the ion beam angle as a function of the non-implanted surface area.

Abstract: A method of indicating the progress of a sacrificial material removal process, the method, comprising; freeing a portion of a member, the member being disposed in a cage and laterally surrounded by the sacrificial material; and preventing the freed portion of the member from floating away by retaining the freed member.

Abstract: Provided are a method of verifying line reliability and a method of fabricating a semiconductor substrate to improve the line reliability. The semiconductor device fabricating method includes: forming an interlayer insulating layer having a via hole on a semiconductor substrate; forming a seed layer on the interlayer insulating layer; performing an ammonia plasma process on the seed layer to reduce the surface of the seed layer; and forming a copper line using the surface roughness reduced seed layer.

Abstract: A method wherein a substrate is provided, wherein, in a scanning step, structures already applied to the substrate are detected by at least one scanning provision of a processing head, wherein the processing head is provided with at least one lighting provision, which lighting provision locally lights the applied lacquer structure in a lighting step by using the information obtained with the scanning step. Further, the invention discloses an apparatus for carrying out the method is described, which apparatus is provided with a processing head which is movable relative to a substrate carrier, wherein the processing head comprises at least one scanning provision and at least one lighting provision.

Abstract: Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in the trench area and form a step between the trench area and the field area; etching to partially etch the trench; determining a target etch duration (tD) for etching to the target depth (DT); and etching the trench to the target depth (DT) for a period approximately equal to the target etch duration (tD). The target etch duration tD may be fed forward for recessing another trench to the target depth DT. The method does not require a send ahead wafer, is fully compatible with conventional automated processes and provides in-situ etch time correction to each wafer.

Abstract: A method for automatic determination of a state of a substrate in a plasma processing chamber is provided. Substrate reflectance data is collected in a processing chamber prior to processing to be analyzed with reference reflectance data to determine if the substrate state meets a control criterion. The substrate state may define the thickness and the qualities of the films on the substrate, the critical dimensions of the different layers on the substrate. The reflectance data is analyzed using a multi-variant analysis technique, such as principle component analysis. In addition to analyzing substrate state prior to processing, substrate reflectance could also be collected in a processing chamber during processing to be analyzed with reference reflectance data to further determine if the substrate state and/or the substrate processing are meeting a control criterion.

Abstract: The present invention provides an evaluation method for a crystal defect in a silicon single crystal wafer based on an infrared laser scattering tomograph method, wherein at least, the silicon single crystal wafer is irradiated with a laser beam, and light that enters the silicon single crystal wafer is scattered by a crystal defect, and the scattered light is detected to evaluate a Direct Surface Oxide Defect (DSOD) and a void defect smaller than the DSOD in the silicon single crystal wafer. As a result, the evaluation method for a crystal defect in a silicon single crystal wafer that can simply and precisely evaluate, e.g., a small DSOD, which can be conventionally evaluated based on a Cu deposition method alone, without requiring a wasteful cost.

Abstract: The invention provides a method for manufacturing an integrated circuit. The method, in one embodiment, includes inspecting a semiconductor wafer including a plurality of die for a defect, the inspecting providing an image of the semiconductor wafer including the defect. The method further includes identifying an area of the semiconductor wafer from the image, wherein the identified area encompasses at least those die including any portion of the defect, and dicing the semiconductor wafer into individual die. The die defined by the identified area, in this embodiment, are then discarded.

Abstract: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

Abstract: A method of a single wafer wet/dry cleaning apparatus comprising: a transfer chamber having a wafer handler contained therein; a first single wafer wet cleaning chamber directly coupled to the transfer chamber; and a first single wafer ashing chamber directly coupled to the transfer chamber.

Abstract: A pattern shape evaluation method comprising detecting an edge of an evaluation target pattern from an image of the evaluation target pattern to output the edge as a first edge, detecting an edge of a reference pattern from an image of the reference pattern to output the edge as a second edge, performing a relative scan of the first edge and the second edge to superpose the first edge onto the second edge, and outputting a resulting edge as a third edge, calculating a characteristic amount indicating characteristics of the third edge from the third edge, and deriving a characteristic amount function which provides the characteristic amount against relative coordinates in the relative scan and comparing the characteristic amount function with a preset value to judge whether or not the evaluation target pattern is good.

Abstract: A laser diode chip is scanned and irradiated with laser light penetrating the interior of crystal of a chip and having a wavelength which produces no electromotive force by optical excitation. When the temperature of a chip 1 increases through irradiation, a thermoelectromotive force is generated in a crystal abnormal part of the chip 1 by a Seebeck effect. This thermoelectromotive force is detected from a change of a voltage or current appearing between the anode and cathode of the chip 1 and displayed at a CRT to thereby detect defects inside the crystal.

Abstract: A method of measuring thickness of a layer in an image sensor and pattern for the same are disclosed, by which layer thickness measurement of an image sensor is enabled in the course of fabrication. Embodiments relate to a method of measuring thickness of a layer in an image sensor in which a first epitaxial layer may be formed over a semiconductor substrate. A photoresist pattern may be formed by coating and patterning photoresist over the first epitaxial layer. A plurality of trenches in the first epitaxial layer may be formed by performing a dry etch on the photoresist pattern. A doped layer may be formed at a bottom of each of the trenches by implanting antimony (Sb) using the photoresist pattern as a mask. After removing the photoresist pattern, a second epitaxial layer may be formed over the first epitaxial layer including a plurality of the trenches. The thickness of the second epitaxial layer may be measured to determine the thickness of one of the doped layers.

Abstract: A method of measuring a degree of crystallinity of a polycrystalline silicon substrate includes obtaining a Raman spectrum graph by irradiating a polycrystalline silicon substrate with a laser beam; and calculating a degree of crystallinity of the polycrystalline silicon substrate from the Raman spectrum graph using the following formula: (degree of crystallinity)=(area of polycrystalline peak)/[(area of amorphous peak)+(area of polycrystalline peak)].

Abstract: An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

Abstract: A method for reducing surface recombination in an area next to a mesa in devices containing active and passive sections. This is obtained by growing, by metalorganic vapor phase epitaxy (MOVPE), a thin epitaxial layer of material with larger bandgap than a waveguide material and preferably smaller surface recombination rate than the waveguide material. This thin layer is preferably non-intentionally doped to avoid creating a surface leakage path, thin enough to allow for carrier to diffuse to and thermalize in the waveguide layer and thick enough to prevent carriers to tunnel through it.

Abstract: A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a test pattern for a different process step is formed in a blading area of the photomask. Also, a method for forming test structures is disclosed in which the photomask is exposed to transfer the test pattern to a semiconductor substrate. The process step that is associated with the test pattern is then performed, forming a test structure on the semiconductor substrate. By utilizing blading areas of photomasks and including test patterns for different process steps on the same photomask, more test structures can be obtained, without the need to generate additional photomasks for testing purposes.

Abstract: A method for preserving semiconductor feature opening profiles for metrology examination including providing semiconductor wafer having a process surface comprising semiconductor feature openings; blanket depositing over the semiconductor feature openings to substantially fill the semiconductor feature openings at least one layer of material comprising silicon oxide; and, preparing a portion of the semiconductor wafer in cross sectional layout for metrology examination.

Abstract: A system and method are provided for qualifying or calibrating lithographic apparatus or parts therefor, using a predetermined objective criterion such as Chauvenet's criterion is used to reject measurement points, individually, by field or by substrate.

Abstract: A method for inspecting a semiconductor wafer fabricated for image sensing operation that has had a transparent protective tape layer applied to a front or active wafer surface. The method includes quantifying chip defects in the image sensor wafer that lie under the protective layer using automatic disposition equipment.

Abstract: OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies, each having different design parameter values for line width and lateral distance between adjacent lines.

Abstract: We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.

Abstract: An integrated circuit structure has an IC chip, at least a functional bump, and at least a dummy bump positioned on a joint surface of the IC chip. A terminal surface of the dummy bump is different in appearance from a terminal surface of the functional bump, which improves an inspection process during production of the IC chip.

Abstract: A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of the associated one of the plurality of layers, and (3) determining dynamic processing progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the processing.

Abstract: A method of forming a protection layer on a specimen for TEM inspection and a method of forming a specimen for TEM inspection are provided. The method of forming a protection layer on a specimen for TEM inspection generally comprises coating a wafer slice comprising an inspection point with a protection material and compressing the protection material to the wafer slice. The method of forming a specimen for TEM inspection generally comprises cutting a wafer slice comprising an inspection point from a wafer, forming a protection layer on the wafer slice, forming a first preliminary specimen by cutting the wafer slice, forming a second preliminary specimen by grinding the first preliminary specimen, and forming a TEM specimen by etching portions of the second preliminary specimen.

Abstract: Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the variable depth is modulated based on the local topography of the wafer. The resultant topography of the applied film and wafer is substantially planar (e.g., within approximately 100 nm) across the wafer.

Abstract: A method for calculating a process center for a chuck in a processing chamber is provided. The method includes generating pre-processing and post-processing measurement data points, which is perform by measuring thickness of a film substrate at a set of orientations and a set of distances from a geometric center of the substrate. The method also includes comparing the pre-processing and post-processing measurement data points to calculate a set of etch depth numbers. The method further includes generating etch profiles for the set of orientations. The method yet also includes extrapolating a set of radiuses, which is associated with a first etch depth, from the etch profiles. The method yet further includes generating an off-centered plot, which is a graphical representation of the set of radiuses versus the set of orientations. The method more over includes calculating the process center by applying a curve-fitting equation to the off-centered plot.

Abstract: A method monitors a thickness of a subject film deposited on an underlying structure, the underlying structure contains at least one thin film formed on a substrate. The method includes determining thickness data of the underlying structure and storing the thickness data of the underlying structure in a thickness memory; measuring profile of optical spectrum of the subject film on the underlying structure; reading the thickness data of the underlying from the thickness memory; calculating theoretical profiles of the optimal spectrum of the subject film based upon corresponding candidate film thicknesses of the subject film and the thickness data of the underlying structure; and searching a theoretical profile of the subject film, which is closest to the measured profile of optical spectrum of the subject film so as to determine a thickness of the subject film.

Abstract: Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation (12) on the front side of the semiconductor wafer (10) designed to accept laser scribing (22), and laser scribing the scribe foundation (12). Disclosed embodiments include a semiconductor wafer (10) having a scribe foundation (12) of layered dielectric (30) and metal (34) on the front side. According to disclosed embodiments of the invention, the formation of a scribe foundation (12) is performed in combination with the formation of a top level metal layer (34) on the semiconductor wafer (10) methods for manufacturing.

Abstract: A system and method for matching chip and package terminals and for packaging integrated circuits. Various aspects of the present invention may comprise receiving as input a first list of chip terminal identifiers and a second list of package terminal identifiers. The first and second lists may be analyzed with a first string-matching algorithm to determine a first set of matching pairs of chip terminals and package terminals. The first and second lists may also be analyzed with a second string-matching algorithm to determine a second set of matching pairs of chip terminals and package terminals. The first and second sets of matching pairs may be compared to identify common matching pairs between the first and second sets of matching pairs. An indication of the common matching pairs may then be output.

Abstract: The present invention attracts a wafer 6, placed on a susceptor 5, toward the susceptor 5 by the electrostatic attractive power of an electrostatic chuck electrode 7, varies the output voltage of a variable direct current power source 23 for the electrostatic chuck electrode 7 while measuring the temperature of the wafer 6 by a temperature detection sensor 21; and detects the potential of the wafer 6 based on the output voltage of the variable direct current power source 23 at a time when the temperature of the wafer 6 peaks.