Abstract: The invention can provide a method of processing a substrate using multi-pitch scatterometry targets (M-PSTs) for de-convolving lithographic process parameters during Single-Patterning (S-P), Double-Patterning (D-P) procedures, and Double-Exposure (D-E) procedures used to control transistor structures. The M-PSTs) can have critical dimension (CD) and sidewall angle (SWA) sensitivity to exposure focus variations, exposure dose variations, and post exposure bake (PEB) temperature variations. In addition, the variation can be de-convolved so that the individual measurement process variable contributor can be identified.

Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion.

Abstract: The present invention discloses an active matrix organic electroluminescence device comprising a thin-film transistor, an organic electroluminescence device, and an interlayer deposited between the thin-film transistor and the organic electroluminescence device, wherein the interlayer is made of cationic ultraviolet-curing adhesive comprising epoxy resin or modified epoxy resin, diluting agent, cationic photo initiator. The interlayer solves poor adhesiveness between the driving circuit and the organic electroluminescence device, and improves the moisture and oxygen proof ability. The preparation method is simple, effective, and able to lower the cost and difficulty, and greatly improve the yield rate.

Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Abstract: According to one embodiment, a first substrate and a second substrate are pressed from an opposite surface of a joint surface of the second substrate such that a joint surface of the first substrate and the joint surface of the second substrate are in contact with each other. The second substrate is restrained by a member to provide a gap between the joint surfaces. It is determined, based on a temporal change of a joint interface calculated based on an image imaged from the opposite surface side of the joint surface, whether joining is normally performed.

Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.

Abstract: An etching method capable of controlling the film thickness of a hard mask layer uniformly is provided. A plasma etching is performed on a native oxide film by using an etching gas containing, for example, CF4 and Ar while a thickness of a silicon nitride film is being monitored and the etching is finished when the thickness of the silicon nitride film reaches a predetermined value. Then, a plasma etching is performed on a silicon substrate by employing an etching gas containing, for example, Cl2, HBr and Ar and using the silicon nitride film as a mask while a depth of a trench is being monitored and the etching is finished when the depth of the trench reaches a specified value.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: A method for staining a sample includes the following steps. A test device is provided. The test device is sampled to obtain a sample. The sample includes a substrate, an active area disposed within the substrate and having a first doped substrate region and a second doped substrate region, at least one gate disposed between the first doped substrate region and the second doped substrate region, and an exposed shallow trench isolation embedded in the substrate and surrounding the active area. A first staining procedure is then carried out to selectively remove the shallow trench isolation to form a first void and to entirely expose the active area. A second staining procedure is subsequently carried out to selectively stain the first doped substrate region and the second doped substrate region to form a second void.

Abstract: According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.

Abstract: The present invention relates generally to steganography and data hiding. One claim recites an object including: electronic processing circuitry having an operating or performance metric associated therewith; and steganographic indicia carried by the object, the steganographic indicia is usable as an index to verify the operating or performance metric. Another claim recites an apparatus including: electronic memory; and machine-readable indicia usable as a registry index including data that provides an indication regarding an expected capacity of the electronic memory. Other combinations are described and claimed as well.

Abstract: A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M6), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.

Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.

Abstract: A method and a device for inspecting surface coatings on workpieces, in particular of lacquer coatings, using an image capture and/or image processing system. The image capture and/or image processing system is designed to measure and/or process electromagnetic radiation from surface coating and/or a layer beneath it which is at least partially outside of the visible wavelength range.

Abstract: An optical property evaluation apparatus includes: a light conversion filter converting light emitted from an LED chip or a bare LED package, which is to be evaluated, into a different wavelength of light, and emitting a specific color of light; and an optical property measurement unit receiving the specific color of light emitted from the light conversion filter and measuring the optical properties of the received light.

Abstract: The invention can provide apparatus and methods for processing substrates and/or wafers in real-time using at least one Direct Current (DC)/Radio Frequency (RF) Hybrid (DC/RFH) processing system and associated Direct Current/Radio Frequency Hybrid (DC/RFH) procedures and DC/RFH process parameters and/or DC/RFH models.

Abstract: Disclosed is a method (300) of manufacturing at least one semiconductor photovoltaic cell or module and for classifying semiconductor material. In one implementation (500) the method involves luminescence imaging a wafer at each of a plurality of stages (312-324) of the manufacturing process, and comparing at least two images obtained from the imaging step in respect of the same wafer to identify the incidence or growth of a manufacturing process induced fault. The wafer is removed (351-356) from the manufacturing process (310) where a process induced fault is identified that exceeds a predetermined level of acceptability or the fault may be remedied, or the wafer passed to an alternate manufacturing process to match its characteristics. In an alternate implementation the method comprises classifying semiconductor material.

Abstract: A light emitting device and method of producing the same is disclosed. The light emitting device includes a light emitting semiconductor, an encapsulation layer, wherein the light emitting semiconductor is disposed within the encapsulation layer, a phosphor layer provided over the encapsulation layer, and an air gap provided between the encapsulation layer and the phosphor layer.

Abstract: In a method of manufacturing a silicon carbide semiconductor device, a trench and a thickness measurement section are formed in a surface of a semiconductor substrate made of silicon carbide. The thickness measurement section includes a plurality of grooves and a protruding portion provided between the grooves so as to have a predetermined width. When an epitaxial layer made of silicon carbide is grown, a thickness of the epitaxial layer formed on the surface of the semiconductor substrate is measured by calculating a difference in height between a surface of the epitaxial layer formed on a portion of the surface of the semiconductor substrate different from the thickness measurement section and a top surface of the protruding portion. The predetermined width is less than a surface migration amount of atoms during growth of the epitaxial layer.

Abstract: The present invention provides an LED and method of manufacture in which white light is produced. Specifically, under the present invention, a wavelength of a light output by an LED (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Based on the wavelength measurement, a conformal coating is applied to the LED. The conformal coating has a phosphor ratio that is based on the wavelength. Moreover, the phosphor ratio is comprised of at least one of the following colors: yellow, green, or red. The light output of the LED is then converted to white light using the conformal coating. In a typical embodiment, these steps are performed at the wafer level so that uniformity and consistency in results can be better obtained. However, it should be understood that the same teachings could be applied at the chip level. Moreover, several different approaches can be implemented for isolating the coating area. Examples include the use of a paraffin wax, a silk screen, or a photo resist.

Abstract: Provided is a light emitting device fabricating apparatus, which includes a light emitting device, first and second contact parts, a power source part, a loading plate, and a chamber. The first and second contact parts are connected to the light emitting device to apply a first current to the light emitting device. The power source part supplies power to the first and second contact parts. The loading plate supports and heats the light emitting device. The chamber accommodates the light emitting device, the first and second contact parts, and the loading plate, and has a vacuum state or oxygen atmosphere.

Abstract: Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously.

Abstract: A semiconductor oxidation apparatus is provided with a sealable oxidation chamber defined by walls, a base provided within the oxidation chamber and configured to support a semiconductor sample, a supply part configured to supply water vapor into the oxidation chamber to oxidize a specific portion of the semiconductor sample, a monitoring window provided in one of the walls of the oxidation chamber and disposed at a position capable of confronting the semiconductor sample supported on the base, a monitoring part provided outside the oxidation chamber and capable of confronting the semiconductor sample supported on the base via the monitoring window, and an adjusting part configured to adjust a distance between the base and the monitoring part.

Abstract: A method of forming a semiconductor thin film includes a highly sensitive inspection method for detecting lateral crystals and a crystallizing method. In the crystallizing method, the time-based pulse width of a laser SXL is modulated and an approximate band-like crystal silicon film SPSI is formed in a desired region while scanning the substrate SUB1 bidirectionally in the X and ?X directions. In the inspection method, an inspection beam PRO1 is irradiated to the substrate just after the laser SXL is turned off. A protrusion TOKI will be formed on the silicon film portion where the laser SXL is turned off if the state of the silicon film is that of a lateral crystal SPSI. The inspection beam PRO1 is scattered by the protrusion TOKI and observed by a detector. If the state of the silicon film is granular crystal GGSI or aggregated film AGSI, such a protrusion TOKI is not observed.

Abstract: After a metal cap layer is laminated on a semiconductor laminated structure, a waveguide ridge is formed, the waveguide ridge is coated with an SiO2 film, and a resist is applied; then, a resist pattern is formed, the resist pattern exposing the surface of the SiO2 film on the top of the waveguide ridge, and burying the SiO2 film in channels with a resist film having a surface higher than the surface of the metal cap layer of the waveguide ridge and lower than the surface of the SiO2 film of the waveguide ridge; the SiO2 film is removed by dry etching, using the resist pattern as a mask. The metal cap layer is removed by wet etching, and a p-GaN layer of the waveguide ridge is exposed to form the electrode layer.

Abstract: A method, performed in connection with bevel etching of a substrate, for improving bevel-etch repeatability among substrates, is disclosed. The method includes providing an optical arrangement and ascertaining at least one bevel edge characteristic of a bevel edge of said substrate. The method also includes deriving at least one compensation factor from said at least one bevel edge characteristic, said at least one compensation factor pertaining to an adjustment in a bevel etch process parameter. The method further includes performing said bevel etching utilizing said at least one compensation factor.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: The temperature of an object such as a semiconductor wafer that includes silicon can be determined based on the variation of the optical absorption coefficient of silicon with temperature. Temperatures above about 850° C., can be found by measuring phenomena that are affected by the magnitude of the optical absorption coefficient, especially at wavelengths >˜1 ?m. Phenomena could include measuring light reflected, transmitted, emitted, absorbed, or scattered by the wafer and deriving the absorption coefficient from the measurements and then deriving temperature from the absorption coefficient. Temperature could be determined from a model relating phenomena directly to temperature, the model constructed based on absorption behavior and techniques discussed herein. The resulting temperature could be used to calibrate or control a rapid thermal processing chamber or other apparatus.

Abstract: In accordance with an embodiment, a pattern evaluation system includes an image acquisition unit, a plurality of image processing units, and a control unit which controls the plurality of image processing units. The image acquisition unit loads a series of images of a pattern to be evaluated. The images are acquired at a first speed. The plurality of image processing units process the series of images at a second speed and then output a result of the evaluation of the pattern to be evaluated. The control unit acquires the first and second speeds, estimates the number of the image processing units which allow the time for acquiring the series of images to be substantially the same as the time for processing the series of images, and allocates the estimated image processing units to the processing of the series of images.

Abstract: In a group-III nitride semiconductor laser device, a laser structure includes a support base comprising a hexagonal group-III nitride semiconductor and having a semipolar principal surface, and a semiconductor region provided on the semipolar principal surface of the support base. An electrode is provided on the semiconductor region of the laser structure. An angle between a normal axis to the semipolar principal surface and the c-axis of the hexagonal group-III nitride semiconductor is in a range of not less than 45° and not more than 80° or in a range of not less than 100° and not more than 135°. The laser structure includes a laser stripe extending in a direction of a waveguide axis above the semipolar principal surface of the support base. The laser structure includes first and second surfaces and the first surface is a surface opposite to the second surface.

Abstract: An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.

Abstract: A method for forming a light emitting device includes providing a light emitting diode (LED) configured to emit light of a first color and providing a plurality of semi-spherical lenses made of a silicone material that contains no phosphor material. Each of the lenses has a layer of phosphor material attached thereto. The method also includes testing the plurality of lenses to select a subset of lenses that converts light of the first color to light of a second color. The method further includes forming the light emitting device using the LED, one of the selected subset of lenses, and a heat conductive substrate. In an embodiment, after the testing of the plurality of lenses, one of the selected subset of lenses is disposed overlying the LED. In another embodiment, the testing of the plurality of lenses is conducted with a light source other than the LED.

Abstract: A method and system for defect localization includes: (i) receiving a test structure that includes at least one conductor that is at least partially covered by an electro-optically active material; (ii) providing an electrical signal to the conductor, such as charge at least a portion of the conductor; and (iii) imaging the test structure to locate a defect.

Abstract: Computer-implemented methods that include correlating a backside defect with a frontside defect detected on a specimen are provided. The defects are correlated if a portion of the backside defect on the backside of the specimen is opposite to a portion of the frontside defect on the frontside of the specimen. In particular, the defects are correlated if the portion of the backside defect is aligned with the portion of the frontside defect along an axis perpendicular to the frontside and the backside of the specimen. The method may also include altering a parameter of a process tool in response to the backside defect to reduce frontside defects on additional specimen processed in the process tool. Computer-implemented methods for analyzing data representing spatial characteristics of backside defects detected on a specimen to classify the backside defects are also provided. Analyzing the data may include spatial signature analysis of the data.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: A semiconductor device includes: a semiconductor substrate, first and second internal electrodes provided on a surface of the semiconductor substrate; a first through electrode which penetrates through the semiconductor substrate in a thickness direction and is electrically connected to the first internal electrode; and a second through electrode connected to the second internal electrode, and the second internal electrode is thinner than the first internal electrode. The second through electrode may penetrate through the second internal electrode.

Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.

Abstract: A solid-state imaging device includes the following elements. A photoelectric conversion section is arranged in a semiconductor layer having a first surface through which light enters the photoelectric conversion section. A signal circuit section is arranged in a second surface of the semiconductor layer opposite to the first surface. The signal circuit section processes signal charge obtained by photoelectric conversion by the photoelectric conversion section. A reflective layer is arranged on the second surface of the semiconductor layer opposite to the first surface. The reflective layer reflects light transmitted through the photoelectric conversion section back thereto. The reflective layer is composed of a single tungsten layer or a laminate containing a tungsten layer.

Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Abstract: A deposition film shape simulation method for calculating a thickness of a thin-film formed by supplying deposition species on a substrate surface, includes: changing a parameter to be used in the calculation depending on the thickness of the deposited thin-film.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2 ?S to about 8 ?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.

Abstract: A system and method is disclosed for reducing processing errors during the fabrication of integrated circuit wafers. A 2D dot matrix wafer scribe that contains coded information is placed on a wafer. The coded information contains wafer information such as the wafer lot number. The wafer is then placed in an ion implantation system. A camera in the ion implantation system is then used to photograph the dot matrix wafer scribe on the wafer. The information about the wafer is then decoded from the photograph of the dot matrix wafer scribe. A station controller that operates the ion implantation system then uses the information from the dot matrix wafer scribe to determine whether the wafer is suitable for ion implantation. The wafer is implanted only when the information from the dot matrix wafer scribe matches information about the wafer that has been previously stored in the station controller.

Abstract: A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated.

Abstract: A method for evaluating a semiconductor substrate is provided that can evaluate even a thin semiconductor substrate or a substrate with untreated surfaces, can evaluate a large quantity of semiconductor substrates for solar cells in a short time and can be used as in-line inspection in a production process of solar cells or the like. The method for evaluating a semiconductor substrate comprises a step of immersing a semiconductor substrate in an etching solution filled in a container, a step of irradiating the substrate being immersed in the etching solution with light via the etching solution to cause the substrate to emit photoluminescence, and a step of observing the emitted photoluminescence.

Abstract: An aspect of the invention provides a method of manufacturing a method of manufacturing a semiconductor element comprises the steps of: growing epitaxially a semiconductor layer on top of a semiconductor substrate; forming a patterned portion of the grown semiconductor layer by forming a pattern by a patterning process on top of the grown semiconductor layer; removing a portion of the semiconductor layer other than the patterned portion by a first etching method with a first etchant; and immersing a resultant from the first etching method in a second etchant that etches only the semiconductor substrate by a second etching method thereby removing the substrate from the semiconductor layer.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

Abstract: Disclosed is a semiconductor device fabrication method that comprises a fabrication process, wherein device structural patients are formed in a device formation area inside a chip formation area and wherein inspection patterns are formed in multiple inspection areas inside the aforementioned chip formation area, on the film-side of a semiconductor wafer that has a film for pattern formation, and an inspection process. The aforementioned inspection patterns have a repeating pattern with identical lines and identical spaces formed in a first inspection area among the aforementioned multiple inspection areas, and a uniform pattern without spaces formed in a second inspection area among the multiple inspection areas.

Abstract: Embodiments relate to a method of manufacturing an image sensor which includes forming a plurality of lower layers over a semiconductor substrate. A first passivation layer may be formed over the lower layers to protect the lower layers. The first passivation layer may be formed in a pixel region and a peripheral region with different thicknesses. A spin-on-glass (SOG) layer may be formed over the first passivation layer. A second passivation layer may be formed over the SOG layer. Array etching may be used to form a concave area in the semiconductor substrate. A plurality of micro lenses may be formed over the bottom surface of the concave area.

Abstract: A substrate inspection apparatus 1-1 (FIG.