Abstract: A two-dimensional image of an alignment mark 30 is acquired by an alignment scope 15 at step S61, and the two-dimensional image acquired at step S61 is converted to a light-intensity signal line by line at step S62. A selection as to whether each line signal is valid or unnecessary is made at step S63. The amount of positional deviation of the alignment mark 30 is calculated using only valid line signals at step S64.

Abstract: Automated defect sourcing system identifies root-causes of yield excursion due to contamination, process faults, equipment failure and/or handling in timely manner and provides accurate timely feedback to address and contain the sources of yield excursion. A signature bank stores known wafer surface manufacturing defects as defect signatures. The signature of a manufacturing defect pattern is associated with a type of equipment or process, and used to source the manufacturing defects and to provide process control for changing and/or stopping yield excursion during fabrication. A defect signature recognition engine matches wafer defects against the signature bank during wafer fabrication. Once the defect signature is detected during fabrication, handling and/or disposing the root-cause of the corresponding defect is facilitated using messages according to an event handling database. Optionally, a real-time process control for wafer fabrication is provided.

Abstract: In the case of a method for producing a fluid device with a fluid structure having an active height, a basic wafer is provided, which comprises a supporting substrate, an insulating layer on the supporting substrate and a patterned layer on the supporting substrate, the thickness of the patterned layer determining the active height of the fluid structure. Following this, the fluid structure is produced in the patterned layer of the basic wafer, said fluid structure extending through the semiconductor layer. A transparent wafer is then applied so that the fluid structure is covered. Subsequently, the supporting substrate and the insulating layer are removed from the back so that the fluid structure is exposed at a second surface of the patterned layer. Finally, a second transparent wafer is attached to the exposed second surface of the semiconductor layer so that the fluid structure is covered. The essential parameter of the fluid device, viz.

Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

Abstract: The invention relates to a method for enabling repair of a defect in a substrate, particularly the invention provides a method and apparatus for enabling repair of a pattern shape in a semiconductor device, which has not been able to be practiced because of lack of a suitable method, and further provides a method for manufacturing the semiconductor device using those. A method for repairing the pattern shape of a substrate having an imperfect pattern is used, which includes (a) a step for inspecting the substrate and thus detecting the imperfect pattern, and (b) a step for repairing the pattern shape by performing etching or deposition to the detected imperfect-pattern using radiation rays. Moreover, apparatus for repairing a pattern shape of a via-hole in a wafer having an imperfect via-hole is used, which has a defect inspection section for detecting the imperfect via-hole, and an etching section for etching the imperfect via-hole using a fast atom beam.

Abstract: To evaluate the adequacy of a profile model, one or more types of process control to be used in controlling a fabrication process are selected. Profile model parameters and acceptable ranges for the profile model parameters are selected. A first and second metrology tools are selected. Statistical metric criteria that define an acceptable amount of variation in measurements obtained using the first and second tools are set. A profile model is selected. A measurement of the profile model parameters is obtained using the first tool and the selected profile model. A measurement of the one or more profile model parameters is obtained using the second tool. Statistical metric criteria are calculated based on the measurements of the one or more profile model parameters obtained using the first and second tools. The calculated and set statistical metric criteria are compared to evaluate the adequacy of the selected profile model.

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract: Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.

Abstract: A method and system for determining a substrate type during a seasoning process is presented. An optical signal is acquired from a process in a plasma processing system, and the optical signal is compared to a pre-determined threshold value. Depending upon the comparison, the substrate type is determined to be of a correct type, or an incorrect type.

Abstract: The object of the present invention is to provide an inspection apparatus for liquid crystal drive substrates that improves the inspection accuracy of liquid crystal drive substrates, judges defect type more accurately, and does not cause a decrease in throughput.

Abstract: A substrate defining an insulating surface layer portion and formed with a wiring groove filled with a wiring line the wiring line is electrically connected to a conductive member. The conductive member occupies an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface. An insulating first film is formed on the first surface. A via hole is formed through the first film. The via hole is formed so that a boundary between the wiring line and the insulating surface layer portion passes through the inside of the via hole. The bottom of the via hole is observed with an apparatus for obtaining image information by utilizing secondary electrons and reflection electrons, to judge whether a state of the bottom of the via hole is accepted or rejected.

Abstract: A method for manufacturing and grading OLED devices is described, comprising the steps of: a) manufacturing OLED devices having a plurality of pixels; b) measuring pixel brightness and uniformity variation of each of the OLED devices prior to burning-in the OLED devices; c) correcting the pixel brightness and uniformity variation of each of the OLED devices prior to burning-in the OLED devices; d) grading each of the corrected OLED devices prior to burning-in the OLED devices; e) burning-in OLED devices graded as acceptable prior to burning-in the OLED devices; f) measuring burned-in pixel brightness and uniformity variation of each of the burned-in OLED devices; g) re-correcting the pixel brightness and uniformity variation of each of the burned-in OLED devices; and h) grading each of the re-corrected, burned-in OLED devices.

Abstract: Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

Abstract: A method for detecting photoresist residue during semiconductor device manufacture includes developing photoresist on a surface of a semiconductor device to expose portions of the surface A plurality of etch paths are then partially etched into the surface and inspected to determine their depths.

Abstract: A system for analyzing a thin film uses an energy beam, such as a laser beam, to remove a portion of a contaminant layer formed on the thin film surface. This cleaning operation removes only enough of the contaminant layer to allow analysis of the underlying thin film, thereby enhancing analysis throughput while minimizing the chances of recontamination and/or damage to the thin film. An energy beam source can be readily incorporated into a conventional thin film analysis tool, thereby minimizing total analysis system footprint. Throughput can be maximized by focusing the probe beam (or probe structure) for the analysis operation at the same location as the energy beam so that repositioning is not required after the cleaning operation. Alternatively, the probe beam (structure) and the energy beam can be directed at different locations to reduce the chances of contamination of the analysis optics.

Abstract: A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one or more chips of a silicon substrate; forming a file containing the coordinates of each potential transient defect on the chip; converting the file into a CAD image layer capable of displaying such potential transient defects; and displaying such potential transient defects superimposed over a CAD image of the actual circuit to permit visual inspection of the compound CAD image and to permit optional action to be taken in view of such potential transient defects.

Abstract: Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure. Far each localized defect, the same charged particle beam based tool may then be used to generate a high resolution image of the localized defect whereby the high resolution image can later be used to classify the each defect. In one embodiment, the defect's presence and location are determined without rotating the test structure relative to the charged particle beam.

Abstract: An edge bead removal measurement method includes determining an edge of a wafer about a circumference of the wafer. A location of a wafer notch on the edge of the wafer is determined. A location of a center of the wafer is determined. A distance from the edge of the wafer to an edge bead removal line about the circumference of the wafer is determined.

Abstract: In a thin film processing method and system, a film thickness is regulated by using electron beams irradiated from a plurality of electron beam tubes onto a film of varying thickness formed on an object to be processed, wherein the output powers or beam irradiation times of the electron beam tubes are individually controlled according to a distribution of the thickness. In the method and system, electric charges charged in a film of an object to be processed can be removed also.

Abstract: There is provided by this invention a wafer probe for measuring plasma and surface characteristics in plasma processing environment that utilizes integrated sensors on a wafer substrate. A microprocessor mounted on the substrate receives input signals from the integrated sensors to process, store, and transmit the data. A wireless communication transceiver receives the data from the microprocessor and transmits information outside of the plasma processing system to a computer that collects the data during plasma processing. The integrated sensors may be dual floating Langmuir probes, temperature measuring devices, resonant beam gas sensors, or hall magnetic sensors. There is also provided a self-contained power source that utilizes the plasma for power that is comprised of a topographically dependent charging device or a charging structure that utilizes stacked capacitors.

Abstract: A semiconductor wafer comprises a wafer formed of a semiconductor material having a peripheral edge portion and a repeating mark on the edge portion of the wafer to allow identification of the wafer. Also described is a method of identifying and tracking these semiconductor wafers.

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.

Abstract: Provided is a fabrication alignment technique for a light guide screen. A plurality of light guide layers are provided. Each light guide layer includes a plurality of aligned light guides, each light guide having an input end, a midsection and an output end. The light guide layers are physically stacked. The input ends and the output ends are aligned. Vertical misalignment is detected with an optical detection device. In response to the detection of vertical misalignment, at least one light guide layer is horizontally adjusted.

Abstract: A method of monitoring a density profile of impurities, the method including presetting a monitoring position of a thin layer coated on a substrate, the density profile of impurities being monitored from the monitoring position in a direction of thickness of the thin layer, moving an exposer for exposing a local area of the thin layer to the monitoring position, exposing the local area of the thin layer along the direction of thickness of the thin layer, forming a shape profile of the exposed local area of the thin layer, and monitoring the density profile of impurities by determining a density of impurities in accordance with the shape profile, and an apparatus therefor. The impurity density profile may be monitored without destroying a substrate on which a thin layer is coated, and an amount of impurities used for forming the thin layer may be monitored and controlled in real-time.

Abstract: The present invention is a method of surface preparation and imaging for integrated circuits. First, a substrate is selected and an opening is cut in the substrate of a sufficient size to fit an integrated circuit to be analyzed. A second substrate is then selected. An adhesive film is applied to the top surface of the first substrate, the adhesive film having adhesive on both sides and covering the opening on the first substrate. An integrated circuit is then inserted into the opening and attached to the bottom side of the adhesive film. Next, the first substrate and integrated circuit are bonded to the second substrate using the adhesive film. The bottom side of the first substrate and the integrated circuit are then thinned until the substrate wafer of the integrated circuit is completely removed. Finally, an analytical imaging technique is performed on the integrated circuit from the bottom side of the first substrate.

Abstract: A method of compensating sensor data and a method of evaluating an interlock of an interlock system, in which an allowable variation between sensors varying depending on a driving time for a set of equipment, an RF time, the number of wafers, etc. is minimized, thereby enhancing detection reliability of a defective wafer.

Abstract: An inspection method and apparatus of laser crystallized silicons in the low-temperature poly Si (LTPS) process. The crystalline quality is inspected by using a visible light source to irradiate the surface of the poly Si and examining the variations of the reflected light caused by the protrusion arrangement at the surface of the poly Si. This method can be adopted on the poly Si samples prepared by the line scanning of the excimer laser annealing (ELA) technology.

Abstract: The present invention provides a method for inspecting a connecting surface of a flip chip to solve problems that the grinding, polishing and chemical etching method is used for making a sample. The present invention utilizes ion beam etching technology for making and processing a sample of the flip chip (FC). The ion beam etching technology includes two modes: keeping the energy of ion beam and increasing the etching time; and keeping the etching time and increasing the ion beam energy. The ion beam etching technology can remove a deforming portion between the solder ball and the metal pad, which is connected thereto because of the grinding and polishing. Specially, it is easy to analyse a sample of a scanning electron microscope (SEM) which includes an intermetallic compound formed between the solder ball and the metal pad connected thereto.

Abstract: The optimization of an optical metrology model for use in measuring a wafer structure is evaluated. An optical metrology model having metrology model variables, which includes profile model parameters of a profile model, is developed. One or more goals for metrology model optimization are selected. One or more profile model parameters to be used in evaluating the one or more selected goals are selected. One or more metrology model variables to be set to fixed values are selected. One or more selected metrology model variables are set to fixed values. One or more termination criteria for the one or more selected goals are set. The optical metrology model is optimized using the fixed values for the one or more selected metrology model variables. Measurements for the one or more selected profile model parameters are obtained using the optimized optical metrology model. A determination is then made as to whether the one or more termination criteria are met by the obtained measurements.

Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.

Abstract: A processing apparatus for processing a microelectronic workpiece includes a metrology unit and a control, signal-connected to the metrology unit. The control can modify a process recipe or a process sequence of the processing apparatus based on a feed forward or a feed back signal from the metrology unit. A seed layer deposition tool, a process layer electrochemical deposition tool, and a chemical mechanical polishing tool, arranged for sequential processing of a workpiece, can be controlled as an integrated system using one or more metrology units. A metrology unit can be located at each tool to measure workpiece parameters. Each of the metrology units can be used as a feed forward control and/or a feed back control at each of the tools.

Abstract: A semiconductor processing device includes a processing section to process a semiconductor substrate in accordance with job information which is used to process the semiconductor substrate. An imaging section takes an image of a processed portion of the semiconductor substrate for each time of processing by the processing section. An image-processing section converts any one and another of the images to image data which are different from each other in data volume, and associates a result of processing from the processing section, the job information and the image data with each other in each processing. An input/output section outputs at least the result of processing and the image data.

Abstract: A test system and a related method to perform optical and electrical tests, to adjust the focus and to seal the lens of digital fixed-focus cameras have been achieved. Said test system is especially suited for miniature camera module to be built into consumer electronic devices as mobile phones, PDAs, etc. Said test system comprises three parts, a control system, an auto-focus head, and a XYZ robot. Said auto-focus head executes the adjustment of the focus, identifies hot pixels and black level, tests the saturation level, identifies cold pixels, tests dust particles and white, blue, red, and infrared color levels. As last step the auto-focus applies glue to fix the focused lens of the camera module. Said XYZ robot performs is moving the camera modules to be tested in XY direction and is approaching the lens system of the auto-focus head in Z direction. Said control system has interfaces to both, XYZ robot and auto-focus hand and is comprising interfaces and a frame grabber.

Abstract: A lidded semiconductor device has a first layer applied to the lid, which first layer is chosen of a material which fluoresces upon application of non-visible electromagnetic waves thereto, for example, ultraviolet light. A second layer is provided over the first layer. Openings extend through the second layer and further extend to a substantial depth into the first layer, for example, generally halfway into the first layer, to expose portions of the first layer.

Abstract: Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

Abstract: A method for obtaining confidence measure of a ball grid array (BGA) model having a plurality of balls in semiconductor surface mounted devices is provided. The method comprises the steps of extracting BGA images from a real surface mounted device, generating a BGA ball model and a BGA body model, generating a first confidence measure of the BGA ball model wherein the first confidence measure includes a first standard deviation of the BGA ball model and a first local image contrast of each BGA ball, and generating a second confidence measure of the BGA body model wherein the second confidence measure includes a second standard deviation of the BGA body model and a second local image contrast of the BGA body.

Abstract: A method of calculating a quantity of light by measuring, by using an adhering force measuring unit (71), the adhering force of an ultraviolet light-curable tape (11 or 21) relying upon the quantity of ultraviolet light with which the ultraviolet light-curable tape is irradiated from an ultraviolet light irradiation unit (61), and calculating, by using a calculation unit, the quantity of ultraviolet light corresponding to a predetermined adhering force, from the measured adhering force of the ultraviolet light-curable tape, and a device therefor. The predetermined adhering force may have been stored in advance in the storage unit or the predetermined adhering force may be determined in advance relying upon at least either one of the kind of the ultraviolet light-curable tape or the elapsed time of the ultraviolet light-curable tape.

Abstract: In fabricating a semiconductor laser producing light with a wavelength of 770 to 810 nm, impurities are introduced into an MQW active layer near a light emitting facet of the laser to form a disordered region constituting a window layer. Pump light is applied to the window layer to generate photoluminescence whose wavelength ? dpl (nm) is measured. A blue shift amount ? bl (nm) is defined as the difference between the wavelength ? apl (nm) 0f photoluminescence generated by application of pump light to the active layer on the one hand, and the wavelength ? dpl (nm) of photoluminescence from the window layer under pump light irradiation on the other hand. The blue shift amount ? bl is referenced during the fabrication process in order to predict catastrophic optical damage levels of semiconductor lasers.

Abstract: Methods and systems for preparing a substrate for analysis are provided. One method includes removing a portion of a copper structure on the substrate using an etch chemistry in combination with an electron beam. The etch chemistry is substantially inert with respect to the copper structure except in the presence of the electron beam. Other methods involve forming masking layers on a substrate that will protect the substrate during etching. For example, one method includes exposing a first portion of the substrate to an electron beam. A second portion of the substrate not exposed to the electron beam includes a copper structure. The method also includes exposing the substrate to a fluorine containing chemical. The fluorine containing chemical bonds to the first portion but not the second portion to form a fluorine containing layer on the first portion.

Abstract: A method for modeling samples includes the use of control points to define lines profiles and other geometric shapes. Each control point used within a model influences a shape within the model. Typically, the control points are used in a connect-the-dots fashion where a set of dots defines the outline or profile of a shape. The layers within the sample are typically modeled independently of the shape defined using the control points. The overall result is to minimize the number of parameters used to model shapes while maintaining the accuracy of the resulting scatterometry models.

Abstract: A method for manufacturing an LED device includes the steps of mounting an LED on a substrate, sealing the LED with a transparent resin including phosphor particles to form an LED device before being dyed, measuring chromaticity of light from the LED device before being dyed; and dyeing the sealing resin by a dye having a color for correcting the measured chromaticity to a desired color.

Abstract: A method of determining temperatures at localized regions of a substrate during processing of the substrate in a photolithography process includes the following steps: independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on the substrate with a light source, so that light is diffracted off the plurality of locations of the photoresist pattern; measuring the diffracted light from the plurality of locations to determine measured diffracted values associated with respective locations from the plurality of locations; and comparing the measured diffracted values against a library to determine a pre-illumination process temperature of the photoresist layer at the plurality of locations.

Abstract: The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.

Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

Abstract: A system and method thereof for experiment management. A storage device stores an experiment plan record, a merge constraint and an integration rule. A processing unit configured to acquire a first experiment plan from the experiment plan record, and a second experiment plan. The processing unit generates an integrated experiment plan by merging the first experiment plan and the second experiment plan according to the merge constraint and the integration rule, and stores the integrated experiment plan to the storage device.

Abstract: Disclosed are a method and apparatus for inspecting a wafer for electrical defects. A first electron beam is irradiated onto an area of the wafer including an inspection region to charge the area. A second electron beam is irradiated onto the inspection region to inspect the inspection region after focusing the second electron beam on the inspection region. A third electron beam is irradiated onto the area to discharge charges accumulated on the area. Therefore, the electrical defect of the wafer can be precisely detected with increased voltage contrasts for distinguishing the electrical defect. This method and apparatus have improved detection sensitivity and detection reliability over conventional methods.

Abstract: A method of manufacturing a waveguide type optical element wherein Zn is selectively diffused on a light absorption layer using an undoped InP layer. Since an impurity diffusion area is made on the light absorption layer under a ridge part, a depletion layer becomes thin in a thickness direction and an electric field can strongly be applied. Thereby, an extinction ratio characteristic of a device can be improved.

Abstract: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.

Abstract: Disclosed is a method and system for detecting abnormal plasma discharge that is useful in, for example, detecting plasma leakage in a reactive ion etching (RIE) chamber. The system includes electrical contacts connected to the chamber that provide an input signal to the chamber. This input signal can be generated by a radio frequency (RF) generator that is connected to the electrical contacts. A variable power controller connected to the RF generator gradually increases (ramps) the power of the input signal being supplied to the chamber.

Abstract: The invention relates to a method and apparatus for detecting defects in a semiconductor or silicon structure at room temperature, and in an efficient time, using photoluminescence. The invention employs the use of a high intensity beam of light preferably having a spot size between 0.1 mm–0.5 microns and a peak or average power density of 104–109 w/cm2 with a view to generating a high concentration of charge carriers, which charge characters detect defects in a semiconductor by interacting with same. These defects are visible by producing a photoluminescence image of the semiconductor. Several wavelengths may be selected to identify defects at a selective depth as well as confocal optics may be used.