Electrical Characteristic Sensed Patents (Class 438/17)
  • Patent number: 10411157
    Abstract: An optoelectronic component includes an optoelectronic semiconductor chip including first and second electrical contacts, a first leadframe section including a first chip contact pad and a first soldering contact pad situated opposite the first chip contact pad, and a second leadframe section including a second chip contact pad and a second soldering contact pad situated opposite the second chip contact pad, wherein the first electrical contact electrically conductively connects to the first chip contact pad and the second electrical contact electrically conductively connects to the second chip contact pad, the first and second leadframe sections are embedded into a housing such that at least parts of the first and second soldering contact pads are accessible at an underside, and a solder stop element is arranged at the underside of the housing, the solder stop element extending between the first soldering contact pad and the second soldering contact pad.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 10, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Christian Gatzhammer, Martin Brandl, Tobias Gebuhr
  • Patent number: 10411686
    Abstract: A delay cell may include: a first inverter coupled to an input terminal; a second inverter coupled between the first inverter and an output terminal; an additional inverter coupled in parallel to the first inverter; and a delay element suitable for selectively coupling the additional inverter to the input terminal under control of a control signal.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae-Heung Kim
  • Patent number: 10403468
    Abstract: A method of producing an implantation ion energy filter, suitable for processing a power semiconductor device. In one example, the method includes creating a preform having a first structure; providing an energy filter body material; and structuring the energy filter body material by using the preform, thereby establishing an energy filter body having a second structure.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Andre Brockmeier
  • Patent number: 10361089
    Abstract: A plasma processing method according to an exemplary embodiment includes a process of applying a first plasma processing to a substrate in a chamber, and a process of applying a second plasma processing to the substrate in the chamber. In the process of applying the first plasma processing, a plurality of first heaters in a chuck main body of an electrostatic chuck are driven, and a plurality of second heaters in the chuck main body are driven. In the process of applying the second plasma processing, the driving of at least the plurality of second heaters is stopped.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 23, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kengo Kaneko, Jun Hirose
  • Patent number: 10324569
    Abstract: A touch screen panel and a driving method thereof. The touch screen panel includes a touch pad unit including a plurality of receiver pads and a plurality of transmitter pads combined with the receiver pads, and a touch sensing unit for determining a touch position, based on changes in mutual capacitance between the receiver pads and the transmitter pads. The touch sensing unit determines maximum values for every column by scanning touch sensing signals in the column direction of the touch pad unit, decides whether rows having maximum values for every column are the same, when the rows having the maximum values for every column are not the same, determines a greatest value by comparing all values of the scanned touch sensing signals, and determines touch coordinates through a combination of transmitter and receiver pads corresponding to the position at which the greatest value exists.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun Ho Kim, Ja Seung Ku
  • Patent number: 10090300
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeff J. Xu, Chih-Hao Chang
  • Patent number: 10090179
    Abstract: In an embodiment, the present invention discloses cleaned storage processes and systems for high level cleanliness articles, such as extreme ultraviolet (EUV) reticle carriers. A decontamination chamber can be used to clean the stored workpieces. A purge gas system can be used to prevent contamination of the articles stored within the workpieces. A robot can be used to detect the condition of the storage compartment before delivering the workpiece. A monitor device can be used to monitor the conditions of the stocker.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 2, 2018
    Assignee: Brooks Automation, Inc.
    Inventor: Lutz Rebstock
  • Patent number: 10048389
    Abstract: A centroid contact radiation detector system/method providing for low capacitance and noise insensitivity is disclosed. The system incorporates a P-type/N-type bulk germanium volume (PGEV/NGEV) having an internal well cavity void (IWCV). The external NGEV surfaces incorporate an N+/P+ electrode and the surface of the IWCV incorporates a centrally located P+/N+ contact (CPPC). The IWCV surface is constructed and the CPPC is positioned within the IWCV so as to provide uniform symmetric field distribution within the PGEV/NGEV and improved noise immunity. The CPPC may be formed using point, reduced-area, medium-area, large-area, hemispherical, semi-hemispherical, and cylindrical annulus contact constructions. The PGEV/NGEV may be constructed using cylindrical, regular polyhedral, or spherical forms.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: August 14, 2018
    Assignee: MIRION TECHNOLOGIES (CANBERRA), INC.
    Inventors: James Francis Colaresi, Kenneth Michael Yocum, Aderemi Sikiru Adekola
  • Patent number: 10020226
    Abstract: In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 10, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 9941207
    Abstract: A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 10, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9890037
    Abstract: For a small sensor produced through a MEMS process, when an electrode pad, wiring, or a shield layer is formed in a final step, it is difficult to nondestructively investigate whether a structure for sensing a physical quantity has been processed satisfactorily. In the present invention, in a physical quantity sensor formed from an MEMS structure, in a structure in which a surface electrode having through wiring is formed on the surface of an electrode substrate and the periphery thereof is insulated, forming a shield layer comprising a metallic material on the surface of the electrode substrate in a planar view and providing a space for internal observation inside the shield layer makes it possible to check for internal defects.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 13, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Masatoshi Kanamaru, Masahide Hayashi, Masashi Yura, Heewon Jeong
  • Patent number: 9865583
    Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 9, 2018
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9847264
    Abstract: Improved methods for manufacturing semiconductor product wafer with the additional use of non-product masks are described. According to certain aspects of the invention, an evaluation wafer is first manufactured by utilizing at least one non-product mask to process one or more layer(s) on the evaluation wafer, and subsequently utilizing at least one unaltered product mask to process an evaluation-region-of-interest on the evaluation wafer. The evaluation-region-of-interest is evaluated by measuring the state of one or more feature(s) in the evaluation-region-of-interest using voltage contrast inspection (VCi). The measurements are then used to identify failures in the evaluation-region-of-interest.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 19, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Yih-Yuh (Kelvin) Doong, Sheng-Che Lin
  • Patent number: 9793361
    Abstract: A thin film transistor, an array substrate and a display device are disclosed, the thin film transistor comprises a gate electrode, an active layer located on the gate electrode, and a source electrode and a drain electrode respectively located at opposite sides of the active layer and both partially overlapped with the active layer; the active layer includes at least one first structure part and at least one second structure part, a material for the first structure part is semiconductor, and a material for the second structure part is predetermined conductor, and the predetermined conductor has better conductivity than the conductivity of the conducted semiconductor, and in response to that a turn-on voltage is applied to the gate electrode, a conductive passage located between the source electrode and the drain electrode includes the first structure part and the second structure part.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 17, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Qinghui Zeng, Zhuo Zhang, Seiji Fujino
  • Patent number: 9786591
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Patent number: 9704750
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes providing a wafer stack including a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side, the second side being attached to the carrier wafer, defining device regions of the wafer stack, partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Wolfgang Lehnert, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 9613874
    Abstract: Methods for evaluating semiconductor device structures are provided. In one example, a method includes forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure. The lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side. The second side is milled to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side. The support layer is removed from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness. The target analysis area of the reduced thickness lamellar sample portion is evaluated.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jie Zhu, Binghai Liu, Eddie Er, Si Ping Zhao, Jeffrey Lam
  • Patent number: 9484892
    Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Reza Kakoee, Shih-Hsin Jason Hu, Min Chen, Jasmin Smaila Ibrahimovic, Carlos Auyon, Sorin Adrian Dobre, Navid Toosizadeh, Nan Chen, Mohamed Waleed Allam
  • Patent number: 9478237
    Abstract: A data storage device may be tested during or after manufacture by a testing device that may have at least a work piece with at least one contact pad concurrently contacting bottom and sidewall surfaces of a probe tip with a centering feature of the at least one contact pad.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 25, 2016
    Assignee: Seagate Technology LLC
    Inventors: Leping Li, Jeffrey Robert O'Konski, Saravuth Keo, Pramit P. Parikh
  • Patent number: 9443855
    Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: September 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thamarai Selvi Devarajan, Sanjay C. Mehta, Eric R. Miller, Soon-Cheon Seo
  • Patent number: 9417264
    Abstract: Provided are a current application device capable of improving the electrical contact between projections of a contact section and a surface electrode when applying a test current to a semiconductor element, and a method of manufacturing a semiconductor element properly tested by using the current application device. The current application device includes a contact section that has a plurality of projections, which are brought into contact with a surface electrode of a semiconductor element to apply a test current, and a pressing section that presses the contact section against the semiconductor element such that the projections penetrate a film to come in contact with the surface electrode. The contact section has a plurality of the projections on a plane that has been formed in a curved shape, and the curved-shaped plane is deformed into a planar shape by being pressed by the pressing section.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: August 16, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Shigeto Akahori, Hitoshi Saito, Hiroyuki Yamagishi, Shinyu Hirayama, Satoshi Hasegawa, Yoko Yamaji, Koichiro Sato, Machie Saitou
  • Patent number: 9383608
    Abstract: An array substrate of an LCD includes a substrate, a first wiring layer, a semiconductor film, an insulating layer, a second wiring layer, a passivation layer, a conductive film, and a spacer. The first wiring layer is patterned to a gate line, a gate electrode, and a first laminating layer. The semiconductor film is patterned to a channel layer and a second laminating layer. The second wiring layer is patterned to a source line, a source electrode, a drain electrode, and a third laminating layer. The conductive film is patterned to a pixel electrode and a fourth laminating layer. The spacer is a laminating structure at least includes the first, second, third, fourth laminating layers. A portion of insulating layer overlaps with the first laminating layer, and a portion of passivation layer overlaps with the third laminating layer.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 5, 2016
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Ming-Tsung Wang, Kuo-Chieh Chi, Qi Xu, Dan Chen
  • Patent number: 9298950
    Abstract: Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel Jacob Fainstein, Chandrasekharan Kothandaraman
  • Patent number: 9279849
    Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Terence L. Kane, John M. Walsh
  • Patent number: 9269639
    Abstract: The present invention provides a method of detecting and measuring the alignment shift of the contacts relative to the gate structures. The method comprises: designing a test model array having different test model regions on the substrate; forming second conductivity type doped well regions, gate structures, and first conductivity type doped active regions in each of the test model regions; forming contacts in each of the test model region; scanning the test model array by an electron-beam inspector to obtain light-dark patterns of the contacts; and detecting and measuring the alignment shift of the contacts relative to the gate structures according to the light-dark patterns of the contacts and the critical dimensions of the transistors in the test model regions.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: February 23, 2016
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Rongwei Fan, Feijue Liu, Yin Long, Qiliang Ni, Hunglin Chen
  • Patent number: 9269632
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 9269622
    Abstract: A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: February 23, 2016
    Assignee: DECA Technologies Inc.
    Inventors: Christopher M. Scanlan, Timothy L. Olson
  • Patent number: 9263525
    Abstract: The present invention includes an n+ type substrate, a drift epitaxial layer formed on the n+ type substrate and having a lower concentration of impurity than the n+ type substrate, a Schottky electrode formed on the drift epitaxial layer, and a PI formed as an insulating film by covering at least an end of the Schottky electrode and an end and a side surface of the drift epitaxial layer.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 16, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshinori Matsuno
  • Patent number: 9240384
    Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: January 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Qing Zhang, Haijing Cao
  • Patent number: 9202684
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 1, 2015
    Assignee: UChicago Argonne, LLC
    Inventors: Anirudha V. Sumant, Alexander Balandin
  • Patent number: 9190392
    Abstract: A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 17, 2015
    Assignee: Sandia Corporation
    Inventors: Subhash L. Shinde, John Teifel, Richard S. Flores, Robert L. Jarecki, Jr., Todd Bauer
  • Patent number: 9165831
    Abstract: A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Charles F. Musante, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 9142505
    Abstract: Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). A barrier layer comprising a bottom part and a side part is formed within an opening for a metal contact, wherein the bottom part comprises a graphene material, the side part comprises an amorphous carbon material and covers a sidewall of the opening, and the bottom part and the side part are formed at a same time. A capping layer comprising a first part and a second part is formed on a dielectric layer and a metal contact, wherein the first part comprises a graphene material, the second part of the capping layer comprises an amorphous carbon material on the dielectric layer, and the first part and the second part are formed at a same time.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Hsiang-Huan Lee, Ming Han Lee, Ching-Fu Yeh, Pei-Yin Liou
  • Patent number: 9136188
    Abstract: Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: September 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Shuhei Yoshitomi
  • Patent number: 9122829
    Abstract: A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 1, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
  • Patent number: 9111895
    Abstract: An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: August 18, 2015
    Assignee: STMicroelectonics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 9099517
    Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are described. The SiC BJT comprises a collector region, a base region and an emitter region disposed as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically disposed between the first portion and the emitter region in the stack.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: August 4, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Patent number: 9099488
    Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. Surface treatments can be inserted at three possible steps during the formation of the MOSCAP structures. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 4, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Dipankar Pramanik
  • Patent number: 9090014
    Abstract: Systems for controlling velocity of a contact line and height profile between a template and a substrate during imprinting of polymerizable material are described.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: July 28, 2015
    Assignees: Canon Nanotechnologies, Inc., Molecular Imprints, Inc.
    Inventors: Xiaoming Lu, Philip D. Schumaker
  • Patent number: 9082660
    Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: July 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ji Feng, Hai-Long Gu, Ying-Tu Chen
  • Patent number: 9047949
    Abstract: A reversible resistance-switching metal-insulator-metal (MIM) stack is provided which can be set to a low resistance state with a first polarity signal and reset to a higher resistance state with a second polarity signal. The first polarity signal is opposite in polarity than the second polarity signal. In one approach, the MIM stack includes a carbon-based reversible resistivity switching material such as a carbon nanotube material. The MIM stack can further include one or more additional reversible resistivity switching materials such as metal oxide above and/or below the carbon-based reversible resistivity switching material. In another approach, a metal oxide layer is between separate layers of carbon-based reversible resistivity switching material.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: June 2, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Jingyan Zhang, Utthaman Thirunavukkarasu, April D Schricker
  • Publication number: 20150147830
    Abstract: A method comprising processing a substrate exposed to a plasma in a processing chamber, obtaining a metric indicative of a parameter of the plasma during the processing of the substrate, and determining a defect in the substrate by comparing the metric to a predefined criteria.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventors: Ilias ILIOPOULOS, Shuo NA, Kelby YANCY
  • Patent number: 9040317
    Abstract: A method includes performing a patterning step on a layer using a process gas. When the patterning step is performed, a signal strength is monitored, wherein the signal strength is from an emission spectrum of a compound generated from the patterning step. The compound includes an element in the patterned layer. At a time the signal strength is reduced to a pre-determined threshold value, the patterning step is stopped.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Szu-Hung Yang, Chiung Wen Hsu
  • Patent number: 9041209
    Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Douglas M. Reber, Lawrence N. Herr
  • Publication number: 20150140696
    Abstract: One or more small spot showerhead apparatus are used to provide dopant exposure and/or to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner. Anneal processes where the area of the process can be controlled such as laser annealing or site-isolated rapid thermal processing (RTP) can be used to vary the annealing conditions in a combinatorial manner.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: Intermolecular, Inc.
    Inventor: Khaled Ahmed
  • Patent number: 9034668
    Abstract: Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 19, 2015
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Massimo Mongillo, Silvano De Franceschi, Panayotis Spathis
  • Patent number: 9034666
    Abstract: Some embodiments provide methods, process, systems and apparatus for use in testing multi-axis Micro Electro Mechanical Systems (MEMS) devices. In some embodiments, methods of testing are provided, comprising: selecting, according to a test specification and a test program, at least a first MEMS device on a substrate comprising a plurality of MEMS formed relative to the substrate and applying one or more electrical probes to the first MEMS device; providing power to the first MEMS device through the one or more electrical probes; measuring output signals of the first MEMS device; applying a force to the first MEMS device using a force actuator; measuring a set of output signals of the first MEMS device based on the applied force; and processing test data and generating output test results according to the test specification and test program.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 19, 2015
    Inventors: Vladimir Vaganov, Nickolai Belov
  • Patent number: 9035306
    Abstract: In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Robert Mulfinger, Vassilios Papageorgiou
  • Publication number: 20150132865
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Publication number: 20150132869
    Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventors: Luke G. England, Paul A. Silvestri, Michel Koopmans