Utilizing Integral Test Element Patents (Class 438/18)
  • Patent number: 12343189
    Abstract: An X-ray inspection apparatus includes: a transport unit configured to transport an article; an X-ray source configured to irradiate the article with X-rays; an X-ray detection unit configured to detect the X-rays using a photon counting method and to classify photon energy of the detected X-rays into two or more energy regions on the basis of a threshold value; a threshold value setting unit configured to set the threshold value; an X-ray image generation unit configured to generate two or more X-ray transmission images corresponding to the two or more energy regions on the basis of a detection result of the X-rays; and an inspection unit configured to inspect the article on the basis of the X-rays. The threshold value setting unit is configured to set the threshold value on the basis of gradations of the two or more X-ray transmission images.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: July 1, 2025
    Assignee: ISHIDA CO., LTD.
    Inventors: Ken Iwakawa, Futoshi Yurugi, Keisuke Yoshida
  • Patent number: 12313709
    Abstract: A magnetoresistive sensor is provided. The magnetoresistive sensor comprises a substrate having a layer structure thereon. The layer structure comprises a lower layer, and an upper layer. The lower layer is provided on the substrate, wherein the lower layer comprises one or more graphene layers which extend across the lower layer. The upper layer is provided on the lower layer and formed of a dielectric material. The lower and upper layers of the layer structure share one or more continuous edge surfaces.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: May 27, 2025
    Assignee: Paragraf Limited
    Inventor: Hugh Frederick John Glass
  • Patent number: 12284894
    Abstract: A display device includes: a first conductive layer including a signal line, which includes a pad contact part and a line part having a smaller width than the pad contact part along a first direction and extending from the pad contact part in a second direction that intersects the first direction, and a first non-contact pattern, which is spaced apart from the pad contact part, on a first side along the first direction; an insulating layer on the first conductive layer and including a contact hole that partially exposes the first conductive layer; and a second conductive layer on the insulating layer and including a first pad electrode, which is electrically connected to the first conductive layer through the contact hole, wherein the first pad electrode overlaps with the pad contact part and the first non-contact pattern.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 22, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chan Jae Park, Sang Duk Lee, Sun Ok Oh, Ki Kyung Youk, Hyun A Lee, Soo Yeon Han
  • Patent number: 12270852
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.
    Type: Grant
    Filed: May 23, 2024
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Patent number: 12265116
    Abstract: A device and a method for detecting LEDs bonded to a display substrate are provided. The device includes a power supply assembly, a pressure fixture and a detector. The power supply assembly is used for providing electrical signals to the LEDs. The pressure fixture is used for applying a force to the power supply assembly, so that the power supply assembly directly contacts and electrically connects to at least one of the LEDs. The detector is on a side of the pressure fixture away from the power supply assembly and used for detecting whether each of the LEDs emits light according to a normal standard.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: April 1, 2025
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventor: Kuang-Hua Liu
  • Patent number: 12255112
    Abstract: A test key configured to measure resistance of a through semiconductor via in a semiconductor substrate is provided. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tse-Pan Yang, Wei Lee, Kuo-Pei Lu, Jen-Yuan Chang
  • Patent number: 12228427
    Abstract: A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: February 18, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Josef Muenz
  • Patent number: 12218076
    Abstract: A semiconductor design that uses high refractive index material between low refractive index material. This structure may act as an optical waveguide.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 4, 2025
    Assignee: Meta Platforms, Inc.
    Inventors: Pradip Sairam Pichumani, Sandeep Rekhi
  • Patent number: 12218016
    Abstract: A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: February 4, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chen Huang, Meng-Feng Tsai, Yuejiao Shu
  • Patent number: 12203973
    Abstract: A circuit includes one or more sensors formed on one or more dies, each sensor detecting one or more wafer characterization data; a stress generator on the die to control the one or more sensors to place the one or more sensors under stress during wafer manufacturing or operation; and an interface coupled to the one or more sensors to communicate the wafer characterization data to a processor or a tester.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: January 21, 2025
    Assignee: Tartan Silicon Systems, Inc.
    Inventor: Alan Paul Aronoff
  • Patent number: 12158496
    Abstract: A chip-on-film test board on which a chip-on-film is mounted according to an embodiment of the present disclosure includes a main board in which a test circuit configured to output a test pattern signal is formed, and a chip-on-film fixing part that fixes a position of the chip-on-film.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: December 3, 2024
    Assignee: LX SEMICON CO., LTD.
    Inventors: Min Suk Kim, Seung Il Hong, Jung Ho Kim
  • Patent number: 12131957
    Abstract: Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence. Scanning probe microscopy may be used to provide conductance data. Conductance data may relate to device characteristics that are normally not available until the conclusion of device manufacturing. The substrates may be selectively treated to ameliorate a condition revealed by the data. Some substrates may be selectively discarded based on the data to avoid the expense of further processing. A process maintenance operation may be selectively carried out based on the data.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang
  • Patent number: 12133452
    Abstract: A display device is disclosed. The display device includes a substrate including a first area, a second area, and a first bending area located between the first and second areas. The first bending area is bent about a first bending axis extending in a first direction. The display device also includes a first inorganic insulating layer arranged over the substrate and having a first opening or a first groove at least in the first bending area, an organic material layer filling at least a part of the first opening or the first groove, and a first conductive layer extending from the first area to the second area across the first bending area and located over the organic material layer.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoonsun Choi, Wonsuk Choi, Cheolsu Kim, Sangjo Lee
  • Patent number: 12107021
    Abstract: Embodiments of the present application provide a process monitoring method and a process monitoring system. The process monitoring method includes: acquiring a semiconductor structure on which an etch process is performed in an etch chamber, and forming a corresponding test structure based on the semiconductor structure; acquiring first theoretical mass of the test structure after the etch process is theoretically performed; placing the test structure in the etch chamber to actually perform the etch process, and acquiring first residual mass of the test structure after the etch process is actually performed; and determining, based on the first theoretical mass and the first residual mass, whether an etch state of the etch process performed in the etch chamber is normal.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: October 1, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chunyang Wang, Xinran Liu, Changli Zhu
  • Patent number: 12078607
    Abstract: A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Yu Chang, Ken-Ichi Goto, Yen-Chieh Huang, Min-Kun Dai, Han-Ting Tsai, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12066484
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Patent number: 12062533
    Abstract: The invention relates to a method of producing a substrate. The method comprises providing a workpiece having a first surface and a second surface opposite the first surface, and providing a carrier having a first surface and a second surface opposite the first surface. The method further comprises attaching the carrier to the workpiece, wherein at least a peripheral portion of the first surface of the carrier is attached to the first surface of the workpiece, and forming a modified layer inside the workpiece. Moreover, the method comprises dividing the workpiece along the modified layer, thereby obtaining the substrate, wherein the substrate has the carrier attached thereto, and removing carrier material from the side of the second surface of the carrier in a central portion of the carrier so as to form a recess in the carrier. The invention further relates to a substrate producing system for performing this method.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 13, 2024
    Assignee: DISCO CORPORATION
    Inventor: Karl Heinz Priewasser
  • Patent number: 12033902
    Abstract: A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chien Hsieh, Ting-Hao Chang, Chun-Hao Lin, Yun-Wei Cheng, Kuo-Cheng Lee
  • Patent number: 12025655
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Patent number: 12009177
    Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 11, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Ya-Chin King, Chrong-Jung Lin, Burn-Jeng Lin, Chien-Ping Wang, Shao-Hua Wang, Chun-Lin Chang, Li-Jui Chen
  • Patent number: 11984369
    Abstract: A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11974391
    Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongyoon Seo, Hwanwook Park, Dohyung Kim, Bora Kim, Seungyeong Lee, Wonseop Lee, Yunho Lee, Yejin Cho
  • Patent number: 11967528
    Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II, Mengzhi Pang
  • Patent number: 11921131
    Abstract: The present disclosure provides a method for manufacturing a measurement probe, the method comprising cutting a carrier substrate to form a probe contour, the probe contour comprising at least one probe tip and a probe body, and metallizing the surface of the at least one probe tip of the probe contour. Further, the present disclosure provides a respective measurement probe.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: March 5, 2024
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Alexander Kunze, Alexander Stuka
  • Patent number: 11908722
    Abstract: A teaching substrate is loaded into a load port of an equipment front-end module (EFEM) of a fabrication or inspection tool. The EFEM includes a substrate-handling robot. The teaching substrate includes a plurality of sensors and one or more wireless transceivers. The tool includes a plurality of stations. With the teaching substrate in the EFEM, the substrate-handling robot moves along an initial route and sensor data are wirelessly received from the teaching substrate. Based at least in part on the sensor data, a modified route distinct from the initial route is determined. The substrate-handling robot moves along the modified route, handling the teaching substrate. Based at least in part on the sensor data, positions of the plurality of stations are determined.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 20, 2024
    Assignee: KLA Corporation
    Inventors: Avner Safrani, Shai Mark, Amir Aizen, Maor Arbit
  • Patent number: 11798624
    Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a plurality of memory blocks each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit for performing a general operation including a program operation, a read operation, and an erase operation on the plurality of memory blocks; and a control logic for controlling the peripheral circuit to operate in a heating mode in which the peripheral circuit applies heat to the plurality of memory blocks.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Kyung Min Kim, Hae Chang Yang
  • Patent number: 11785814
    Abstract: Disclosed are a display panel and a display device. The display panel includes: at least one group of gate driving signal lines, the gate driving signal lines starting from the driving chip bonding area and going around the display area after passing through the bending area; and at least two first driving voltage lines, the at least two first driving voltage lines respectively starting from the flexible printed circuit bonding area, going through the bending area after passing through two sides of the driving chip bonding area, and extending to be close to the display area, and the at least two first driving voltage lines are respectively at two sides of the at least one group of gate driving signal lines.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 10, 2023
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yi Qu, Hao Zhang, Linhong Han, Meng Zhang, Jie Dai, Yang Zhou, Yi Zhang, Chang Luo, Shun Zhang
  • Patent number: 11776973
    Abstract: A method of manufacturing a display device, the method including providing a substrate, forming a first electrode, a second electrode spaced from the first electrode and in a same plane as the first electrode, a first alignment line connected to the first electrode, and a second alignment line connected to the second electrode on the substrate, self-aligning the plurality of light emitting elements by providing a solution containing a plurality of light emitting elements on the substrate, removing the first alignment line and the second alignment line from the substrate on which the plurality of light emitting elements are self-aligned, forming a first contact electrode electrically connecting one end of each light emitting element to the first electrode, and forming a second contact electrode electrically connecting an other end of each light emitting element to the second electrode.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 3, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Joon Kim, Kyung Bae Kim, Kyung Hoon Chung, Mee Hye Jung
  • Patent number: 11764116
    Abstract: A method for detecting a physical short-circuit defect between the first metal layer and a gate below. A first detection structure and a second detection structure are arranged in parallel in a detection region or a dicing channel region on a wafer, each detection structure comprises a P-type active detection, a detection gate structure, a contact hole in the P-type active detection, gate contact holes at two ends of the detection gate structure, a metal wire connected to the contact hole in the P-type active detection, and a metal wire connected to the gate contact hole. The detection gate structure of the first detection structure and the metal wire above it at least partially overlap. However, there is no projective overlap region between the detection gate structure of the second detection structure and the metal wire—above it.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 19, 2023
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventor: Shuhua Lei
  • Patent number: 11754621
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Patent number: 11735549
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang
  • Patent number: 11730044
    Abstract: A display cell includes a signal line electrically connected to a pixel arranged in a display area, a signal pad unit disposed in a peripheral area adjacent to the display area, and including a signal pad electrically connected to the signal line, an inspection pad unit disposed in a turn-on inspection area, and including an inspection pad electrically connected to the signal pad, where the inspection pad is configured to receive a turn-on inspection signal, and a power supply voltage line configured to apply a power supply voltage to the pixel, extending from the inspection pad unit to the peripheral area, and divided into a plurality of sublines by at least one slit pattern in a cut-off area between the peripheral area and the turn-on inspection area.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyungjun Lim, Dong-Yoon So, Kyung Min Park
  • Patent number: 11688701
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Yi-Feng Chang
  • Patent number: 11670548
    Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 6, 2023
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II, Mengzhi Pang
  • Patent number: 11630149
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Patent number: 11585847
    Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 21, 2023
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Pedro Jr Santos Peralta, David Gani
  • Patent number: 11574079
    Abstract: A method for provisioning an electronic device includes providing a semiconductor wafer on which multiple integrated circuit (IC) chips have been fabricated. Each chip includes a secure memory and programmable logic, which is configured to store at least two keys in the secure memory and to compute digital signatures over data using the at least two keys. A respective first key is provisioned into the secure memory of each of the chips via electrical probes applied to contact pads on the semiconductor wafer. After dicing of the wafer, a respective second key is provisioned into the secure memory of each of the chips via contact pins of the chips. A respective provisioning report is received from each of the chips with a digital signature computed by the logic using both of the respective first and second keys. The provisioning is verified based on the digital signature.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: February 7, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Dan Morav, Ziv Hershman, Oren Tanami
  • Patent number: 11532524
    Abstract: A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wen Liu, Hsien-Wei Chen
  • Patent number: 11480543
    Abstract: A semiconductor sensor-based near-patient diagnostic system and related methods.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: October 25, 2022
    Assignee: FemtoDx, Inc.
    Inventors: Pritiraj Mohanty, Shyamsunder Erramilli
  • Patent number: 11448692
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWANN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Patent number: 11443825
    Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: September 13, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Feng Ho, Kuo-Min Liao, Yu-Pei Lin
  • Patent number: 11366156
    Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 21, 2022
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Pedro Jr Santos Peralta, David Gani
  • Patent number: 11367790
    Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 21, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anupam Dutta, Balaji Swaminathan
  • Patent number: 11320478
    Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
  • Patent number: 11081458
    Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: James M. Derderian
  • Patent number: 11011478
    Abstract: A semiconductor device includes an integrated circuit, an outer seal ring, and an inner seal ring. The outer seal ring forms a first closed loop surrounding the integrated circuit. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring has a first seal portion surrounding the integrated circuit and a second seal portion spaced apart from the first seal portion, a first connector interconnecting the first seal portion and the second seal portion, and a second connector spaced apart from the first connector and interconnecting the first seal portion and the second seal portion. The first seal portion, the second seal portion, the first connector, and the second connector form a second closed loop.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
  • Patent number: 10976362
    Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 13, 2021
    Assignee: AEHR TEST SYSTEMS
    Inventors: Steven C. Steps, Scott E. Lindsey, Kenneth W. Deboe, Donald P. Richmond, II, Alberto Calderon
  • Patent number: 10900953
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10885244
    Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Wook Hwang, Jong-Hyun Lee, Min-Soo Kang
  • Patent number: 10831978
    Abstract: A method of making an integrated circuit including identifying a first wire at a first location in an array of wires next to an empty location in a layout of the integrated circuit, adjusting a width of the first wire at the first location, and calculating a performance of a widened wire with regard to a first parameter. The method also includes comparing the calculated performance of the widened wire to a performance threshold of the first parameter, adjusting a degree of width adjustment of the widened wire according to a comparison result, and comparing the calculated performance of the width-adjusted widened wire to the performance threshold of the first parameter.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Chih Ou, Wen-Hao Chen