Abstract: A chip-on-film test board on which a chip-on-film is mounted according to an embodiment of the present disclosure includes a main board in which a test circuit configured to output a test pattern signal is formed, and a chip-on-film fixing part that fixes a position of the chip-on-film.

Abstract: A display device is disclosed. The display device includes a substrate including a first area, a second area, and a first bending area located between the first and second areas. The first bending area is bent about a first bending axis extending in a first direction. The display device also includes a first inorganic insulating layer arranged over the substrate and having a first opening or a first groove at least in the first bending area, an organic material layer filling at least a part of the first opening or the first groove, and a first conductive layer extending from the first area to the second area across the first bending area and located over the organic material layer.

Abstract: Costs may be avoided and yields improved by applying scanning probe microscopy to substrates in the midst of an integrated circuit fabrication process sequence. Scanning probe microscopy may be used to provide conductance data. Conductance data may relate to device characteristics that are normally not available until the conclusion of device manufacturing. The substrates may be selectively treated to ameliorate a condition revealed by the data. Some substrates may be selectively discarded based on the data to avoid the expense of further processing. A process maintenance operation may be selectively carried out based on the data.

Abstract: Embodiments of the present application provide a process monitoring method and a process monitoring system. The process monitoring method includes: acquiring a semiconductor structure on which an etch process is performed in an etch chamber, and forming a corresponding test structure based on the semiconductor structure; acquiring first theoretical mass of the test structure after the etch process is theoretically performed; placing the test structure in the etch chamber to actually perform the etch process, and acquiring first residual mass of the test structure after the etch process is actually performed; and determining, based on the first theoretical mass and the first residual mass, whether an etch state of the etch process performed in the etch chamber is normal.

Abstract: A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

Abstract: The invention relates to a method of producing a substrate. The method comprises providing a workpiece having a first surface and a second surface opposite the first surface, and providing a carrier having a first surface and a second surface opposite the first surface. The method further comprises attaching the carrier to the workpiece, wherein at least a peripheral portion of the first surface of the carrier is attached to the first surface of the workpiece, and forming a modified layer inside the workpiece. Moreover, the method comprises dividing the workpiece along the modified layer, thereby obtaining the substrate, wherein the substrate has the carrier attached thereto, and removing carrier material from the side of the second surface of the carrier in a central portion of the carrier so as to form a recess in the carrier. The invention further relates to a substrate producing system for performing this method.

Abstract: A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.

Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Abstract: A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor.

Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Abstract: The present disclosure provides a method for manufacturing a measurement probe, the method comprising cutting a carrier substrate to form a probe contour, the probe contour comprising at least one probe tip and a probe body, and metallizing the surface of the at least one probe tip of the probe contour. Further, the present disclosure provides a respective measurement probe.

Abstract: A teaching substrate is loaded into a load port of an equipment front-end module (EFEM) of a fabrication or inspection tool. The EFEM includes a substrate-handling robot. The teaching substrate includes a plurality of sensors and one or more wireless transceivers. The tool includes a plurality of stations. With the teaching substrate in the EFEM, the substrate-handling robot moves along an initial route and sensor data are wirelessly received from the teaching substrate. Based at least in part on the sensor data, a modified route distinct from the initial route is determined. The substrate-handling robot moves along the modified route, handling the teaching substrate. Based at least in part on the sensor data, positions of the plurality of stations are determined.

Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a plurality of memory blocks each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit for performing a general operation including a program operation, a read operation, and an erase operation on the plurality of memory blocks; and a control logic for controlling the peripheral circuit to operate in a heating mode in which the peripheral circuit applies heat to the plurality of memory blocks.

Abstract: Disclosed are a display panel and a display device. The display panel includes: at least one group of gate driving signal lines, the gate driving signal lines starting from the driving chip bonding area and going around the display area after passing through the bending area; and at least two first driving voltage lines, the at least two first driving voltage lines respectively starting from the flexible printed circuit bonding area, going through the bending area after passing through two sides of the driving chip bonding area, and extending to be close to the display area, and the at least two first driving voltage lines are respectively at two sides of the at least one group of gate driving signal lines.

Abstract: A method of manufacturing a display device, the method including providing a substrate, forming a first electrode, a second electrode spaced from the first electrode and in a same plane as the first electrode, a first alignment line connected to the first electrode, and a second alignment line connected to the second electrode on the substrate, self-aligning the plurality of light emitting elements by providing a solution containing a plurality of light emitting elements on the substrate, removing the first alignment line and the second alignment line from the substrate on which the plurality of light emitting elements are self-aligned, forming a first contact electrode electrically connecting one end of each light emitting element to the first electrode, and forming a second contact electrode electrically connecting an other end of each light emitting element to the second electrode.

Abstract: A method for detecting a physical short-circuit defect between the first metal layer and a gate below. A first detection structure and a second detection structure are arranged in parallel in a detection region or a dicing channel region on a wafer, each detection structure comprises a P-type active detection, a detection gate structure, a contact hole in the P-type active detection, gate contact holes at two ends of the detection gate structure, a metal wire connected to the contact hole in the P-type active detection, and a metal wire connected to the gate contact hole. The detection gate structure of the first detection structure and the metal wire above it at least partially overlap. However, there is no projective overlap region between the detection gate structure of the second detection structure and the metal wire—above it.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

Abstract: A display cell includes a signal line electrically connected to a pixel arranged in a display area, a signal pad unit disposed in a peripheral area adjacent to the display area, and including a signal pad electrically connected to the signal line, an inspection pad unit disposed in a turn-on inspection area, and including an inspection pad electrically connected to the signal pad, where the inspection pad is configured to receive a turn-on inspection signal, and a power supply voltage line configured to apply a power supply voltage to the pixel, extending from the inspection pad unit to the peripheral area, and divided into a plurality of sublines by at least one slit pattern in a cut-off area between the peripheral area and the turn-on inspection area.

Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.

Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

Abstract: A method for provisioning an electronic device includes providing a semiconductor wafer on which multiple integrated circuit (IC) chips have been fabricated. Each chip includes a secure memory and programmable logic, which is configured to store at least two keys in the secure memory and to compute digital signatures over data using the at least two keys. A respective first key is provisioned into the secure memory of each of the chips via electrical probes applied to contact pads on the semiconductor wafer. After dicing of the wafer, a respective second key is provisioned into the secure memory of each of the chips via contact pins of the chips. A respective provisioning report is received from each of the chips with a digital signature computed by the logic using both of the respective first and second keys. The provisioning is verified based on the digital signature.

Abstract: A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.

Abstract: A semiconductor sensor-based near-patient diagnostic system and related methods.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

Abstract: Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.

Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.

Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

Abstract: In a method of testing a semiconductor wafer, a probe tip contacts a pad in a scribe line space between facing sides of first and second dies. The probe tip is electrically coupled to an automated test equipment (ATE). The second die is spaced apart from the first die. The scribe line space includes an interconnect extending along at least an entire length of the facing sides of the first and second dies. The pad is electrically coupled through the interconnect to at least one of the first or second dies. With the ATE, circuitry is tested in at least one of the first or second dies. The pad is electrically coupled through the interconnect to the circuitry.

Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

Abstract: A semiconductor device includes an integrated circuit, an outer seal ring, and an inner seal ring. The outer seal ring forms a first closed loop surrounding the integrated circuit. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring has a first seal portion surrounding the integrated circuit and a second seal portion spaced apart from the first seal portion, a first connector interconnecting the first seal portion and the second seal portion, and a second connector spaced apart from the first connector and interconnecting the first seal portion and the second seal portion. The first seal portion, the second seal portion, the first connector, and the second connector form a second closed loop.

Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.

Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

Abstract: A method of making an integrated circuit including identifying a first wire at a first location in an array of wires next to an empty location in a layout of the integrated circuit, adjusting a width of the first wire at the first location, and calculating a performance of a widened wire with regard to a first parameter. The method also includes comparing the calculated performance of the widened wire to a performance threshold of the first parameter, adjusting a degree of width adjustment of the widened wire according to a comparison result, and comparing the calculated performance of the width-adjusted widened wire to the performance threshold of the first parameter.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.

Abstract: A semiconductor device including a test circuit is disclosed. The semiconductor device includes a test pad coupled to a probe of a test device during a wafer test; a normal pad configured to receive a power or a signal during a normal mode; and a test circuit configured to perform a predetermined test operation based on a test signal received through the test pad. The test circuit is disposed below the normal pad.

Abstract: A semiconductor integrated circuit includes a plurality of logic circuits each being configurable to perform a logic function according to configuration data set therein, a memory that stores configuration information for use in setting the configuration data in each of the plurality of logic circuits, a test circuit configured to perform a test for detecting an error in each logic circuit, and an output circuit configured to output information indicating whether the error exists in one or more of the logic circuits based on a result of the test. In response to the output of the information indicating that the error exists, the configuration information stored in the memory is updated with new configuration information for setting the configuration data of each of the logic circuits other than one or more logic circuits having the error.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A manufacturing method of contact probes for a testing head comprises the steps of: providing a substrate made of a conductive material; and defining at least one contact probe by laser cutting the substrate. The method further includes at least one post-processing fine definition step of at least one end portion of the contact probe, that follows the step of defining the contact probe by laser cutting, the end portion being a portion including a contact tip or a contact head of the contact probe. The fine definition step does not involve a laser processing and includes geometrically defining the end portion of the contact probe with at least a substantially micrometric precision.

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

Abstract: A method of producing a secure integrated circuit (IC), including: loading the IC with a unique identification number (UID); loading the IC with a key derivation data (KDD) that is based upon a secret value K and the UID; producing a secure application configured with a manufacturer configuration parameter (MCP) and the secret value K and configured to receive the UID from the IC; producing a manufacturer diversification parameter (MDP) based upon the MCP and the secret value K and loading the MDP into the IC; wherein secure IC is configured to calculate a device specific key (DSK) based upon the received MDP and the KDD, and wherein the secure application calculates the DSK based upon the MCP, K, and the received UID.

Abstract: An electronic equipment is provided with a semiconductor device including an electrode joined to an electric conductor via a joint layer, a calculator and a controller. The semiconductor device is configured to pass current bidirectionally. The calculator is configured to calculate an imbalance EM progression index. The imbalance EM progression index is a difference between a forward current EM progression index and a reverse current EM progression index. The controller is configured to: adopt a condition to accelerate an increase rate of the reverse current EM progression index in at least a part of an excessive forward current EM period; and adopt a condition to accelerate an increase rate of the forward current EM progression index in at least a part of an excessive reverse current EM period.