Utilizing Integral Test Element Patents (Class 438/18)
  • Patent number: 10401387
    Abstract: A manufacturing method of contact probes for a testing head comprises the steps of: providing a substrate made of a conductive material; and defining at least one contact probe by laser cutting the substrate. The method further includes at least one post-processing fine definition step of at least one end portion of the contact probe, that follows the step of defining the contact probe by laser cutting, the end portion being a portion including a contact tip or a contact head of the contact probe. The fine definition step does not involve a laser processing and includes geometrically defining the end portion of the contact probe with at least a substantially micrometric precision.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 3, 2019
    Assignee: TECHNOPROBE S.P.A.
    Inventor: Raffaele Ubaldo Vallauri
  • Patent number: 10256188
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: April 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: 10237063
    Abstract: A method of producing a secure integrated circuit (IC), including: loading the IC with a unique identification number (UID); loading the IC with a key derivation data (KDD) that is based upon a secret value K and the UID; producing a secure application configured with a manufacturer configuration parameter (MCP) and the secret value K and configured to receive the UID from the IC; producing a manufacturer diversification parameter (MDP) based upon the MCP and the secret value K and loading the MDP into the IC; wherein secure IC is configured to calculate a device specific key (DSK) based upon the received MDP and the KDD, and wherein the secure application calculates the DSK based upon the MCP, K, and the received UID.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventor: Jan Rene Brands
  • Patent number: 10044352
    Abstract: An electronic equipment is provided with a semiconductor device including an electrode joined to an electric conductor via a joint layer, a calculator and a controller. The semiconductor device is configured to pass current bidirectionally. The calculator is configured to calculate an imbalance EM progression index. The imbalance EM progression index is a difference between a forward current EM progression index and a reverse current EM progression index. The controller is configured to: adopt a condition to accelerate an increase rate of the reverse current EM progression index in at least a part of an excessive forward current EM period; and adopt a condition to accelerate an increase rate of the forward current EM progression index in at least a part of an excessive reverse current EM period.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 7, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Satoshi Hirose
  • Patent number: 9960227
    Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 1, 2018
    Assignee: XILINX, INC.
    Inventors: Michael J. Hart, James Karp
  • Patent number: 9831139
    Abstract: A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the test element. A first wire is connected to the test element, and the first wire and the test element are part of a first layer disposed on a semiconductor substrate. A second wire is connected to the first wire, and is part of a second layer disposed on the semiconductor substrate, and the second layer is different from the first layer.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng Ding, Junjung Kim, Jeong HOON Ahn
  • Patent number: 9638744
    Abstract: An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: May 2, 2017
    Assignee: NXP USA, Inc.
    Inventors: Valérie Bernon-Enjalbert, Guillaume Founaud, Yuan Gao, Philippe Givelin
  • Patent number: 9541601
    Abstract: An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 10, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Pagani
  • Patent number: 9465058
    Abstract: A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 11, 2016
    Assignee: SK HYNIX INC.
    Inventors: Dong Uk Lee, Young Ju Kim
  • Patent number: 9362269
    Abstract: A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the circuit device comprises a substrate and a passive device disposed on the substrate. The passive device includes a bottom plate disposed over the substrate, a top plate disposed over the bottom plate, a spacing dielectric disposed between the bottom plate and the top plate, a first contact and a second contact electrically coupled to the top plate, and a third contact electrically coupled to the bottom plate. The passive device is configured to provide a target capacitance and a first target resistance. The passive device may also include a second top plate disposed over the bottom plate and configured to provide a second target resistance, such that the second target resistance is different from the first target resistance.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fu Chang, Jen-Pan Wang
  • Patent number: 9331059
    Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: May 3, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Robert Allinger, Gottfried Beer, Juergen Hoegerl
  • Patent number: 9304160
    Abstract: Aspects of the present disclosure describe an inspection apparatus which performs inspection on a smaller field of a wafer with structures for current collection. The defective via holes may be located based on the collected current. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: April 5, 2016
    Assignee: KLA-Tencor Corporation
    Inventors: Earl Jensen, Christopher Kirk
  • Patent number: 9287186
    Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
  • Patent number: 9185796
    Abstract: An OLED display including a substrate having a pixel area where an organic light emitting diode is formed, and a peripheral area surrounding the pixel area. Monitoring patterns are disposed in the peripheral area and are separated from each other.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyoung-Wook Min
  • Patent number: 9064716
    Abstract: An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 23, 2015
    Assignee: VIRTIUM TECHNOLOGY, INC.
    Inventors: Phan Hoang, Chinh Minh Nguyen
  • Patent number: 9048201
    Abstract: The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: June 2, 2015
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Neal Kistler, Don Bautista
  • Publication number: 20150144940
    Abstract: A display panel includes first to third test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer, and disposed adjacent to the first test pad in the second direction, a third test pad electrically connected to the third test line and disposed adjacent to the first test pad in the first direction, the third test pad and the third test line being formed from a same layer.
    Type: Application
    Filed: August 12, 2014
    Publication date: May 28, 2015
    Inventors: Ji-Yun HONG, Joon-Geol KIM, Jin-Won LEE, Ki-Won KIM
  • Patent number: 9043743
    Abstract: Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Zeljka Topic-Beganovic
  • Publication number: 20150140697
    Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Jin Cho, Hui Zang
  • Publication number: 20150140698
    Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Jin Cho, Hui Zang
  • Patent number: 9034637
    Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.
    Type: Grant
    Filed: April 5, 2008
    Date of Patent: May 19, 2015
    Assignee: NXP, B.V.
    Inventors: Matthias Merz, Youri V. Ponomarev, Gilberto Curatola
  • Publication number: 20150123129
    Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Chin-Yi Cho
  • Publication number: 20150115266
    Abstract: The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Audel A. SANCHEZ, Michele L. MIERA, Robert A. PRYOR, Jose L. SUAREZ
  • Patent number: 9018628
    Abstract: A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: April 28, 2015
    Assignee: Sony Corporation
    Inventor: Masaya Nagata
  • Patent number: 9006739
    Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: James V. Crain, Jr., Mark C. H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw, David B. Stone
  • Patent number: 9000785
    Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics SA
    Inventors: Clement Charbuillet, Patrick Scheer
  • Patent number: 8993355
    Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Chia-Lun Tsai, Shang-Yun Hou, Shin-Puu Jeng, Shih-Hsun Hsu, Wei-Ti Hsu, Lin-Ko Feng, Chun-Jen Chen
  • Patent number: 8987843
    Abstract: A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jerome L. Cann, David P. Vallett
  • Patent number: 8987014
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: March 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8987009
    Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Xilinx, Inc.
    Inventors: Cinti X. Chen, Myongseob Kim, Xiao-Yu Li, Mohsen H. Mardi
  • Patent number: 8980655
    Abstract: A test apparatus includes a foreign matter removal unit having a first slope provided with an abrasive coating or an adhesive sheet and a second slope provided with an abrasive coating or an adhesive sheet, the second slope facing the first slope in such a manner that an upper end of the second slope is spaced from an upper end of the first slope a greater distance than a lower end of the second slope is spaced from a lower end of the first slope, a test unit for testing electrical characteristics of a semiconductor chip, and a transfer unit for holding and releasing the semiconductor chip at a position above the first and second slopes and transferring the semiconductor chip to the test unit.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: March 17, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Okada, Takaya Noguchi, Norihiro Takesako, Kinya Yamashita, Hajime Akiyama
  • Patent number: 8977210
    Abstract: A radio-frequency circuit has a signal processing unit for processing a symmetrical input signal, two signal inputs for receiving the symmetrical input signal, a connection which is used as a ground point for the symmetrical signal, and a line which connects the signal inputs and has a length which essentially corresponds to an odd-numbered multiple of half the wavelength of the input signal. A method for testing a radio-frequency circuit having a signal processing unit for processing a symmetrical input signal is additionally provided.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventor: Johann Peter Forstner
  • Patent number: 8975095
    Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Ajay K. Royyuru, Gustavo A. Stolovitzky, Deqiang Wang
  • Publication number: 20150060854
    Abstract: A semiconductor device includes a main region suitable for performing a first test operation and a second test operation respectively based on a first test signal and a second test signal in a test mode, a first test region electrically connected to the main region and suitable for generating and transferring the first test signal to the main region in the test mode, and a second test region electrically connected to the main region or the first test region with a scribe lane disposed therebetween and suitable for generating and transferring the second test signal to the main region in the test mode.
    Type: Application
    Filed: December 15, 2013
    Publication date: March 5, 2015
    Applicant: SK hynix Inc.
    Inventors: Sang-Hoon SHIN, Sang-Jin BYEON
  • Patent number: 8969870
    Abstract: A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y1 and a width of X1, and the main array having a height of Y3. The pattern according to the example embodiment may further include at least one first field region comprising a monitoring region having a height of Y2 and a width of X2 and an auxiliary die region having a height of Y2 and comprising an auxiliary array of dies. The dimensions of the various regions may be proportional to one another, such that X2=n1×X1+adjustment1, Y2=n3×Y1+adjustment3, and Y3=n4×Y2+adjustment4, n1, n3, and n4 being integers.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8962354
    Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
  • Publication number: 20150048352
    Abstract: A wafer for forming an imaging element has a test pattern and a plurality of imaging element units. The wafer has an imaging region which includes a great number of photoelectric conversion pixels, an imaging element units and a test pattern. The test pattern includes a testing organic photoelectric conversion film and a testing counter electrode having the same configuration and formed at the same time as the organic photoelectric conversion film and a counter electrode, respectively of the photoelectric conversion pixels. A first testing terminal is electrically connected to the undersurface side of the testing organic photoelectric conversion film, and a second testing terminal is electrically connected to the testing counter electrode. A protective film is formed over the entire semiconductor wafer so as to cover the imaging region and the test pattern, and is then partially removed so that a part of each testing terminal is exposed.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 19, 2015
    Applicant: FUJIFILM CORPORATION
    Inventor: Takahiko ICHIKI
  • Patent number: 8956889
    Abstract: In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chih Lin, Mill-Jer Wang, Ching-Nen Peng, Hao Chen
  • Publication number: 20150044789
    Abstract: A method of manufacturing an array substrate 20 according to the present invention includes a line forming step, and line forming step includes following performances. A plurality of source lines 27 are formed on a glass substrate GS so as to extend from a first region A1 on the glass substrate GS to a second region A2 that is adjacent to the first region on an outer side thereof. A plurality of source driver side check lines 45A are formed on the glass substrate GS so as to extend from the second region A2 to a third region that is adjacent to the first region A1 on an outer side thereof and adjacent to the second region A2. A plurality of first line connection portions 49 are formed in the second region A2 and the first line connection portions 49 connect the source lines 27 and the first source driver side check lines 45A. A capacity stem line 43 and a common line 44 are formed to extend from the first region A1 to the third region A3.
    Type: Application
    Filed: July 12, 2012
    Publication date: February 12, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takaharu Yamada, Ryohki Itoh, Masahiro Yoshida, Hidetoshi Nakagawa, Takuya Ohishi, Masahiro Matsuda, Kazutoshi Kida
  • Publication number: 20150041809
    Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventors: Norbert Arnold, Jin Liu, Brian W. Messenger, Oliver D. Patterson
  • Patent number: 8952716
    Abstract: A method of detecting a defect of a semiconductor device includes forming test patterns and unit cell patterns in a test region a cell array region of a substrate, respectively, obtaining reference data with respect to the test patterns by irradiating an electron beam into the test region, obtaining cell data by irradiating the electron beam into the cell array region, and detecting defects of the unit cell patterns by comparing the obtained cell data with the obtained reference data.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Min Cho, Dong-Ryul Lee
  • Patent number: 8951814
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 8945956
    Abstract: Test dies having metrology test structures and methods of manufacture are disclosed. The method includes forming one or more metrology test structures in a test die that are identical to one or more structures formed in an adjacent product chip.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Anthony K. Stamper
  • Patent number: 8940554
    Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Toshiharu Furukawa, Douglas C. La Tulipe, Jr., William R. Tonti
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter
  • Patent number: 8932884
    Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Noah D. Zamdmer
  • Patent number: 8921855
    Abstract: It is disclosed that, as an embodiment, a test circuit includes a test signal supply unit configured to supply a test signal via a signal line to signal receiving units provided in a plurality of columns, wherein the test signal supply unit is a voltage buffer or a current buffer, and the test circuit has a plurality of test signal supply units and a plurality of signal lines, and wherein at least one test signal supply unit is electrically connected to one signal line different from a signal line to which another test signal supply unit is electrically connected.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: December 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Okita, Masaaki Iwane, Yu Arishima, Masaaki Minowa
  • Patent number: 8921139
    Abstract: A manufacturing method of an organic light emitting diode (OLED) display includes manufacturing a mother substrate including a plurality of panels formed with a plurality of anodes for each pixel and a test pad connected to each anode of the panel. The method further includes loading the mother substrate into a plasma chamber and applying a plasma voltage to the test pad of the mother substrate to perform a plasma surface treatment process. The test pad is applied with a different plasma voltage for each pixel.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jae-Young Lee
  • Patent number: 8921176
    Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Rama I. Hegde
  • Publication number: 20140367684
    Abstract: Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 18, 2014
    Inventors: Michael T. Coster, Mark A. DiRocco, Jeffrey P. Gambino, Kirk D. Peterson