Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: A substrate is provided wherein the substrate includes a number of site-isolated regions (SIRs). At least one material is deposited using PVD on a sub-set of the SIRs. At least one of the material or the process conditions are varied in a combinatorial manner across the sub-set of SIRs. Next, at least one material is deposited using ALD on a sub-set of the SIRs. At least one of the material or the process conditions are varied in a combinatorial manner across the sub-set of SIRs. Next, a material is deposited across the entire substrate using CVD. Each device within each of the SIRs is evaluated for at least one of an electric property or a material property.

Abstract: A wiring fault detection method according to an embodiment of the present invention is capable of determining that, in a case where a temperature rise value of a faulty portion exceeds a temperature rise threshold within a preset threshold of the number of frames, a corresponding pixel has a fault. A wiring fault detection apparatus according to the present invention includes a temperature measurement imaging unit that measure a temperature of a semiconductor substrate and forms an image thereof.

Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.

Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided.

Abstract: A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.

Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.

Abstract: An organic light-emitting display device including: a substrate including a pixel region and a non-pixel region; a first electrode formed on the pixel region in a first direction; a first wire coupled to the first electrode and formed in the non-pixel region; a second electrode formed in the pixel region in a second direction; a second wire coupled to the second electrode and formed in the non-pixel region; an organic thin film layer formed between the first electrode and the second electrode; a drive circuit coupled to the first wire and the second wire; and a passivation layer formed across the pixel region and the non-pixel region and having an opening to expose at least one of the first wire and the second wire.

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract: Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.

Abstract: A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, molding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules.

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Abstract: A method of generating an ion implantation distribution by a computer is disclosed. The method includes calculating ion implantation distribution regions in a case of generating the ion implantation distribution with a large tilt angle and generating an analytical model of the ion implantation distribution in correspondence with each of the ion implantation distribution regions by using a Gauss distribution model, in which the ion implantation distribution regions have different influence on a channel region depending on a gate structure formed on the ion distribution regions.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.

Abstract: The present disclosure provides a system for fabricating a semiconductor device. The system includes a semiconductor fabrication tool. The semiconductor fabrication tool has an integrated inter interface that measures a first process parameter of the fabrication tool. The system also includes a wireless sensor. The wireless sensor is detachably coupled to the fabrication tool. The wireless sensor measures a second process parameter of the fabrication tool. The second process parameter is different from the first process parameter.

Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: A chip on film (COF) package and a method for manufacturing same are provided. The COF package comprises a base film, a semiconductor chip mounted on the base film, a signal-inputting portion mounted on the base film, a first passive element mounted on the base film and comprising first and second terminals and a first signal line formed on the base film and connecting the first passive element to the semiconductor chip, wherein the first signal line comprises a connection pad connected to the first terminal of the first passive element and a first test line connected to the signal-inputting portion.

Abstract: A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are electrically connected to each other in a state in which a first connection surface of the first semiconductor substrate and a second connection surface of the second semiconductor substrate face each other. A concave portion is formed in at least one of the first connection surface and the second connection surface. An electrode, which is electrically connected to a portion of wirings included in a wiring layer provided in the first semiconductor substrate or the second semiconductor substrate in which the concave portion is formed and is capable of being electrically connected to an outside, is formed in an inside of the concave portion.

Abstract: A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

Abstract: A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 ? on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 ?m on the semiconductor substrate; and assessing hot carrier injection (HCI) for the PMOS element.

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract: The object of the invention is to improve the visual inspection yield of a semiconductor light emitting device. To achieve the object, a semiconductor light emitting device includes a semiconductor layer, a pad electrode on the layer, and a protection film covering at least the layer. The device includes at least one stopper arranged on a peripheral part of the pad electrode surface away from the film. The stopper has a semicircular arc shape opening toward the center of the pad electrode. In electrical/optical property inspection, if sliding on the pad electrode, a probe needle can be guided into the concave surface of the semicircular arc shape. The stopper can reliably hold the needle. It is avoidable that the needle contacts the film. It is preferable that each of positive/negative electrodes have the pad electrode, and a pair of stoppers be arranged in positions on the electrodes facing each other.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.

Abstract: A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel cap

Abstract: A method for testing TSV structures includes providing a wafer having a front side and a back side, the wafer further comprising a plurality of TSV structures formed therein; thinning the wafer from the back side of the wafer; forming a first under bump metallization layer on the back side of the wafer blanketly; providing a probing card to the front side of the wafer to test the TSV structures; and patterning the first UBM layer.

Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.

Abstract: To provide a simple method for evaluating reliability of a transistor, a simple test which correlates with a bias-temperature stress test (BT test) is performed instead of the BT test. Specifically, a gate current value is measured in the state where a voltage lower than the threshold voltage of an n-channel transistor whose channel region includes an oxide semiconductor is applied between a gate and a source of the transistor and a potential applied to a drain is higher than a potential applied to the gate. The evaluation of the gate current value can be simply performed compared to the case where the BT test is performed; for example, it takes short time to measure the gate current value. That is, reliability of a semiconductor device including the transistor can be easily evaluated.

Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.

Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes heating a resistor pattern by scanning the resistor pattern with a first beam. The resistor pattern includes resistors, and a connection structure connecting the resistors in series. The resistors is arranged in matrix of two or more rows and two or more columns. The method includes further heating the resistor pattern by scanning the resistor pattern with a second beam having a different scan direction as that of the first beam.

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract: A method for fabricating a semiconductor device comprising: a first process for attaching a first supporting substrate having a plurality of through holes to a semiconductor substrate having a first surface and a second surface, so that each of the through holes is opposed to a semiconductor device formed in the semiconductor substrate; a second process for contacting probes of an electric characteristic inspection apparatus with a first electrode formed on the first surface, and a second electrode formed on the second surface via the through hole; and a third process for measuring electric characteristic of the semiconductor device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.

Abstract: A thermal processing apparatus and method with predictive temperature correction. Distances are measured from a backside of the wafer relative to a reference plane. Heat is transferred to the backside of the substrate in relation to the measured distances. This allows a baking unit to uniformly heat the substrate to compensate for irregularities or warpage.

Abstract: Provided is an ion implantation method of transporting ions generated by an ion source to a wafer and implanting the ions into the wafer by irradiating an ion beam on the wafer, including, during the ion implantation into the wafer, using a plurality of detection units which can detect an event having a possibility of discharge and determining a state of the ion beam based on existence of detected event having a possibility of discharge and a degree of influence of the event on the ion beam.

Abstract: Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.

Abstract: The invention provides a measurement of lateral diffusion of implanted ions in the doped well regions of semiconductor devices comprising: designing a test model having active areas, the P-type and N-type doped well regions of the active areas are separated by STI, and the bottom width of the STI is determined; performing multiple processes on the test model comprising the ion implantation process and the tungsten interconnection process to simulate a semiconductor device structure, wherein during the ion implantation process, in the P-type or N-type doped well regions, only the first procedure of the ion implantation process is performed; scanning the test model, obtaining a light-dark pattern of the tungsten interconnects. The present invention is convenient and accessible and can provide reference to optimize the property of the doped well regions of the semiconductor devices and ensure the yield enhancement.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: An extremely non-degenerate two photon absorption (END-2PA) method and apparatus provide for irradiating a semiconductor material substrate simultaneously with two photons each of different energy less than a bandgap energy of the semiconductor material substrate but in an aggregate greater than the bandgap energy of the semiconductor material substrate. A ratio of a higher energy photon energy to a lower energy photon energy is at least about 3.0. Alternatively, or as an adjunct, the higher energy photon has an energy at least about 75% of the bandgap energy and the lower energy photon has an energy no greater than about 25% of the bandgap energy.

Abstract: A defect inspection device for a silicon wafer comprises: an infrared light illumination which illuminates the silicon wafer with a light power that has been adjusted in accordance with a specific resistance value of the silicon wafer; and an imaging unit constituted by a line sensor array that is sensitive to infrared light, which captures the silicon wafer.

Abstract: The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

Abstract: A test system for facilitating determining whether a plasma processing system (which includes a plasma processing chamber) is ready for processing wafers. The test system may include a computer-readable medium storing at least a test program. The test program may include code for receiving electric parameter values derived from signals detected by at least one sensor when no plasma is present in the plasma processing chamber. The test program may also include code for generating electric model parameter values using the electric parameter values and a mathematical model. The test program may also include code for comparing the electric model parameter values with baseline model parameter value information. The test program may also include code for determining readiness of the plasma processing system based on the comparison. The test system may also include circuit hardware for performing one or more tasks associated with the test program.