Having Heterojunction (e.g., Hemt, Modfet, Etc.) Patents (Class 438/172)
  • Patent number: 11569375
    Abstract: A vertical field-effect transistor (FET), comprising a first doped region of a first material, said first doped region having a first doping and being formed on a surface of a substrate, a second doped region of said first material, said second doped region having a second doping and being formed on the first doped region, and a third doped region of said first material, said third doped region having a third doping and being formed on the second doped region, wherein the first doped region has a first width along a first direction parallel to said surface of the substrate, the second doped region has a second width along said first direction, the third doped region has a third width along said first direction, the second width being smaller than the first and third widths.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: January 31, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventor: Biqin Huang
  • Patent number: 11527641
    Abstract: The present disclosure relates to semiconductor power devices, and in particular, to a high-electron-mobility transistor (HEMT) with high voltage endurance capability and a preparation method thereof. The high-electron-mobility transistor with high voltage endurance capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer and a substrate, wherein the P-type nitride semiconductor layer is between the barrier layer and the substrate, which is insufficient to significantly deplete a two-dimensional electron gas in a channel except a gate stack, the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 13, 2022
    Inventor: Zilan Li
  • Patent number: 11462636
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: October 4, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11424409
    Abstract: A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 23, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Peter Krogstrup Jeppesen, Yu Liu, Alessandra Luchini
  • Patent number: 11380771
    Abstract: A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a channel layer, a barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The channel layer is disposed on a substrate. A surface of a portion of the channel layer within a first region of the HEMT device includes a polar plane and a non-polar plane. The barrier layer is conformally disposed on the channel layer. The first gate electrode is disposed on the barrier layer, and located within the first region. The first drain electrode and the first source electrode are disposed within the first region, and located at opposite sides of the first gate electrode.
    Type: Grant
    Filed: November 3, 2019
    Date of Patent: July 5, 2022
    Assignee: Nuvoton Technology Corporation
    Inventors: Chih-Wei Chen, Wen-Ying Wen
  • Patent number: 11355600
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: June 7, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
  • Patent number: 11329148
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 11171052
    Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a conductive line layer over a semiconductor substrate. The conductive line layer includes a metal line. The method also includes forming a conductive pillar on and in contact with the metal line. The method further includes depositing a dielectric layer over the conductive line layer to cover the conductive pillar, and etching the dielectric layer to form a trench. The conductive pillar is exposed through the trench. In addition, the method includes filling the trench with a conductive material to form a conductive line.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10947616
    Abstract: In a method for forming a vapor deposition pattern using a vapor deposition mask provided with a plurality of openings corresponding to a pattern that is produced by vapor deposition, and forming a vapor deposition pattern in a vapor deposition target, the method includes a close contact step of disposing the vapor deposition mask on one surface side of the vapor deposition target, disposing a pressing member and a magnetic plate in layer in this order on the other surface side of the vapor deposition target, and bringing the vapor deposition target and the vapor deposition mask into close contact with each other by using magnetism of the magnetic plate, and a vapor deposition pattern forming step of causing a vapor deposition material released from a vapor deposition source to adhere to the vapor deposition target through openings after the close contact step, and forming the vapor deposition pattern in the vapor deposition target.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: March 16, 2021
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Yoshinori Hirobe, Yoshiko Miyadera, Katsunari Obata, Naoto Yamada
  • Patent number: 10890712
    Abstract: Photonic devices having Al1-xScxN and AlyGa1-yN materials, where Al is Aluminum, Sc is Scandium, Ga is Gallium, and N is Nitrogen and where 0<x?0.45 and 0?y?1.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 12, 2021
    Assignees: Raytheon BBN Technologies Corp., Raytheon Company
    Inventors: Mohammad Soitani, Eduardo M. Chumbes
  • Patent number: 10868136
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Patent number: 10804359
    Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Sanaz Gardner, Seung Hoon Sung
  • Patent number: 10468553
    Abstract: A semiconductor comprising at least one contact, formed on an interface with the semiconductor, the contact comprising at least a layer of a first metal, the first metal being of sufficient amount to impart a first property in the layer; and a second metal diffused in the layer, the second metal having a concentration in the layer sufficiently low such that the second metal does not diminish significantly the first property of the layer, the concentration being sufficiently high such that the second metal imparts significantly a second property in the layer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 5, 2019
    Assignee: SORAA, INC.
    Inventor: Christophe A. Hurni
  • Patent number: 10469041
    Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony Kendall Stamper, Vibhor Jain, Humberto Campanella Pineda, John Joseph Pekarik
  • Patent number: 10439058
    Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Tinggang Zhu
  • Patent number: 10418473
    Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 17, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
  • Patent number: 10388604
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Hyung Jong Lee, Boram Im
  • Patent number: 10319644
    Abstract: In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, Chun Lin Tsai, Alexander Kalnitsky
  • Patent number: 10269923
    Abstract: In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Wei-Hao Lee, Huan-yu Shih
  • Patent number: 10211296
    Abstract: An epitaxial group-III-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-III-nitride layers, wherein the interlayer structure comprises a group-III-nitride interlayer material having a larger band gap than the materials of the first and second group-III-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-III-nitride layers.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 19, 2019
    Assignee: AzurSpace Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Patent number: 10026814
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 17, 2018
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Patent number: 9978684
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changseop Yoon, Hyung Jong Lee, Boram Im
  • Patent number: 9951912
    Abstract: A lighting apparatus for emitting polarized white light, which includes at least a first light source for emitting primary light comprised of one or more first wavelengths and having a first polarization direction; and at least a second light source for emitting secondary light in the first polarization direction, comprised of one or more secondary wavelengths, wherein the first light and the secondary light are combined to produce a polarized white light. The lighting apparatus may further comprise a polarizer for controlling the primary light's intensity, wherein a rotation of the polarizer varies an alignment of its polarization axis with respect to the first polarization direction, which varies transmission of the primary light through the polarizer, which controls a color co-ordinate or hue of the white light.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 24, 2018
    Assignee: The Regents of the University of California
    Inventors: Natalie Fellows DeMille, Hisashi Masui, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 9929248
    Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiang Fan, Chun-Hsiung Lin, Mao-Lin Huang
  • Patent number: 9814143
    Abstract: A method of forming a pattern with high aspect ratio on a polycrystalline aluminum nitride substrate comprises the steps of (A) providing an aluminum nitride substrate and forming a barrier layer on the aluminum nitride substrate; (B) etching the barrier layer with an energy beam to form at least one recess in the barrier layer; (C) plasma etching the substrate to deepen the recess into the aluminum nitride substrate; (D) removing the barrier layer to obtain the aluminum nitride substrate having at least one pattern with high aspect ratio. The method uses the energy beam to directly form a pattern on the barrier layer, and further employs plasma etching to prepare the aluminum nitride substrate having a pattern with high aspect ratio quickly and effectively.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 7, 2017
    Assignee: National Chung Shan Institute of Science and Technology
    Inventors: Chung-Yen Lu, Yi-Hsiuan Yu, Chia-Ting Lin, Lea-Hwung Leu
  • Patent number: 9728613
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Patent number: 9660069
    Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Christopher Peter D'Emic, William J. Gallagher, Effendi Leobandung, Devendra K. Sadana
  • Patent number: 9646879
    Abstract: A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 9, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akinobu Kakimoto, Youichirou Chiba, Takumi Yamada, Daisuke Suzuki
  • Patent number: 9564503
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9559093
    Abstract: A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component has a breakdown voltage less than a breakdown voltage of the GaN FET. The voltage dropping component is formed to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: January 31, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • Patent number: 9548363
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 17, 2017
    Assignee: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Patent number: 9536873
    Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 3, 2017
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masakazu Kanechika, Hiroyuki Ueda, Hidemoto Tomita
  • Patent number: 9508807
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chen-Ju Yu, King-Yuen Wong, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 9508646
    Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
  • Patent number: 9490357
    Abstract: A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 8, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Sameh G. Khalil, Andrea Corrion, Karim S. Boutros
  • Patent number: 9484340
    Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 1, 2016
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masakazu Kanechika, Hiroyuki Ueda, Hidemoto Tomita
  • Patent number: 9425281
    Abstract: Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: August 23, 2016
    Assignee: IMEC
    Inventor: Stefaan Decoutere
  • Patent number: 9340899
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 17, 2016
    Assignee: The Regents of the University of California
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 9337389
    Abstract: Group-III nitride structure comprising at least one structure pyramid having a base having at least four sides. The structure pyramid comprises an inner pyramid having a base having at least four sides, which inner pyramid is made of a first group-III nitride. The inner pyramid is coated with an inner first layer made of a second group-III nitride and an outer second layer made of a third group-III nitride, wherein the second group-III nitride has a lower band gap than the first group-III nitride and a lower band gap than the third group-III nitride. The base of the structure pyramid is elongated resulting in an upper ridge creating at least one anisotropic quantum dot.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 10, 2016
    Assignee: POLAR LIGHT TECHNOLOGIES AB
    Inventors: Anders Lundskog, Chih-Wei Hsu, Fredrik Karlsson
  • Patent number: 9318572
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Patent number: 9312341
    Abstract: A compound semiconductor device includes: a substrate; and a compound semiconductor lamination structure formed over the substrate, the compound semiconductor lamination structure including a buffer layer containing an impurity, and an active layer formed over the buffer layer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Norikazu Nakamura
  • Patent number: 9306027
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Toshiyuki Takewaki, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
  • Patent number: 9293646
    Abstract: In a method of manufacture for a nitride semiconductor light emitting element including: a monocrystalline substrate; and an AlN layer; and a first nitride semiconductor layer of a first electrical conductivity type; and a light emitting layer made of an AlGaN-based material; and a second nitride semiconductor layer of a second electrical conductivity type, a step of forming the AlN layer includes: a first step of supplying an Al source gas and a N source gas into the reactor to generate a group of AlN crystal nuclei having Al-polarity to be a part of the AlN layer on the surface of the monocrystalline substrate; and a second step of supplying the Al source gas and the N source gas into the reactor to form the AlN layer, after the first step.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 22, 2016
    Assignees: PANASONIC CORPORATION, RIKEN
    Inventors: Takayoshi Takano, Takuya Mino, Norimichi Noguchi, Kenji Tsubaki, Hideki Hirayama
  • Patent number: 9287368
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Akira Yoshioka, Yoshiharu Takada
  • Patent number: 9263544
    Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: February 16, 2016
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Takeshi Araya, Tsutomu Komatani
  • Patent number: 9257548
    Abstract: A nitride semiconductor element includes a Si substrate; a buffer layer including (a) an AlN layer formed on a primary surface of the Si substrate; and (b) an AlGaN deposit layer formed by laminating multiple AlGaN layers on the AlN layer and having a total thickness ranging from 100 nm to 500 nm; a GaN electron transfer layer formed on the AlGaN deposit layer and having a thickness ranging from 500 nm to 2000 nm provided that the GaN electron transfer layer is thicker than the AlGaN deposit layer; and an AlGaN electron supply layer formed on the GaN electron transfer layer, wherein the AlGaN deposit layer includes an AlGaN layer that is provided closer to the AlN layer and has an Al component that ranges from about 40% to about 60%, and a reference AlGaN layer that has an Al component (%) that is lower than that of the AlGaN layer.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: February 9, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Shinya Takado, Norikazu Ito, Atsushi Yamaguchi
  • Patent number: 9236443
    Abstract: High electron mobility transistors (HEMTs) having improved I-V characteristics and reliability are provided. According to one embodiment, a selective implantation is performed to form a damage region in a gate-to-drain region of, for example, an I?A?N/GaN HEMT. The selective implantation can be performed by irradiating some or all of a gate-to-drain region of an InAlN/GaN HEMT on a substrate with protons or other ions such as Ge ions, He ions, N ions, or O ions. The damage region can extend in a region below a 2DEG interface of the HEMT.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: January 12, 2016
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Fan Ren, Stephen John Pearton, Jihyun Kim
  • Patent number: 9231059
    Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: January 5, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Noboru Negoro, Hidekazu Umeda, Nanako Hirashita, Tetsuzo Ueda
  • Patent number: 9190474
    Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 17, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Noboru Negoro, Hidekazu Umeda, Nanako Hirashita, Tetsuzo Ueda
  • Patent number: 9178016
    Abstract: A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias Strassburg, Roman Knoefler