Abstract: A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

Abstract: A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes.

Abstract: Disclosed are a bidirectional power device and a method for manufacturing the same. The bidirectional power device includes a semiconductor layer, a plurality of trenches located in the semiconductor layer, a gate dielectric layer located on an inner wall of each of the plurality of trenches, a control gate located at a lower portion of each of the plurality of trenches, a shield gate located at an upper portion of each of the plurality of trenches and an isolation layer located between the control gate and the shield gate. When the bidirectional power device is turned off, charges of a source region and a drain region are depleted by the shield gate through a shield dielectric layer, thereby improving voltage withstand property. When the bidirectional power device is turned on, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.

Abstract: A semiconductor device includes a main groove formed in a main surface of a substrate, a semiconductor region formed in contact with a surface of the main groove, an electron supply region formed in contact with a surface of the semiconductor region on opposite sides of at least side surfaces of the main groove to generate a two-dimensional electron gas layer in the semiconductor region, and a first electrode and a second electrode formed in contact with the two-dimensional electron gas layer and apart from each other.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode and a single field plate. The source electrode, the drain electrode, and the gate electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is between the source and drain electrodes. The single field plate is disposed over the gate electrode and extends toward the drain electrode. The field plate has a first end part, a second end part and the central part. The first and the second end parts are located at substantially the same height. Portions of the central part are in a position lower than that of the first and second end parts, and the first end part extends laterally in a length greater than a width of the gate electrode.

Abstract: Embodiments of this application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.

Abstract: A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

Abstract: A high electron mobility transistor (HEMT) includes a channel layer, a plurality of barrier layers, and a p-type semiconductor layer. The barrier layers have an energy band gap greater than that of the channel layer. A gate electrode is arranged on the p-type semiconductor layer. A source electrode and a drain electrode are apart from the p-type semiconductor layer and the gate electrode on the barrier layers. Impurity concentrations of the barrier layers are different from each other in a drift area between the source electrode and the drain electrode.

Abstract: A vertical field-effect transistor (FET), comprising a first doped region of a first material, said first doped region having a first doping and being formed on a surface of a substrate, a second doped region of said first material, said second doped region having a second doping and being formed on the first doped region, and a third doped region of said first material, said third doped region having a third doping and being formed on the second doped region, wherein the first doped region has a first width along a first direction parallel to said surface of the substrate, the second doped region has a second width along said first direction, the third doped region has a third width along said first direction, the second width being smaller than the first and third widths.

Abstract: The present disclosure relates to semiconductor power devices, and in particular, to a high-electron-mobility transistor (HEMT) with high voltage endurance capability and a preparation method thereof. The high-electron-mobility transistor with high voltage endurance capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer and a substrate, wherein the P-type nitride semiconductor layer is between the barrier layer and the substrate, which is insufficient to significantly deplete a two-dimensional electron gas in a channel except a gate stack, the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.

Abstract: A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a channel layer, a barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The channel layer is disposed on a substrate. A surface of a portion of the channel layer within a first region of the HEMT device includes a polar plane and a non-polar plane. The barrier layer is conformally disposed on the channel layer. The first gate electrode is disposed on the barrier layer, and located within the first region. The first drain electrode and the first source electrode are disposed within the first region, and located at opposite sides of the first gate electrode.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a conductive line layer over a semiconductor substrate. The conductive line layer includes a metal line. The method also includes forming a conductive pillar on and in contact with the metal line. The method further includes depositing a dielectric layer over the conductive line layer to cover the conductive pillar, and etching the dielectric layer to form a trench. The conductive pillar is exposed through the trench. In addition, the method includes filling the trench with a conductive material to form a conductive line.

Abstract: In a method for forming a vapor deposition pattern using a vapor deposition mask provided with a plurality of openings corresponding to a pattern that is produced by vapor deposition, and forming a vapor deposition pattern in a vapor deposition target, the method includes a close contact step of disposing the vapor deposition mask on one surface side of the vapor deposition target, disposing a pressing member and a magnetic plate in layer in this order on the other surface side of the vapor deposition target, and bringing the vapor deposition target and the vapor deposition mask into close contact with each other by using magnetism of the magnetic plate, and a vapor deposition pattern forming step of causing a vapor deposition material released from a vapor deposition source to adhere to the vapor deposition target through openings after the close contact step, and forming the vapor deposition pattern in the vapor deposition target.

Abstract: Photonic devices having Al1-xScxN and AlyGa1-yN materials, where Al is Aluminum, Sc is Scandium, Ga is Gallium, and N is Nitrogen and where 0<x?0.45 and 0?y?1.

Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.

Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.

Abstract: A semiconductor comprising at least one contact, formed on an interface with the semiconductor, the contact comprising at least a layer of a first metal, the first metal being of sufficient amount to impart a first property in the layer; and a second metal diffused in the layer, the second metal having a concentration in the layer sufficiently low such that the second metal does not diminish significantly the first property of the layer, the concentration being sufficiently high such that the second metal imparts significantly a second property in the layer.

Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.

Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.

Abstract: In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.

Abstract: In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed.

Abstract: An epitaxial group-III-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-III-nitride layers, wherein the interlayer structure comprises a group-III-nitride interlayer material having a larger band gap than the materials of the first and second group-III-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-III-nitride layers.

Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.

Abstract: A lighting apparatus for emitting polarized white light, which includes at least a first light source for emitting primary light comprised of one or more first wavelengths and having a first polarization direction; and at least a second light source for emitting secondary light in the first polarization direction, comprised of one or more secondary wavelengths, wherein the first light and the secondary light are combined to produce a polarized white light. The lighting apparatus may further comprise a polarizer for controlling the primary light's intensity, wherein a rotation of the polarizer varies an alignment of its polarization axis with respect to the first polarization direction, which varies transmission of the primary light through the polarizer, which controls a color co-ordinate or hue of the white light.

Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.

Abstract: A method of forming a pattern with high aspect ratio on a polycrystalline aluminum nitride substrate comprises the steps of (A) providing an aluminum nitride substrate and forming a barrier layer on the aluminum nitride substrate; (B) etching the barrier layer with an energy beam to form at least one recess in the barrier layer; (C) plasma etching the substrate to deepen the recess into the aluminum nitride substrate; (D) removing the barrier layer to obtain the aluminum nitride substrate having at least one pattern with high aspect ratio. The method uses the energy beam to directly form a pattern on the barrier layer, and further employs plasma etching to prepare the aluminum nitride substrate having a pattern with high aspect ratio quickly and effectively.

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

Abstract: A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region.

Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.

Abstract: A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component has a breakdown voltage less than a breakdown voltage of the GaN FET. The voltage dropping component is formed to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features.

Abstract: A HEMT device comprising a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.

Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

Abstract: Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

Abstract: Group-III nitride structure comprising at least one structure pyramid having a base having at least four sides. The structure pyramid comprises an inner pyramid having a base having at least four sides, which inner pyramid is made of a first group-III nitride. The inner pyramid is coated with an inner first layer made of a second group-III nitride and an outer second layer made of a third group-III nitride, wherein the second group-III nitride has a lower band gap than the first group-III nitride and a lower band gap than the third group-III nitride. The base of the structure pyramid is elongated resulting in an upper ridge creating at least one anisotropic quantum dot.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A compound semiconductor device includes: a substrate; and a compound semiconductor lamination structure formed over the substrate, the compound semiconductor lamination structure including a buffer layer containing an impurity, and an active layer formed over the buffer layer.