Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

Abstract: A nitride semiconductor element includes a Si substrate; a buffer layer including (a) an AlN layer formed on a primary surface of the Si substrate; and (b) an AlGaN deposit layer formed by laminating multiple AlGaN layers on the AlN layer and having a total thickness ranging from 100 nm to 500 nm; a GaN electron transfer layer formed on the AlGaN deposit layer and having a thickness ranging from 500 nm to 2000 nm provided that the GaN electron transfer layer is thicker than the AlGaN deposit layer; and an AlGaN electron supply layer formed on the GaN electron transfer layer, wherein the AlGaN deposit layer includes an AlGaN layer that is provided closer to the AlN layer and has an Al component that ranges from about 40% to about 60%, and a reference AlGaN layer that has an Al component (%) that is lower than that of the AlGaN layer.

Abstract: High electron mobility transistors (HEMTs) having improved I-V characteristics and reliability are provided. According to one embodiment, a selective implantation is performed to form a damage region in a gate-to-drain region of, for example, an I?A?N/GaN HEMT. The selective implantation can be performed by irradiating some or all of a gate-to-drain region of an InAlN/GaN HEMT on a substrate with protons or other ions such as Ge ions, He ions, N ions, or O ions. The damage region can extend in a region below a 2DEG interface of the HEMT.

Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

Abstract: A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride.

Abstract: A semiconductor device includes an electron transit layer formed on a substrate; an electron supply layer formed on the electron transit layer; a doping layer formed on the electron supply layer, the doping layer being formed with a nitride semiconductor in which an impurity element to become p-type and C are doped; a p-type layer formed on the doping layer, the p-type layer being formed with a nitride semiconductor in which the impurity element to become p-type is doped; a gate electrode formed on the p-type layer; and a source electrode and a drain electrode formed on the doping layer or the electron supply layer. The p-type layer is formed in an area immediately below the gate electrode, and a density of the C doped in the doping layer is greater than or equal to 1×1017 cm?3 and less than or equal to 1×1019 cm?3.

Abstract: A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×1019 ions/cm3. The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.

Abstract: A semiconductor device includes: a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer; a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and a p-type-dopant-diffusion-blocking layer.

Abstract: An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.

Abstract: An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.

Abstract: High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a source electrode, a gate electrode, a drain electrode, a channel formation layer including at least a 2-dimensional electron gas (2DEG) channel, a channel supplying layer for forming the 2DEG channel in the channel formation layer, a portion of the channel supplying layer including a first oxygen treated region. The channel supplying layer may include a second oxygen treated region that extends from the first oxygen treated region towards the drain electrode, and the depth and concentration of oxygen of the second oxygen treated region may be less than those of the first oxygen treated region.

Abstract: According to one embodiment of the present invention, an electronic device includes: a carbon layer including graphene, a thin film layer formed on the carbon layer, a channel layer formed on the thin film layer, a current cutoff layer formed between the thin film layer and the channel layer so as to cut off the flow of current between the thin film layer and the channel layer, and a source electrode and a drain electrode formed on the channel layer.

Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source feature and a drain feature on the second III-V compound layer, depositing a p-type layer on a portion of the second III-V compound layer between the source feature and the drain feature, and forming a gate electrode on the p-type layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.

Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.

Abstract: A semiconductor device includes: a substrate; nitride semiconductor layers disposed over the substrate; a source electrode and a drain electrode disposed over the nitride semiconductor layers; a first insulating layer disposed over the nitride semiconductor layers, the source electrode and the drain electrode; a second insulating layer disposed over the first insulating layer; a first opening disposed in the second insulating layer and the first insulating layer and between the source electrode and the drain electrode, a portion of the nitride semiconductor layer being exposed in the first opening; a second opening disposed in the second insulating layer and between the source electrode and the drain electrode, a portion of the first insulating layer being exposed in the second opening; and a gate electrode disposed over the second insulating layer to bury the first opening and at least a portion of the second opening.

Abstract: A semiconductor device includes: a first nitride semiconductor layer formed over a substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer; element isolation regions formed in a part of the second nitride semiconductor layer and the first nitride semiconductor layer; a gate electrode, source electrodes, and a drain electrode formed over the second semiconductor layer and the element isolation regions; and a drain field plate formed in such a manner as to project from upper portions of side surfaces of the drain electrode.

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.

Abstract: Provided are a high electron mobility transistor and/or a method of manufacturing the same. The high electron mobility transistor includes a channel layer, a channel supply layer formed on the channel layer to generate a two-dimensional electron gas (2DEG), a depletion forming layer formed on the channel supply layer, a gate electrode formed on the depletion forming layer, and a barrier layer formed between the depletion forming layer and the gate electrode. Holes may be prevented from being injected into the depletion forming layer from the gate electrode, thereby reducing a gate forward current.

Abstract: A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer.

Abstract: There are disclosed herein various implementations of a III-Nitride device and method for its fabrication. The III-Nitride device includes a III-Nitride buffer layer situated over a substrate, the III-Nitride buffer layer having a first bandgap. In addition, the device includes a III-Nitride heterostructure situated over the III-Nitride buffer layer and configured to produce a two-dimensional electron gas (2DEG); the III-Nitride heterostructure including a channel layer having a second bandgap smaller than the first bandgap. The III-Nitride device also includes a buffer termination body situated between the III-Nitride buffer layer and the channel layer, the buffer termination body including a III-Nitride material having a third bandgap smaller than the first bandgap and larger the second bandgap.

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.

Abstract: A semiconductor device comprises a semiconductor body of a first semiconductor material, wherein at least a part of the semiconductor body constitutes a drift zone of a first conductivity type. The semiconductor device further comprises a channel layer structure comprising a semiconductor heterojunction between first and second semiconductor layers electrically coupled to the drift zone. The first and second semiconductor layers include semiconductor materials that are different to the first semiconductor material.

Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.

Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.

Abstract: An enhancement-mode device comprises: a substrate, an epitaxial multilayer structure formed on the substrate, and a gate region formed on the epitaxial multilayer structure, where the epitaxial multilayer structure sequentially comprises from the substrate: a nucleation layer, a buffer layer, a heterojunction structure layer, a second gallium nitride layer, a nitride transition layer and a dielectric layer, where the heterojunction structure layer comprises a gallium nitride channel layer and a barrier layer which has a sandwich structure, and a middle layer of the sandwich structure is a first gallium nitride layer; and the gate region comprises a gate metal layer and a p-type nitride layer located under the gate metal layer, wherein the p-type nitride layer is embedded into the epitaxial multilayer structure, a bottom of the p-type nitride layer is in contact with the first gallium nitride layer of the sandwich structure.

Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.

Abstract: Provided is a method of manufacturing a gallium-nitride-based semiconductor device, comprising forming a first semiconductor layer of a gallium-nitride-based semiconductor; and forming a recessed portion by dry etching a portion of the first semiconductor layer via a microwave plasma process using a bromine-based gas.

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel.

Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: A semiconductor device includes a superlattice buffer layer formed on a substrate. An upper buffer layer is formed on the superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the upper busier layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. A gate electrode, a source electrode and a drain electrode are formed on the second semiconductor layer. The superlattice buffer layer is formed by cyclically laminating nitride semiconductor films having different composition. The upper buffer layer is formed by a nitride semiconductor material having a band gap wider than a band gap of the first semiconductor layer and doped with an impurity element that causes a depth of an acceptor level to be greater than or equal to 0.5 eV.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Abstract: A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a Silicon substrate and depositing a photoresist material thereover, removing a predetermined portion first dielectric layer to define an exposed portion, implanting dopants into the exposed portion to define a doped portion, preferentially removing Silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a Silicon face having a 111 orientation, and forming a 2DEG on at least one sidewall.

Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.

Abstract: A semiconductor device includes a buffer layer made of nitride semiconductor on a substrate, a first semiconductor layer made of nitride semiconductor on the buffer layer, a second semiconductor layer made of nitride semiconductor on the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, wherein the buffer layer has elements doped therein that include both an element selected from a group consisting of C, Mg, Fe, and Co and an element selected from a group consisting of Si, Ge, Sn, and O.

Abstract: A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

Abstract: The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based on the set ion beam scanning speed and the set mechanical scanning speed of the object. In the setting in advance, each of the ion beam scanning speeds is set based on each of ion beam scanning amplitudes changing severally according to a surface outline of an object which is irradiated with the ions so that an ion beam scanning frequency is maintained constant for any of ion beam scanning amplitudes, and the mechanical scanning speed of the object corresponding to the ion beam scanning speed is set so that an ion implantation dose per unit area to be implanted into the surface of the object is maintained constant.

Abstract: There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening 28 that extends from an n+-type contact layer 8 and reaches an n-type drift layer 4 through a p-type barrier layer 6 is formed. The semiconductor device includes a regrown layer 27 located so as to cover portions of the p-type barrier layer 6 and the like that are exposed to the opening, the regrown layer 27 including an undoped GaN channel layer 22 and a carrier supply layer 26; an insulating layer 9 located so as to cover the regrown layer 27; and a gate electrode G located on the insulating layer 9. In the p-type barrier layer, the Mg concentration A (cm?3)and the hydrogen concentration B (cm?3) satisfy 0.1<B/A<0.9 . . . (1).

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), a regrown structure disposed in and epitaxially coupled with the barrier layer, the regrown structure including nitrogen (N) and at least one of aluminum (Al) or gallium (Ga) and being epitaxially deposited at a temperature less than or equal to 600° C., and a gate terminal disposed in the barrier layer, wherein the regrown structure is disposed between the gate terminal and the buffer layer. Other embodiments may be described and/or claimed.

Abstract: A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration.

Abstract: A heterojunction semiconductor device having a semiconductor body is provided. The semiconductor body includes a first semiconductor region comprising aluminum gallium nitride, a second semiconductor region comprising gallium nitride and forming a heterojunction with the first semiconductor region, an n-type third semiconductor region, a p-type fourth semiconductor region forming a first rectifying junction with the third semiconductor region, and an n-type seventh semiconductor region adjoining the heterojunction formed between the first semiconductor region and the second semiconductor region. The first rectifying junction forms a rectifying junction of a transistor structure which is in ohmic contact with the seventh semiconductor region. Further, a method for producing such a heterojunction semiconductor device is provided.

Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.