Having Heterojunction (e.g., Hemt, Modfet, Etc.) Patents (Class 438/172)
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Patent number: 7868318Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.Type: GrantFiled: November 7, 2008Date of Patent: January 11, 2011Assignee: Intel CorporationInventors: Mantu Hudait, Robert S. Chau, Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey
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Publication number: 20100330754Abstract: Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.Type: ApplicationFiled: June 24, 2010Publication date: December 30, 2010Inventor: Francois Hebert
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Publication number: 20100320505Abstract: A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face.Type: ApplicationFiled: June 3, 2010Publication date: December 23, 2010Applicant: FUJITSU LIMITEDInventors: Naoya OKAMOTO, Atsushi Yamada
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Publication number: 20100323506Abstract: A method for fabricating a semiconductor layer comprising: a) growing a semiconductor layer on a foreign substrate; b) forming at least one opening on the semiconductor layer, wherein the opening exposes the interface between the semiconductor layer and the foreign substrate; and c) removing at least part of the semiconductor solid state material along the interface between the semiconductor layer and the foreign substrate. The removing step c) is preferably achieved by selective interfacial chemical etching. The semiconductor layer may be utilized as a substrate for fabrication of a wide variety of electronic and opto-electronic devices and integrated circuitry products.Type: ApplicationFiled: June 23, 2009Publication date: December 23, 2010Inventors: Yuh-Jen Cheng, Ming-Hua Lo, Hao-Chung Kuo
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Patent number: 7855108Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).Type: GrantFiled: February 26, 2010Date of Patent: December 21, 2010Assignee: Northrop Grumman Systems CorporationInventors: Narsingh B. Singh, Brian P. Wagner, David J. Knuteson, Michael E. Aumer, Andre Berghmans, Darren Thomson, David Kahler
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Publication number: 20100317164Abstract: The present invention is a method for fabricating a semiconductor device including the steps of: a first silicon nitride film having a refractive index of 2.2 or higher on a semiconductor layer made of a GaN- or InP-based semiconductor; forming, on the first silicon nitride film, a second silicon nitride film having a refractive index lower than that of the first silicon nitride; forming a source electrode and a drain electrode in areas in which the semiconductor layer is exposed; annealing the source electrode and the drain electrode in a state in which the first silicon nitride film and the second silicon nitride film are formed; and forming a gate electrode on the semiconductor layer between the source electrode and the drain electrode.Type: ApplicationFiled: August 20, 2010Publication date: December 16, 2010Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Tsutomu Komatani
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Patent number: 7851284Abstract: A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.Type: GrantFiled: October 30, 2007Date of Patent: December 14, 2010Assignee: Lockheed Martin CorporationInventors: An-Ping Zhang, James Kretchmer, Edmund Kaminsky, Jr.
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Publication number: 20100308375Abstract: According to one embodiment, a high electron mobility transistor (HEMT) comprises an insulator layer comprising a first group III-V intrinsic layer doped with a rare earth additive. The HEMT also comprises a second group III-V intrinsic layer formed over the insulator layer, and a group III-V semiconductor layer formed over the second group III-V intrinsic layer. In one embodiment, a method for fabricating a HEMT comprises forming a first group III-V intrinsic layer and doping the first group III-V intrinsic layer with a rare earth additive to produce an insulator layer. The method also comprises forming a second group III-V intrinsic layer over the insulator layer, and further forming a group III-V semiconductor layer over the second group III-V intrinsic layer. A two-dimensional electron gas (2DEG) is formed at a heterojunction interface of the group III-V semiconductor layer and the second group III-V intrinsic layer.Type: ApplicationFiled: June 8, 2009Publication date: December 9, 2010Applicant: INTERNATIONAL RECTIFIER CORPORATIONInventor: Ronald H. Birkhahn
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Patent number: 7847410Abstract: An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the first adhesion layer/diffusion barrier layer/second adhesion layer is located between the copper wire line and the group III-V semiconductor device, the adhesion between the diffusion barrier layer and other materials is improved. Therefore, the yield of the device is increased.Type: GrantFiled: November 22, 2005Date of Patent: December 7, 2010Assignee: National Chiao Tung UniversityInventors: Cheng-Shih Lee, Edward Yi Chang, Huang-Choung Chang
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Publication number: 20100301395Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.Type: ApplicationFiled: August 5, 2009Publication date: December 2, 2010Inventors: Dong Xu, Xiaoping Yang, Wendell Kong, Lee M. Mohnkern, Phillip M. Smith, Pane-chane Chao
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Patent number: 7842532Abstract: A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the side surfaces of the one or more convex portions of the first nitride semiconductor layer.Type: GrantFiled: October 29, 2009Date of Patent: November 30, 2010Assignee: Panasonic CorporationInventors: Toshiyuki Takizawa, Jun Shimizu, Tetsuzo Ueda
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Publication number: 20100295100Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.Type: ApplicationFiled: May 20, 2009Publication date: November 25, 2010Inventors: JENN HWA HUANG, Bruce M. Green
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Publication number: 20100295098Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: ApplicationFiled: June 24, 2010Publication date: November 25, 2010Applicant: Toyota Jidosha Kabushiki KaishaInventors: Masahiro SUGIMOTO, Tetsu KACHI, Yoshitaka NAKANO, Tsutomu UESUGI, Hiroyuki UEDA, Narumasa SOEJIMA
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Patent number: 7838907Abstract: In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.Type: GrantFiled: June 19, 2008Date of Patent: November 23, 2010Assignee: Renesas Electronics CorporationInventor: Masaki Shiraishi
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Patent number: 7838906Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.Type: GrantFiled: October 3, 2008Date of Patent: November 23, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Ken Sato, Nobuo Kaneko
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Publication number: 20100270591Abstract: Disclosed are high electron mobility transistors (HEMTs). In some embodiments, a HEMT includes a channel layer composed of a first compound semiconductor material and one or more barrier layers disposed on either one side or both sides of the channel layer and composed of a second compound semiconductor material.Type: ApplicationFiled: April 27, 2009Publication date: October 28, 2010Applicant: University of Seoul Industry Cooperation FoundationInventor: Doyeol AHN
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Patent number: 7821036Abstract: A semiconductor device (10) comprises a substrate (11), a semiconductor layer (12), an insulation film (13), a protective film (15), a source electrode (21), a drain electrode (22), a gate electrode (23). The semiconductor device (10) comprises a protective film (15) formed so as to cover at least an upper surface of the insulation film (13). This enables preventing aluminum contained in the source electrode (21) and the drain electrode (22) from reacting with material contained in the insulation film (13). Accordingly, the increase of the resistance of the electrode and the increase of current collapse are prevented. Accordingly, the semiconductor device (10) has a satisfactory electric performance characteristics.Type: GrantFiled: December 10, 2007Date of Patent: October 26, 2010Assignee: Sanken Electric Co., Ltd.Inventor: Toshihiro Ehara
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Publication number: 20100264462Abstract: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.Type: ApplicationFiled: April 21, 2010Publication date: October 21, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Walter Rieger, Markus Zundel
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Publication number: 20100264461Abstract: A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.Type: ApplicationFiled: September 18, 2006Publication date: October 21, 2010Inventors: Siddharth Rajan, Chang Soo Suh, James S. Speck, Umesh K. Mishra
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Publication number: 20100258843Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.Type: ApplicationFiled: April 8, 2010Publication date: October 14, 2010Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
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Publication number: 20100258846Abstract: The disclosure relates to electronic devices and associated methods of manufacture including materials of the Group III/N. An exemplary device successively includes, from its base towards its surface: (i) a support substrate, (ii) a layer adapted to contain an electron gas, (iii) a barrier layer, and (iv) a superficial layer extending on at least one part of the surface of the barrier layer, wherein the superficial layer has an electrical field of which the current is controlled so that, in at least one first region of the superficial layer, the electrical field is weaker than in a second region of the superficial layer.Type: ApplicationFiled: May 27, 2010Publication date: October 14, 2010Applicant: S.O.I.TEC Silicon on Insulator TechnologiesInventor: Hacéne Lahreche
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Patent number: 7811872Abstract: An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.Type: GrantFiled: May 8, 2008Date of Patent: October 12, 2010Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinichi Hoshi, Masanori Itoh, Hideyuki Okita, Toshiharu Marui
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Patent number: 7811907Abstract: A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.Type: GrantFiled: September 28, 2006Date of Patent: October 12, 2010Assignees: DENSO CORPORATION, Sumco CorporationInventors: Takumi Shibata, Shoichi Yamauchi, Tomonori Yamaoka, Syouji Nogami
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Publication number: 20100255646Abstract: III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure have different compositions, some of the layers act as etch stops to allow for precision etching. In some embodiments, a regrowth mask is used to prevent growth of material in the gate region. A gate electrode is deposited in the recess.Type: ApplicationFiled: June 16, 2010Publication date: October 7, 2010Applicant: Transphorm Inc.Inventors: Chang Soo Suh, Ilan Ben-Yaacov
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Patent number: 7807521Abstract: A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer formed on a substrate, an active layer formed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed on the active layer, an undoped GaN layer formed on the p-type nitride semiconductor layer, an AlGaN layer formed on the undoped GaN layer to form a two-dimensional electron gas (2DEG) layer at a bonding interface between the AlGaN layer and the undoped GaN layer, and an n-side electrode and a p-side electrode respectively formed on the n-type nitride semiconductor layer and the AlGaN layer to be connected to each other. As a hetero-junction structure of GaN/AlGaN is formed on the p-type nitride semiconductor layer, contact resistance between the p-type nitride semiconductor layer and the p-side electrode is enhanced by virtue of tunneling effect through the 2DEG layer.Type: GrantFiled: January 17, 2008Date of Patent: October 5, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae Hoon Lee, Jeong Tak Oh, Jin Sub Park
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Patent number: 7800132Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.Type: GrantFiled: October 25, 2007Date of Patent: September 21, 2010Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
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Patent number: 7795642Abstract: III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure have different compositions, some of the layers act as etch stops to allow for precision etching. In some embodiments, a regrowth mask is used to prevent growth of material in the gate region. A gate electrode is deposited in the recess.Type: GrantFiled: April 14, 2008Date of Patent: September 14, 2010Assignee: Transphorm, Inc.Inventors: Chang Soo Suh, Ilan Ben-Yaacov
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Publication number: 20100219452Abstract: A GaN HEMT structure having: a first III-N layer on GaN; a source electrode in contact with a first surface portion the first III-N layer disposed over a first region in the GaN layer; a drain electrode in contact with a second surface portion of the first III-N layer disposed over a second region in the GaN layer; a gate electrode disposed over a third surface portion of the first III-N layer, such third surface portion being disposed over a third region in the GaN layer. The GaN layer has: a fourth region therein disposed between the first region therein and the third region; and a fifth region therein disposed between the third region therein and the second region therein. A second III-N layer is disposed over the first III-N layer for generating a two-dimensional electron gas density in the GaN density in at least one of the fourth region and fifth region greater than the density in the third region of the GaN layer.Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Inventor: STEVEN K. BRIERLEY
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Patent number: 7786509Abstract: A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode.Type: GrantFiled: September 26, 2007Date of Patent: August 31, 2010Assignee: Hitachi Cable, Ltd.Inventors: Tomoyoshi Mishima, Toru Nakamura, Masataka Sato, Kazutaka Nomoto
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Publication number: 20100213512Abstract: A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolation (STI) regions are formed, wherein inner portions of the STI regions are directly over portions of the dislocation-blocking layer, and wherein inner sidewalls of the STI regions contact the dislocation-blocking layer. A second recess is formed by removing a portion of the dislocation-blocking layer between two of the inner sidewalls of the STI regions, with the two inner sidewalls facing each other. A semiconductor region is epitaxially grown in the second recess.Type: ApplicationFiled: November 13, 2009Publication date: August 26, 2010Inventor: Chih-Hsin Ko
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Publication number: 20100207124Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.Type: ApplicationFiled: May 3, 2010Publication date: August 19, 2010Applicants: FUJITSU LIMITED, HITACHI CABLE, LTD.Inventors: Kenji IMANISHI, Toshihide KIKKAWA, Takeshi TANAKA, Yoshihiko MORIYA, Yohei OTOKI
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Patent number: 7772055Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.Type: GrantFiled: February 4, 2009Date of Patent: August 10, 2010Assignee: IMECInventors: Marianne Germain, Joff Derluyn, Maarten Leys
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Publication number: 20100184262Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: ApplicationFiled: March 25, 2010Publication date: July 22, 2010Applicant: Northrop Grumman Space and Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7759700Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.Type: GrantFiled: November 6, 2006Date of Patent: July 20, 2010Assignee: Panasonic CorporationInventors: Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 7749828Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: GrantFiled: March 3, 2006Date of Patent: July 6, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
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Publication number: 20100163928Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.Type: ApplicationFiled: November 13, 2009Publication date: July 1, 2010Applicant: FUJITSU LIMITEDInventors: Tadahiro Imada, Atsushi Yamada
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Patent number: 7745272Abstract: A semiconductor device has a heterostructure including a first layer of semiconductor oxide material. A second layer of semiconductor oxide material is formed on the first layer of semiconductor oxide material such that a two dimensional electron gas builds up at an interface between the first and second materials. A passivation layer on the outer surface stabilizes the structure. The device also has a source contact and a drain contact.Type: GrantFiled: August 27, 2008Date of Patent: June 29, 2010Assignee: Palo Alto Research Center IncorporatedInventors: Christian G. Van de Walle, Kiesel Peter, Oliver Schmidt
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Patent number: 7737432Abstract: A computing element for use in a quantum computer has at least three coupled quantum dots, and at least one gate for applying an electric field to manipulate the state of said qubit.Type: GrantFiled: June 14, 2005Date of Patent: June 15, 2010Assignee: National Research Council of CanadaInventors: Pawel Hawrylak, Marek Korkusinski
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Publication number: 20100140664Abstract: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.Type: ApplicationFiled: January 12, 2010Publication date: June 10, 2010Inventors: Scott Sheppard, Richard Peter Smith
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Publication number: 20100140663Abstract: In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Inventors: Peter J. Hopper, William French
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Patent number: 7719031Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.Type: GrantFiled: July 6, 2004Date of Patent: May 18, 2010Assignee: Panasonic CorporationInventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
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Patent number: 7713803Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.Type: GrantFiled: March 29, 2007Date of Patent: May 11, 2010Assignee: Intel CorporationInventors: Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau
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Patent number: 7713802Abstract: This invention relates to a method of sulfuration treatment for InAlAs/InGaAs metamorphic high electron mobility transistor (MHEMT), and the sulfuration treatment is applied to the InAlAs/InGaAs MHEMT for a passivation treatment for Gate, in order to increase initial voltage, lower the surface states and decrease surface leakage current, which makes the MHEMT work in a range of high current density and high input power.Type: GrantFiled: March 12, 2007Date of Patent: May 11, 2010Assignee: Chang Gung UniversityInventors: Hsien-Chin Chiu, Liann-Be Chang, Yuan-Chang Huang, Chung-Wen Chen, Wei-Hsien Lee
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Patent number: 7714360Abstract: A high electron mobility transistor is disclosed which has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer. A source, drain, and gate overlie the electron supply layer. Also formed on the electron supply layer is a surface-stabilizing organic semiconductor overlay which is of p conductivity type in contrast to the n type of the electron supply layer.Type: GrantFiled: December 20, 2007Date of Patent: May 11, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Osamu Machida, Hitoshi Murofushi
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Patent number: 7713794Abstract: A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode.Type: GrantFiled: October 31, 2008Date of Patent: May 11, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Noriyuki Iwamuro
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Publication number: 20100102358Abstract: Disclosed herein is a pseudomorphic high electron mobility transistor (PHEMT) power device (1) including a semi-insulating substrate (2); an epitaxial substrate (3) formed on the semi-insulating substrate (2) a contact layer (19). The contact layer (19) includes a lightly doped contact layer (20) formed on the Schottky layer (18), and a highly doped contact layer (21) formed on the lightly doped contact layer (20) and having a doping concentration higher than the lightly doped contact layer (20). The PHEMT power device (1) further includes a—wide recess (23) formed to penetrate the highly doped contact layer (21) and a narrow recess (24) formed in the wide recess (23) to penetrate the lightly doped contact layer (20). The gate electrode (6) is formed in the narrow recess (24) and in Schottky contact with the Schottky layer (18).Type: ApplicationFiled: October 4, 2006Publication date: April 29, 2010Inventors: Claudio Lanzieri, Simone Lavanga, Marco Peroni, Antonio Cetronio
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Publication number: 20100102359Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).Type: ApplicationFiled: December 17, 2007Publication date: April 29, 2010Applicant: UNIVERSITY OF SOUTH CAROLINAInventors: M. Asif Khan, Vinod Adivarahan
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Publication number: 20100090251Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.Type: ApplicationFiled: November 20, 2007Publication date: April 15, 2010Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&DInventors: Anne Lorenz, Joff Derluyn, Joachim John
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Patent number: 7696533Abstract: The invention relates to a structure usable in electronic, optical or optoelectronic engineering which comprises a substantially crystalline layer made of an alloy consisting of at least one element of the column II of the periodic elements system and/or at least one element of the column IV of the periodic elements system and of N2 (said alloy being noted N-IV-N2), wherein said structure also comprises an InN layer. A method for producing an indium nitride layer, a substrate forming plate and the use thereof for indium nitride growth are also disclosed.Type: GrantFiled: September 14, 2005Date of Patent: April 13, 2010Assignees: Centre National de la Recherche Scientifique (CNRS), Universite Montpellier IIInventors: Bernard Gil, Olivier Gérard Serge Briot, Sandra Ruffenach, Bénédicte Maleyre, Thierry Joseph Roland Cloitre, Roger-Louis Aulombard
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Publication number: 20100084688Abstract: A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials.Type: ApplicationFiled: October 6, 2009Publication date: April 8, 2010Inventors: Bin Lu, Tomas Palacios