Electron Emitter Manufacture Patents (Class 438/20)
  • Patent number: 11063084
    Abstract: A method for manufacturing a light-emitting element comprises: forming a mask comprising a first film and a second film such that the mask covers a first active layer and a second nitride semiconductor layer, which comprises: forming the first film covering at least an upper surface of the second nitride semiconductor layer, and forming the second film covering the first film; while the first active layer and the second nitride semiconductor layer are covered with the mask, forming a third nitride semiconductor layer at an exposed portion of a first nitride semiconductor layer, wherein a temperature at which the third nitride semiconductor layer is formed is less than a melting point of the second film; and after the forming of the third nitride semiconductor layer, removing the mask, during which lift-off of the mask is performed by removing the first film, which also removes the second film.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: July 13, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Hirofumi Nishiyama, Seiichi Hayashi, Toshinori Wada
  • Patent number: 10998431
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Alexis Gauthier
  • Patent number: 10990948
    Abstract: Sever-based order persistence and/or fulfillment is described herein. In an example, server(s) associated with a payment processing service may receive, from a point-of-sale (POS) device associated with a merchant, an order associated with at least one item available for purchase from a physical location of the merchant. The server(s) may store the order in a storage data structure. In an example, the server(s) may determine an occurrence of a trigger event and may update a status of the order based at least in part on the trigger event. In some examples, the trigger event may correspond to an interruption in a connection with the POS device, fulfillment of the order, etc. The status of the order can indicate whether the order is to be sent to the POS device, removed from the storage data structure, etc.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 27, 2021
    Assignee: Square, Inc.
    Inventors: Christopher Woodyard, Brad Seiler, Roshan Jhunja, Noah Batterson
  • Patent number: 10818465
    Abstract: A method for making field emitter is provided. A carbon nanotube array and a cathode substrate are provided. A pressure is applied on the carbon nanotube array to make the carbon nanotubes of the carbon nanotube array toppled over and form a carbon nanotube paper. An adhesive tape is placed on the carbon nanotube paper, and then the adhesive tape is peeled off to make the carbon nanotube paper bonded to the adhesive tape. The cathode substrate is placed on the carbon nanotube paper; and then the cathode substrate is peeled off, at least part of the plurality of carbon nanotubes are bonded to the cathode substrate and perpendicular to the cathode substrate.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 27, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Guang Wang, Shou-Shan Fan
  • Patent number: 9991159
    Abstract: According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma Ito, Yasuhito Yoshimizu, Yuya Akeboshi, Hisashi Okuchi, Masayuki Kitamura
  • Patent number: 9754755
    Abstract: Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 5, 2017
    Assignee: ELWHA LLC
    Inventors: Max N. Mankin, Tony S. Pan
  • Patent number: 9443640
    Abstract: Provided is a process for producing a dispersion liquid of carbon nanotube aggregates in which the carbon nanotube aggregates are dispersed in a dispersion medium, comprising the two steps: (A) a step of adsorbing a dispersant to carbon nanotube aggregates by physical dispersion treatment in a dispersion medium to prepare a carbon nanotube paste with a particle size of 100 nm to 20 ?m resulting from partial dissociation of a mass of the carbon nanotube aggregates; and (B) a step of dispersing the carbon nanotube paste by ultrasonic dispersion treatment. A process for producing a dispersion liquid of carbon nanotube aggregates with reduced destruction and breakage of graphite structure of a carbon nanotube aggregate can be provided.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 13, 2016
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Kazunori Hondo, Hidekazu Nishino, Kenichi Sato
  • Patent number: 9337100
    Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: May 10, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Seung-Chul Song, Beom-Mo Han, Mohamed Hassan Abu-Rahma
  • Patent number: 9331028
    Abstract: Substrate material is oxidized around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with the result that the non-oxidized substrate material area between the channels forms a tapered shape with a pointed tip at the top. These pointed substrate areas are then used to form cathodes.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: May 3, 2016
    Assignee: NXP B.V.
    Inventors: Michael In 'T Zandt, Olaf Wunnicke, Klaus Reimann
  • Patent number: 9299757
    Abstract: A display device comprising one or more thin-film transistors (“TFTs”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode are formed on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate. A top surface of the first storage electrode may include hillocks and the gate insulating layer is formed between the first storage electrode and the second storage electrode to conform to the shape of the top surface of the first storage electrode with the hillocks.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Moo Soon Ko
  • Patent number: 9281187
    Abstract: The invention provides a method for manufacturing a nitride semiconductor device that grows a multilayer film of a III-V group nitride semiconductor in a reaction furnace into which a III group element raw material gas and a V group element raw material gas are introduced, the method including: growing a first nitride semiconductor layer at a first raw material gas flow rate of the V group element raw material gas and a first carrier gas flow rate; and growing a second nitride semiconductor layer at a second raw material gas flow rate of the V group element raw material gas lower than the first raw material gas flow rate and a second carrier gas flow rate higher than the first carrier gas flow rate, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are stacked.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 8, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ken Sato, Hirokazu Goto, Hiroshi Shikauchi, Keitaro Tsuchiya, Masaru Shinomiya, Kazunori Hagimoto
  • Patent number: 9275860
    Abstract: A method of manufacturing a junction electronic device having a 2-Dimensional (2D) material as a channel, includes forming a pattern portion by surface-treating a substrate so that the patterned portion has a higher surface potential than other portions of the substrate; bonding a 2D material to rthe patterned portion having the higher surface potential by spraying a liquid including 2D material flakes onto the substrate; forming a pair of first electrodes in contact with both ends of the 2D material disposed on the substrate; forming a dielectric layer on the first electrodes and the 2D material; and forming a second electrode on the dielectric layer. The 2D materials are disposed at desired positions by chemical exfoliation.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 1, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Jun Yu, Jin Soo Kim, Hong Kyw Choi, Jin Sik Choi, Jin Tae Kim, Kwang Hyo Chung, Doo Hyeb Youn, Choon Gi Choi
  • Patent number: 9202657
    Abstract: Disclosed is an encapsulated micro-diode and a method for producing same. The method comprises forming a plurality columns in the substrate with a respective tip disposed at a first end of the column, the tip defining a cathode of the diode; disposing a sacrificial oxide layer on the substrate, plurality of columns and respective tips; forming respective trenches in the sacrificial oxide layer around the columns; forming an opening in the sacrificial oxide layer to expose a portion of the tips; depositing a conductive material in of the opening and on a surface of the substrate to form an anode of the diode; and removing the sacrificial oxide layer.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: December 1, 2015
    Assignee: Sandia Corporation
    Inventors: Paul J. Resnick, Eric Langlois
  • Patent number: 9184016
    Abstract: A field emission cathode device includes a cathode electrode. An electron emitter is electrically connected to the cathode electrode, wherein the electron emitter includes a number of sub-electron emitters. An electron extracting electrode is spaced from the cathode electrode by a dielectric layer, wherein the electron extracting electrode defines a through-hole. The distances between an end of each of the sub-electron emitters away from the cathode electrode and a sidewall of the through-hole are substantially equal.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: November 10, 2015
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Peng Liu, Chun-Hai Zhang, Duan-Liang Zhou, Bing-Chu Du, Cai-Lin Guo, Pi-Jin Chen, Shou-Shan Fan
  • Patent number: 9067791
    Abstract: According to some embodiments, the present invention provides a system and method for supporting a carbon nanotube array that involve an entangled carbon nanotube mat integral with the array, where the mat is embedded in an embedding material. The embedding material may be depositable on a carbon nanotube. A depositable material may be metallic or nonmetallic. The embedding material may be an adhesive material. The adhesive material may optionally be mixed with a metal powder. The embedding material may be supported by a substrate or self-supportive. The embedding material may be conductive or nonconductive. The system and method provide superior mechanical and, when applicable, electrical, contact between the carbon nanotubes in the array and the embedding material. The optional use of a conductive material for the embedding material provides a mechanism useful for integration of carbon nanotube arrays into electronic devices.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: June 30, 2015
    Assignee: WILLIAM MARSH RICE UNIVERSITY
    Inventors: Myung Jong Kim, Nolan Walker Nicholas, W. Carter Kittrell, Howard K. Schmidt
  • Patent number: 9064669
    Abstract: A field emission cathode comprises at least one electron emitting parcel, and at least one ion absorbing parcel each being electrically connected with each of the at least one electron emitting parcel. The electron emitting parcel includes a first substrate and a nano emission component disposed on the first substrate for emitting electrons in an electric field. The ion absorbing parcel is constituted by a second substrate, in which the electric conductivity of the first substrate is less than that of the second substrate. A field emission light comprises the said field emission cathode, a field emission anode and a power supply. Thus the positive ions in an electric field can be absorbed by ion absorbing parcels to suppress an ion bombardment in the electric field. The efficiency of the electric field of the field emission is then maintained, and the lifetime of the field emission light is enhanced.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: June 23, 2015
    Assignee: NATIONAL DEFENSE UNIVERSITY
    Inventors: Yih-Ming Liu, Meng-Jey Youh, Nen-Wen Pu, Ming-Der Ger, Kevin Cheng, Kun-Ju Chung, Jhih-Cheng Jiang, Guan-Fang Xu
  • Patent number: 9039411
    Abstract: A disclosed thermal treatment apparatus includes a supporting member where plural substrates are supported in the form of shelves; a reaction tube that accommodates the supporting member within the reaction tube, and is provided with plural gas supplying pipes arranged in a side part of the reaction tube, thereby allowing a gas to flow into the reaction tube through the plural gas supplying pipes; and a first heating part that heats the plural substrates supported by the supporting member accommodated within the reaction tube, wherein the first heating part includes a slit that extends from a bottom end to a top end of the first heating part and allows the plural gas supplying pipes to go therethrough, and wherein an entire inner surface, except for the slit, of the heating part faces the side part of the reaction tube.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 26, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kadobe, Naomi Onodera, Kazuhiko Kato
  • Patent number: 9023681
    Abstract: The present invention discloses a method of fabricating a heterojunction battery, comprising the steps of: depositing a first amorphous silicon intrinsic layer on the front of an n-type silicon wafer, wherein the n-type silicon wafer may be a monocrystal or polycrystal silicon wafer; depositing an amorphous silicon p layer on the first amorphous silicon intrinsic layer; depositing a first boron doped zinc oxide thin film on the amorphous silicon p layer; forming a back electrode and an Al-back surface field on the back of the n-type silicon wafer; and forming a positive electrode on the front of the silicon wafer. In addition, the present invention further discloses a method of fabricating a double-sided heterojunction battery. In the present invention, the boron doped zinc oxide is used as an anti-reflection film in place of an ITO thin film; due to the special nature, especially the light trapping effect of the boron doped zinc oxide, the boron doped zinc oxide can achieve good anti-reflection.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Chint Solar (Zhejiang) Co., Ltd.
    Inventors: Xinwei Niu, Cao Yu, Lan Ding, Junmei Rong, Shiyong Liu, Minghua Wang, Jinyan Hu, Weizhi Han, Yongmin Zhu, Hua Zhang, Tao Feng, Jianbo Jin, Zhanwei Qiu, Liyou Yang
  • Patent number: 8981338
    Abstract: A semiconductor photocathode includes an AlXGa1-XN layer (0?X<1) bonded to a glass substrate via an SiO2 layer and an alkali-metal-containing layer formed on the AlXGa1-XN layer. The AlXGa1-XN layer includes a first region, a second region, an intermediate region between the first and second regions. The second region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately, the intermediate region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately. When a pair of adjacent barrier and well layers is defined as a unit section, an average value of a composition ratio X of Al in a unit section decreases monotonously with distance from an interface position between the second region and the SiO2 layer at least in the intermediate region.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: March 17, 2015
    Assignees: Sanken Electric Co., Ltd., Hamamatsu Photonics K.K.
    Inventors: Shunro Fuke, Tetsuji Matsuo, Yoshihiro Ishigami, Tokuaki Nihashi
  • Publication number: 20150060758
    Abstract: A field emission device may comprise: an emitter comprising a cathode electrode and an electron emission source supported by the cathode electrode; an insulating spacer around the emitter, the insulating spacer forming an opening that is a path of electrons emitted from the electron emission source; and/or a gate electrode around the opening. The electron emission source may comprise a plurality of graphene thin films vertically supported in the cathode electrode toward the opening.
    Type: Application
    Filed: September 1, 2014
    Publication date: March 5, 2015
    Applicant: Kumoh National Institute of Technology - Academic Cooperation Foundation
    Inventors: Donggu LEE, Shanghyeun PARK, Yongchul KIM, Ilhwan KIM, Taewon JEONG
  • Publication number: 20150060757
    Abstract: A field emission device may comprise: an emitter comprising a cathode electrode and an electron emission source supported by the cathode electrode; an insulating spacer around the emitter, the insulating spacer forming an opening that is a path of electrons emitted from the electron emission source; and/or a gate electrode comprising a graphene sheet covering the opening. A method of manufacturing a gate electrode may comprise: forming a graphene thin film on one surface of a conductive film; forming a mask layer having an etching opening on another surface of the conductive film, wherein the etching opening exposes a portion of the conductive film; partially removing the conductive film through the etching opening to partially expose the graphene thin film; and/or removing the mask layer.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Applicant: KUMOH NATIONAL INSTITUTE OF TECHNOLOGY
    Inventors: Dong-gu LEE, Shang-hyeun PARK, Yong-chul KIM, Chang-soo LEE, Do-yoon KIM
  • Patent number: 8969848
    Abstract: A field emission device is configured as a heat engine. Different embodiments of the heat engine may have different configurations that may include a cathode, gate, suppressor, and anode arranged in different ways according to a particular embodiment. Different embodiments of the heat engine may also incorporate different materials in and/or proximate to the cathode, gate, suppressor, and anode.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: March 3, 2015
    Inventors: Jesse R. Cheatham, III, Philip Andrew Eckhoff, William Gates, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Nathan P. Myhrvold, Tony S. Pan, Robert C. Petroski, Clarence T. Tegreene, David B. Tuckerman, Charles Whitmer, Lowell L. Wood, Jr., Victoria Y. H. Wood
  • Patent number: 8916394
    Abstract: A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: December 23, 2014
    Assignee: California Institute of Technology
    Inventors: Risaku Toda, Michael J. Bronikowski, Edward M. Luong, Harish Manohara
  • Patent number: 8912526
    Abstract: An electron multiplier for a system for detecting electromagnetic radiation or an ion flow is disclosed. The multiplier includes at least one active structure intended to receive a flow of incident electrons, and to emit in response a flow of electrons called secondary electrons. The active structure includes a substrate on which is positioned a thin nanodiamond layer formed from diamond particles the average size of which is less than or equal to about 100 nm.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: December 16, 2014
    Assignee: Photonis France
    Inventors: Gert Nutzel, Pascal Lavoute, Richard B. Jackman
  • Patent number: 8900890
    Abstract: Techniques are disclosed for improving the quantum efficiency of photocathode devices. The techniques allow for an increase in the optical thickness of the photocathode device, while simultaneously allowing for an increase in the probability of electron escape into the vacuum of the device. The techniques are particularly useful in detector and imaging. In one embodiment, a photocathode device is provided that has an array of corner cubes fabricated in a surface of the photocathode. The corner cube array is made of the same material as the photocathode layer. The device may be, for example, a detector or image intensifier that operates in the UV, visible, and IR light spectrums, and may further include a gain medium, anode, and readout device. Techniques for forming the device are also provided.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: December 2, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Michael E. DeFlumere, Paul W. Schoeck
  • Patent number: 8878161
    Abstract: A strain-balanced quantum well tunnel junction (SB-QWTJ) device. QW structures are formed from alternating quantum well and barrier layers situated between n++ and p++ layers in a tunnel junction formed on a substrate. The quantum well layers exhibit a compressive strain with respect to the substrate, while the barrier layers exhibit a tensile strain. The composition and layer thicknesses of the quantum well and barrier layers are configured so that the compressive and tensile strains in the structure are balanced.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 4, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew Lumb, Michael K. Yakes, María González, Christopher Bailey, Robert J. Walters
  • Patent number: 8877526
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting part. The first semiconductor layer includes an n-type semiconductor layer. The second semiconductor layer includes a p-type semiconductor layer. The light emitting part is provided between the first semiconductor layer and the second semiconductor layer, and includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers. The first semiconductor layer has a first irregularity and a second irregularity. The first irregularity is provided on a first major surface of the first semiconductor layer on an opposite side to the light emitting part. The second irregularity is provided on a bottom face and a top face of the first irregularity, and has a level difference smaller than a level difference between the bottom face and the top face.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ono, Toshiki Hikosaka, Tomoko Morioka, Toshiyuki Oka, Shinya Nunoue
  • Publication number: 20140264256
    Abstract: According to one embodiment, a product includes an array of three dimensional structures, where each of the three dimensional structure includes a semiconductor material; a cavity region between each of the three dimensional structures; and a first material in contact with at least one surface of each of the three dimensional structures, where the first material is configured to provide high energy particle and/or ray emissions.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Lawrence Livermore National Security, LLC
    Inventors: Rebecca J. Nikolic, Adam P. Conway, Roger A. Henderson, Victor P. Karpenko, Qinghui Shao, Dawn A. Shaughnessy, Mark A. Stoyer, Lars F. Voss
  • Patent number: 8835902
    Abstract: A nano-structured light-emitting device (LED) includes: a plurality of nanostructures on a first type semiconductor layer. Each of the plurality of nanostructures includes: a first type semiconductor nanocore on a portion of the first type semiconductor layer; a current spreading layer formed to cover a surface of the first type semiconductor nanocore and formed of an AlxGa1-xN(0<x<1)/GaN superlattice structure; an active layer on the current spreading layer (or on the first type semiconductor nanocore if the current spreading layer is embedded in the first type semiconductor nanocore); and a second type semiconductor layer on the active layer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Kim, Taek Kim
  • Publication number: 20140158179
    Abstract: In a method of manufacturing an electrode of a thermionic converter, a carbide layer is formed on a base material by a vapor synthesis, an N-type diamond layer doped with a donor impurity is formed on the carbide layer by a vapor synthesis, and a surface of the N-type diamond layer is terminated with hydrogen. The base material is made of a metal, and the carbide layer is made of a metal carbide.
    Type: Application
    Filed: November 27, 2013
    Publication date: June 12, 2014
    Applicant: DENSO CORPORATION
    Inventors: Mitsuhiro KATAOKA, Yuji KIMURA, Susumu SOBUE
  • Patent number: 8727827
    Abstract: A method for making field emission electron source comprises following steps. An insulating layer is coated on outer surface of a linear carbon nanotube structure. A field emission electron source preform is formed by locating a plurality of conductive ring on outer surface of the insulating layer, wherein the plurality of conductive ring is space from each other, and each conductive ring comprises a first ring face and a second ring face opposite to the first ring face. A plurality of field emission electron source is formed by cutting off the plurality of conductive ring, the insulating layer, and the linear carbon nanotube structure, wherein each field emission electron source comprises at least one conductive ring, and a ring face of the conductive ring, end surface of the insulating layer, and end surface of the linear carbon nanotube structure are coplanar.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 20, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Cai-Lin Guo, Jie Tang, Peng Liu, Shou-Shan Fan
  • Patent number: 8708795
    Abstract: Systems and methods for facilitating one or more base wagering games in an extended format are provided. Outcomes for the base wagering game may be determined, and based on the outcomes, player rankings in the extended play wagering game may be determined.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: April 29, 2014
    Assignee: GTECH Corporation
    Inventor: Thomas J. Napolitano
  • Publication number: 20140110661
    Abstract: The present invention provides for a structure comprising a plurality of emitters, wherein a first nozzle of a first emitter and a second nozzle of a second emitter emit in two directions that are not or essentially not in the same direction; wherein the walls of the nozzles and the emitters form a monolithic whole. The present invention also provides for a structure comprising an emitter with a sharpened end from which the emitter emits; wherein the emitters forms a monolithic whole. The present invention also provides for a fully integrated separation of proteins and small molecules on a silicon chip before the electrospray mass spectrometry analysis.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Daojing Wang, Pan Mao, Hung-Ta Wang, Peidong Yang
  • Patent number: 8692226
    Abstract: A field emission device is configured as a heat engine. Different embodiments of the heat engine may have different configurations that may include a cathode, gate, suppressor, and anode arranged in different ways according to a particular embodiment. Different embodiments of the heat engine may also incorporate different materials in and/or proximate to the cathode, gate, suppressor, and anode.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: April 8, 2014
    Inventors: Jesse R. Cheatham, III, Philip Andrew Eckhoff, William Gates, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Nathan P. Myhrvold, Tony S. Pan, Robert C. Petroski, Clarence T. Tegreene, David B. Tuckerman, Charles Whitmer, Lowell L. Wood, Jr., Victoria Y. H. Wood
  • Publication number: 20140090684
    Abstract: Techniques are provided for enhancing electrical properties of semiconductor structures. At a semiconductor structure, a heterojunction interface is provided between two dissimilar materials such that a two-dimensional electron gas (2DEG) region is present in the vicinity of the heterojunction. Energy is added to the semiconductor structure such that electrons that are present in the 2DEG region are promoted from below the Fermi level to energy states sufficiently high that the electrons can escape the structure. Electrons are emitted from the semiconductor structure in response to adding the energy such that electrons escape the surface of the semiconductor structure.
    Type: Application
    Filed: September 24, 2013
    Publication date: April 3, 2014
    Inventor: Joshua R. Smith
  • Patent number: 8686399
    Abstract: Disclosed are a growth substrate and a light emitting device. The light emitting device includes a silicon substrate, a first buffer layer disposed on the silicon substrate and having an exposing portions of the silicon substrate, a second buffer layer covering the first buffer layer and the exposed portions of the silicon substrate, wherein the second buffer layer is formed of a material causing a eutectic reaction with the silicon substrate, a third buffer layer disposed on the second buffer layer, and a light emitting structure disposed on the third buffer layer, and the second buffer layer includes voids.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: April 1, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jeong Sik Lee
  • Patent number: 8680511
    Abstract: A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Damon B. Farmer, Alfred Grill, Yu-Ming Lin, Deborah A. Neumayer, Dirk Pfeiffer, Wenjuan Zhu
  • Patent number: 8669545
    Abstract: A light emitting device includes an active layer including a quantum barrier and a quantum well, a first conductive type semiconductor layer disposed at one side of the active layer, and a second conductive type semiconductor layer disposed at the other side of the active layer, wherein the first conductive type semiconductor layer or the second conductive type semiconductor layer includes a main barrier layer, and the main barrier layer includes a plurality of sub barrier layers and a basal layer disposed between the plurality of sub barrier layers. The plurality of sub barrier layers includes a first section in which energy band gaps of the plurality of sub barrier layers are increased and a second section in which energy band gaps of the plurality of sub barrier layers are decreased.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yong Seon Song, Yong Tae Moon
  • Patent number: 8664641
    Abstract: Disclosed herein is a nano device, including: a carbon layer including one-layered graphene having a honeycombed planar structure in which carbon atoms are connected with each other and two or more-layered monocrystalline graphite; and one or more vertically-grown nanostructures formed on the carbon layer. This nano device can be used to manufacture an integrated circuit in which various devices including a graphene electronic device and a photonic device are connected with each other, and is a high-purity and high-quality nano device having a small amount of impurities because a metal catalyst is not used.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: March 4, 2014
    Assignee: SNU R&DB Foundation
    Inventors: Gyu-chul Yi, Yong-Jin Kim
  • Publication number: 20140034813
    Abstract: Techniques are disclosed for improving the quantum efficiency of photocathode devices. The techniques allow for an increase in the optical thickness of the photocathode device, while simultaneously allowing for an increase in the probability of electron escape into the vacuum of the device. The techniques are particularly useful in detector and imaging. In one embodiment, a photocathode device is provided that has an array of corner cubes fabricated in a surface of the photocathode. The corner cube array is made of the same material as the photocathode layer. The device may be, for example, a detector or image intensifier that operates in the UV, visible, and IR light spectrums, and may further include a gain medium, anode, and readout device. Techniques for forming the device are also provided.
    Type: Application
    Filed: October 4, 2013
    Publication date: February 6, 2014
    Applicant: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Michael E. DeFlumere, Paul W. Schoeck
  • Patent number: 8642995
    Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 4, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8633468
    Abstract: A solution for reducing a number of dislocations in an active region of an emitting device is provided. A dislocation bending structure can be included in the emitting device between the substrate and the active region. The dislocation bending structure can be configured to cause dislocations to bend and/or annihilate prior to reaching the active region, e.g., due to the presence of a sufficient amount of strain. The dislocation bending structure can include a plurality of layers with adjacent layers being composed of a material, but with molar fractions of an element in the respective material differing between the two layers. The dislocation bending structure can include at least forty pairs of adjacent layers having molar fractions of an element differing by at least five percent between the adjacent layers.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 21, 2014
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Jinwei Yang, Michael Shur
  • Patent number: 8624221
    Abstract: A light emitting device is provided. The light emitting device comprises an active layer comprising a plurality of well layers and a plurality of barrier layers. The bather layers comprise a first barrier layer having a first band gap which is the nearest to the second conductive type semiconductor layer, a second barrier layer adjacent to the first barrier, and a third barrier layer between the second bather layer and the first conductive type semiconductor layer. The well layers comprise a first well layer having a third band gap different from the first band gap between the first and second bather layers, and a second well layer between the second barrier layer and the third barrier layer, the second well layer having a second band gap. The first well layer has a thickness thinner than that of the second well layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 7, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jong Hak Won
  • Patent number: 8610107
    Abstract: A light emitting device is provided. The light emitting device comprises an active layer comprising a plurality of well layers and barrier layers. The barrier layers comprise a first barrier layer which is the nearest to a second conductive type semiconductor layer and has a first band gap, a second barrier layer having a third band gap, and a third barrier layer having the first band gap between the second barrier layer and a first conductive type semiconductor layer. The well layers comprise a first well layer having a second band gap between the first and the second barrier layers, and a second well layer between the second barrier layer and the third barrier layer. The second barrier layer is disposed between the first and the second well layers, and the third band gap is narrower than the first band gap and wider than the second band gap.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 17, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jong Hak Won
  • Publication number: 20130320295
    Abstract: A vacuum encapsulated, hermetically sealed cathode capsule for generating an electron beam of secondary electrons, which generally includes a cathode element having a primary emission surface adapted to emit primary electrons, an annular insulating spacer, a diamond window element comprising a diamond material and having a secondary emission surface adapted to emit secondary electrons in response to primary electrons impinging on the diamond window element, a first high-temperature solder weld disposed between the diamond window element and the annular insulating spacer and a second high-temperature solder weld disposed between the annular insulating spacer and the cathode element.
    Type: Application
    Filed: May 17, 2013
    Publication date: December 5, 2013
    Applicant: Brookhaven Science Associates, LLC
    Inventors: Triveni Rao, John Walsh, Elizabeth Gangone
  • Publication number: 20130299773
    Abstract: An electronic device including a first conducting layer, a second conducting layer, and an insulating layer provided between the conducting layers. At least one side wall extends from the first conducting layer to the second conducting layer and includes at least a portion of the first conducting layer, the second conducting layer and the insulating layer. A bias voltage is applied between the first and second conducting layers, wherein responsive to the bias voltage, a two dimensional electron system is induced at least in one of the first conducting layer and the second conducting layer, and wherein electrons from the two dimensional electron system are emitted from the side wall side wall as a result of Coulombic repulsion and travel in air from the one of the first conducting layer and the second conducting layer to the other of the first conducting layer and the second conducting layer.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 14, 2013
    Applicant: UNIVERSITY OF PITTSBURGH - OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
    Inventor: UNIVERSITY OF PITTSBURGH - OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
  • Patent number: 8574942
    Abstract: A method of preparing a silicon nanowire and a method of fabricating a lithium secondary battery including the silicon nanowire are provided. The method of preparing a silicon nanowire may include forming a catalyst layer including metal particles separated from one another on a silicon layer, selectively etching the silicon layer contacting the metal particles, and removing the metal particles.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 5, 2013
    Assignee: Unist Academy-Industry Research Corporation
    Inventors: Soojin Park, Byoungman Bang, Jung-Pil Lee, Hyun-Kon Song, Jaephil Cho
  • Publication number: 20130280830
    Abstract: A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 24, 2013
    Inventors: Risaku TODA, Michael J. BRONIKOWSKI, Edward M. LUONG, Harish MANOHARA
  • Publication number: 20130248815
    Abstract: A semiconductor photocathode includes an AlXGa1-XN layer (0?X<1) bonded to a glass substrate via an SiO2 layer and an alkali-metal-containing layer formed on the AlXGa1-XN layer. The AlXGa1-XN layer includes a first region, a second region, an intermediate region between the first and second regions. The second region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately, the intermediate region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately. When a pair of adjacent barrier and well layers is defined as a unit section, an average value of a composition ratio X of Al in a unit section decreases monotonously with distance from an interface position between the second region and the SiO2 layer at least in the intermediate region.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicants: HAMAMATSU PHOTONICS K.K., SANKEN ELECTRIC CO., LTD.
    Inventors: Shunro FUKE, Tetsuji MATSUO, Yoshihiro ISHIGAMI, Tokuaki NIHASHI
  • Publication number: 20130214244
    Abstract: Devices and methods are described for a cathode having a plurality of apertures in an insulating layer, pits in a substrate layer, and emitters in the pit. The device can also have gate layer on top of the insulating layer which has an opening that is substantially aligned with the pit and the aperture. The emitter can be an array of substantially aligned carbon nanotubes. The device and method produces cathodes that are designed to avoid shorting of the cathode due to emitter-gate contact and other fabrication challenges.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 22, 2013
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventor: GEORGIA TECH RESEARCH CORPORATION