Electron Emitter Manufacture Patents (Class 438/20)
  • Publication number: 20130248815
    Abstract: A semiconductor photocathode includes an AlXGa1-XN layer (0?X<1) bonded to a glass substrate via an SiO2 layer and an alkali-metal-containing layer formed on the AlXGa1-XN layer. The AlXGa1-XN layer includes a first region, a second region, an intermediate region between the first and second regions. The second region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately, the intermediate region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately. When a pair of adjacent barrier and well layers is defined as a unit section, an average value of a composition ratio X of Al in a unit section decreases monotonously with distance from an interface position between the second region and the SiO2 layer at least in the intermediate region.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicants: HAMAMATSU PHOTONICS K.K., SANKEN ELECTRIC CO., LTD.
    Inventors: Shunro FUKE, Tetsuji MATSUO, Yoshihiro ISHIGAMI, Tokuaki NIHASHI
  • Publication number: 20130214244
    Abstract: Devices and methods are described for a cathode having a plurality of apertures in an insulating layer, pits in a substrate layer, and emitters in the pit. The device can also have gate layer on top of the insulating layer which has an opening that is substantially aligned with the pit and the aperture. The emitter can be an array of substantially aligned carbon nanotubes. The device and method produces cathodes that are designed to avoid shorting of the cathode due to emitter-gate contact and other fabrication challenges.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 22, 2013
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventor: GEORGIA TECH RESEARCH CORPORATION
  • Patent number: 8513644
    Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 20, 2013
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Asaf Albo, Gad Bahir, Dan Fekete
  • Patent number: 8507890
    Abstract: An infrared photoconversion device comprising a collector with at least an active layer made of a single sheet of doped single-layer, bilayer, or multilayer graphene patterned as nanodisks or nanoribbons. The single sheet of doped graphene presents high absorbance and thus, the efficiency of devices such as photovoltaic cells, photodetectors, and light emission devices can be improved by using graphene as the central absorbing or emitting element. These devices become tunable because their peak absorption or emission wavelength is changed via electrostatic doping of the graphene.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: August 13, 2013
    Assignees: Fundacio Institut de Ciencies Fotoniques, Consejo Superior de Investigaciones Cientificas
    Inventors: Frank Koppens, Francisco Javier GarcĂ­a de Abajo
  • Patent number: 8497493
    Abstract: Disclosed are a growth substrate and a light emitting device. The light emitting device includes a silicon substrate, a first buffer layer disposed on the silicon substrate and having an exposing portions of the silicon substrate, a second buffer layer covering the first buffer layer and the exposed portions of the silicon substrate, wherein the second buffer layer is formed of a material causing a eutectic reaction with the silicon substrate, a third buffer layer disposed on the second buffer layer, and a light emitting structure disposed on the third buffer layer, and the second buffer layer includes voids.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 30, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jeong Sik Lee
  • Patent number: 8492744
    Abstract: Preferred embodiments of the invention provide semiconducting microcavity plasma devices. Preferred embodiments of the invention are microcavity plasma devices having at least two pn junctions, separated by a microcavity or microchannel and powered by alternate half-cycles of a time-varying voltage waveform. Alternate embodiments have a single pn junction. Microplasma is produced throughout the cavity between single or multiple pn junctions and a dielectric layer isolates the microplasma from the single or multiple pn junctions. Additional preferred embodiments are devices in which the spatial extent of the plasma itself or the n or p regions associated with a pn junction are altered by a third (control) electrode.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: July 23, 2013
    Assignees: The Board of Trustees of the University of Illinois, Acumen Scientific
    Inventors: J. Gary Eden, Paul Tchertchian, Clark J. Wagner, Steve Solomon, Robert Ginn
  • Patent number: 8481347
    Abstract: Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: July 9, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jonghyurk Park, Seung Youl Kang
  • Patent number: 8476090
    Abstract: A circuit board for a light emitting diode package improved in heat radiation efficiency and a manufacturing method thereof. In a simple manufacturing process, insulating layers are formed by anodizing on a portion of a thermally conductive board body and plated with a conductive material. In the light emitting diode package, a board body is made of a thermally conductive metal. Insulating oxidation layers are formed at a pair of opposing edges of the board body. First conductive patterns are formed on the insulating oxidation layers, respectively. Also, second conductive patterns are formed in contact with the board body at a predetermined distance from the first conductive patterns, respectively. The light emitting diode package ensures heat generated from the light emitting diode to radiate faster and more effectively. Additionally, the insulating layers are formed integral with the board body by anodizing, thus enhancing productivity and durance.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hyun Shin, Seog Moon Choi, Young Ki Lee
  • Patent number: 8471243
    Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 25, 2013
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8445934
    Abstract: An organic light emitting diode (OLED) display includes a display substrate including an organic light emitting element, an encapsulation substrate arranged opposite to the display substrate and covering the organic light emitting element, a sealant disposed on the edge of the display substrate and the encapsulation substrate, and sealing the display substrate and the encapsulation substrate to each other; and a filler filling the space between the display substrate and the encapsulation substrate. One surface of at least one of the display substrate and the encapsulation substrate is contacted with the filler and is divided into a hydrophobic region and a hydrophilic region, and the hydrophobic region is positioned between the hydrophilic region and the sealant.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 21, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyung-Jun Lee
  • Patent number: 8436332
    Abstract: An electron emission element has an electron emission layer that emits an electron from a surface emission portion, a focusing electrode layer that is film-formed on a surface of the electron emission layer via a first insulation layer and focuses the emitted electron, a gate electrode layer that is film-formed on a surface of the focusing electrode layer via a second insulation layer, an emission concave portion that penetrates the gate electrode layer, the second insulation layer, the focusing electrode layer and the first insulation layer and opens in a concave shape on a surface of the surface emission portion, a carbon layer that is film-formed from a surface of the gate electrode layer over an inner peripheral surface of the emission concave portion, and a partial insulation portion that insulates the focusing electrode layer from the carbon layer.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 7, 2013
    Assignees: Pioneer Corporation, Pioneer Micro Technology Corporation
    Inventor: Masaki Yoshinari
  • Patent number: 8436334
    Abstract: A multiple quantum well (MQW) structure for a light emitting diode and a method for fabricating a MQW structure for a light emitting diode are provided. The MQW structure comprises a plurality of quantum well structures, each quantum well structure comprising: a barrier layer; and a well layer having quantum dot nanostructures embedded therein formed on the barrier layer, the barrier and the well layer comprising a first metal-nitride based material; wherein at least one of the quantum well structures further comprises a capping layer formed on the well layer, the capping layer comprising a second metal-nitride based material having a different metal element compared to the first metal-nitride based material.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: May 7, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Chew Beng Soh, Soo Jin Chua, Wei Liu, Jing Hua Teng
  • Patent number: 8405189
    Abstract: An example of a carbon nanotube capacitor may include (i) a carbon nanotube film having carbon nanotubes and voids with dielectric material, (ii) conductive contacts and (iii) a dielectric layer. The carbon nanotube film may switch from a conductive state to a non-conductive state when a voltage is applied by creating an electrical break within the carbon nanotube film and providing a first conductive region and a second conductive region within the carbon nanotube film. The electrical break may separate the first conductive region from the second conductive region. The first and second conductive regions may store charge. An integrated device may include one or more transistors and one or more carbon nanotube capacitors. A method of making a carbon nanotube capacitor is also disclosed.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jonathan W. Ward, Quoc X. Ngo
  • Patent number: 8394651
    Abstract: The present invention is generally directed to a method of suppressing the Auger rate in confined structures, comprising replacing an abrupt confinement potential with either a smooth confinement potential or a confinement potential of a certain size found by increasing the confinement potential width until the Auger recombination rate undergoes strong oscillations and establishes a periodic minima. In addition, the present invention provides for the design of structures with high quantum efficiency.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 12, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Alexander L. Efros, George E. Cragg
  • Patent number: 8388431
    Abstract: A gaming machine of the present invention includes slot machines each of which repeatably runs, independently of the other slot machines, a unit game which scroll displays a base game symbol column image and stops the scroll-display to rearrange base game symbols. In response to a common game start command from a center controller, each slot machine runs, in sync with other slot machines, a common game which executes a common scrolling process in which a common game symbol column image which is different from the base game symbol column image is scroll displayed, and then stopped to rearrange common game symbols.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 5, 2013
    Assignees: Universal Entertainment Corporation, Aruze Gaming America, Inc.
    Inventor: Yoichi Kato
  • Publication number: 20120327326
    Abstract: A field emission panel includes a cathode electrode which is formed on a substrate, a multilayered carbon nano tube which is formed on the cathode electrode, and a gate electrode which is positioned at a distance from the multilayered carbon nano tube. The multilayered carbon nano tube has a minimum thermal decomposition temperature higher than a temperature of a heating process which is performed when the field emission panel is manufactured, and has three peaks of Raman scattered light in a Raman intensity distribution characteristic.
    Type: Application
    Filed: December 23, 2011
    Publication date: December 27, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kwang-jong SUH, Jae-sang HA
  • Publication number: 20120314367
    Abstract: An apparatus for cooling a semiconductor element is provided. The apparatus can include an electron emitter configured to emit electrons such that at least some of the emitted electrons become attached to air particulates and an air accelerator configured to generate an electric field that accelerates the air particulates toward the air accelerator to create an air flow over at least a portion of the semiconductor element. The air flow carries heat away from the at least a portion of the semiconductor element.
    Type: Application
    Filed: June 13, 2011
    Publication date: December 13, 2012
    Applicant: Broadcom Corporation
    Inventors: Sam Ziqun ZHAO, Milind S. BHAGAVAT
  • Patent number: 8330178
    Abstract: A light emitted diode (LED) package structure and an LED package process are provided. The LED package structure comprises a carrier, a spacer, at least one LED chip, a junction coating, a plurality of phosphor particles, and an encapsulant. The spacer is disposed on the carrier and provided with a reflective layer covering a top surface of the spacer. The LED chip is disposed on the reflective layer and electrically connected to the carrier. The junction coating is disposed over the spacer and covers the LED chip. The phosphor particles are distributed within the junction coating. The encapsulant is disposed on the carrier and encapsulates the LED chip, the spacer and the junction coating. Uniform light output and high illuminating efficiency can be obtained by the phosphor particles uniformly distributed in the junction coating. The junction coating is formed by package level dispensing process to reduce the fabrication cost.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: December 11, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hyunsoo Jeong, Seongoo Lee, Ryungshik Park, Hyunil Lee
  • Publication number: 20120301981
    Abstract: The present invention is directed to a method for the fabrication of electron field emitter devices, including carbon nanotube (CNT) field emission devices. The method of the present invention involves depositing one or more electrically conductive thin-film layers onto a electrically conductive substrate and performing lithography and etching on these thin film layers to pattern them into the desired shapes. The top-most layer may be of a material type that acts as a catalyst for the growth of single- or multiple-walled carbon nanotubes (CNTs). Subsequently, the substrate is etched to form a high-aspect ratio post or pillar structure onto which the previously patterned thin film layers are positioned. Carbon nanotubes may be grown on the catalyst material layer. The present invention also described methods by which the individual field emission devices may be singulated into individual die from a substrate.
    Type: Application
    Filed: May 23, 2011
    Publication date: November 29, 2012
    Inventors: Mehmet OZGUR, Paul SUNAL, Lance OH, Michael HUFF, Michael PEDERSEN
  • Publication number: 20120292590
    Abstract: An optical component comprising an emitter and a solid reflector, said reflector having a convex outer surface, said emitter being located within the solid reflector, the emitter being configured to emit radiation via an electric dipole transition, the dipole having a dipole axis being orientated at an angle of 45 degrees or less to the surface normal at the apex of the reflector.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Anthony John BENNETT, Andrew James SHIELDS, Joanna Krystyna SKIBA-SZYMANSKA
  • Patent number: 8314539
    Abstract: A field electron emitter includes a thin film layer including a carbon nanotube (“CNT”) disposed on a substrate, wherein the thin film layer includes nucleic acid.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: November 20, 2012
    Assignees: Samsung Electronics Co., Ltd., Korea University Industrial & Academic Collaboration Foundation
    Inventors: Yoon-chul Son, Yong-chul Kim, Jeong-na Heo, Byeong-kwon Ju
  • Patent number: 8293628
    Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 23, 2012
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Asaf Albo, Gad Bahir, Dan Fekete
  • Patent number: 8268646
    Abstract: A layered group III-nitride article includes a single crystal silicon substrate, and a highly textured group III-nitride layer, such as GaN, disposed on the silicon substrate. The highly textured group III-nitride layer is crack free and has a thickness of at least 10 ?m. A method for forming highly textured group III-nitride layers includes the steps of providing a single crystal silicon comprising substrate, depositing a nanostructured InxGa1-xN (1?x?0) interlayer on the silicon substrate, and depositing a highly textured group III-nitride layer on the interlayer. The interlayer has a nano indentation hardness that is less than both the silicon substrate and the highly textured group III-nitride layer.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: September 18, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Olga Kryliouk, Hyun Jong Park, Timothy J. Anderson
  • Patent number: 8269210
    Abstract: A field emission cathode assembly that has a UV-blocking, insulating dielectric layer (3.4).
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: September 18, 2012
    Assignee: E I du Pont de Nemours and Company
    Inventors: Lap-Tak Andrew Cheng, Adam Fennimore
  • Patent number: 8227268
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well stricture. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: July 24, 2012
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Patent number: 8216863
    Abstract: A method of manufacturing field-emitter arrays by a molding technique includes uniformly controlling a shape of mold holes to obtain field emitter tips having diameters below 100 nm and blunted side edges. Repeated oxidation and etching of a mold substrate formed of single-crystal semiconductor mold wafers is carried out, wherein the mold holes for individual emitters are fabricated by utilizing the crystal orientation dependence of the etching rate.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: July 10, 2012
    Assignee: Paul Scherrer Insitut
    Inventors: Eugenie Kirk, Soichiro Tsujino
  • Patent number: 8198106
    Abstract: A field emitter array structure is provided. The field emitter array structure includes a plurality of vertical un-gated transistor structures formed on a semiconductor substrate. The semiconductor substrate includes a plurality of vertical pillar structures to define said un-gated transistor structures. A plurality of emitter structures are formed on said vertical un-gated transistor structures. Each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical ungated transistor structure to effectively provide high dynamic resistance with large saturation currents.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: June 12, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Akintunde I. Akinwande, Luis Fernando Velásquez-García
  • Patent number: 8188456
    Abstract: A thermionic electron emitter/collector includes a substrate and a doped diamond electron emitter/collector layer on the substrate. The doped diamond electron emitter/collector layer has at least a first and a second doping concentration as a function of depth such that the first doping concentration is different from the second doping concentration.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: May 29, 2012
    Assignee: North Carolina State University
    Inventors: Robert J. Nemanich, Franz A. M. Koeck
  • Publication number: 20120119183
    Abstract: The present invention provides for a fabrication of an integrated THz source. The fabrication includes integrating a field emitter array (FEA) with a grating by utilizing micro-electromechanical system (MEMS) and grating fabrication methods to build the FEA device upon a moveable surface that can be rotated perpendicular to the other, and locked into alignment or alternately finely adjusted.
    Type: Application
    Filed: August 1, 2007
    Publication date: May 17, 2012
    Inventors: Boris G. Kharas, Robert Amantea, Pradyumna Kumar Swain
  • Patent number: 8143514
    Abstract: Method and structure for hydrogenation of silicon substrates with shaped covers. According to an embodiment, the present invention provides a method for fabricating a photovoltaic material. The method includes providing a semiconductor substrate. The method also includes forming a crystalline material characterized by a plurality of worm hole structures therein overlying the semiconductor substrate. The worm hole structures are characterized by a density distribution from a surface region of the crystalline material to a defined depth within a z-direction of the surface region to form a thickness of material to be detached. The method further includes providing a glue layer overlying a surface region of the crystalline material. The method includes joining the surface region of the crystalline material via the glue layer to a support substrate.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 27, 2012
    Assignee: Silicon China (HK) Limited
    Inventors: Yick Chuen Chan, Pui Yee Joan Ho, Nathan W. Cheung, Chung Chan
  • Patent number: 8110417
    Abstract: There is provided a method of forming a pattern on a group III nitride semiconductor substrate. A method of forming a pattern on a group III nitride semiconductor substrate according to an aspect of the invention may include: irradiating a laser beam onto at least one first region for preventing etching in a group III nitride semiconductor substrate; and etching at least one second region exclusive of the first region using the first region irradiated with the laser beam as a mask.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: February 7, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Jong In Yang, Yu Seung Kim, Sang Yeob Song, Si Hyuk Lee, Tae Hyung Kim
  • Patent number: 8076701
    Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: December 13, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhong L. Wang, Christopher J. Summers, Xudong Wang, Elton D Graugnard, Jeffrey King
  • Patent number: 8053258
    Abstract: The present invention is a composition that may be used for sealing applications in the manufacture of electronic devices. The composition includes organic vehicles that may be removed upon low temperature firing in air or inert atmospheres. The present invention is further a process for the use of the composition.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: November 8, 2011
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Lech Wilczek, Ross Getty, Phil Lynch
  • Patent number: 8048397
    Abstract: A method for making a field emission cathode includes the steps of: (a) providing a substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface; (b) forming a conductive film on the first substrate surface; (c) forming a catalyst film on the conductive film, the catalyst film including carbonaceous material; (d) flowing a mixture of a carrier gas and a carbon source gas over the catalyst film; (e) focusing a laser beam on the catalyst film and/or on the second substrate surface to locally heat the catalyst to a predetermined reaction temperature; and (f) growing an array of the carbon nanotubes via the catalyst film to form a field emission cathode.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: November 1, 2011
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhuo Chen, Chun-Xiang Luo, Kai-Li Jiang, Shou-Shan Fan
  • Publication number: 20110253209
    Abstract: A solar cell includes a substrate of a first conductive type; an emitter layer that is positioned on the substrate and is a second conductive type that is opposite to the first conductive type; first electrodes that are connected to the emitter layer; and a second electrode that is connected to the substrate, wherein the emitter layer includes a first emitter portion and a second emitter portion, the first electrodes include a finger electrode, and a bus electrode intersecting and connected to the finger electrode, and the first emitter portion and the second emitter portion are positioned under the bus electrode.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Inventor: JaeSung YOU
  • Patent number: 8030191
    Abstract: Disclosed herein are a method of producing microstructure and a method of producing mold, the methods permitting production of much smaller pores than before in an atmosphere where impurities are negligible and also permitting production of microstructures having a smaller size and a higher crystallinity than before with the help of the pores. The method of producing microstructure comprises a step of making pores (4) in a substrate (1) to become a mold (5) by irradiation with a focused energy beam (3) and a step of growing a microstructure (8) in the thus made pores (4). The method of producing a mold includes a step of making pores (4) by irradiating a substrate (1) to become a mold (5) with a focused energy beam (3).
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventors: Koji Kadono, Yosuke Murakami
  • Patent number: 8017176
    Abstract: A method by which photocathodes(201), single crystal, amorphous, or otherwise ordered, can be surface modified to a robust state of lowered and in best cases negative, electron affinity has been discovered. Conventional methods employ the use of Cs(203) and an oxidizing agent(207), typically carried by diatomic oxygen or by more complex molecules, for example nitrogen trifluoride, to achieve a lowered electron affinity(404). In the improved activation method, a second alkali, other than Cs(205), is introduced onto the surface during the activation process, either by co-deposition, yo-yo, or sporadic or intermittent application. Best effect for GaAs photocathodes has been found through the use of Li(402) as the second alkali, though nearly the same effect can be found by employing Na(406).
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: September 13, 2011
    Inventors: Gregory A. Mulhollan, John C. Bierman
  • Patent number: 8017413
    Abstract: Provided is a method for manufacturing a field emission array with a carbon microstructure. The method includes: a photomask attachment step of attaching a photomask with a pattern groove to one surface of a transparent substrate; a photoresist attachment step of attaching a negative photoresist to one surface of the photomask; an exposure step of irradiating light toward the opposite surface of the transparent substrate from the photomask to cure a portion of the negative photoresist with the light irradiated on the negative photoresist through the pattern groove; a developing step of removing an uncured portion of the negative photoresist while leaving the cured portion of the negative photoresist as a microstructure; a pyrolysis step of heating and carbonizing the microstructure thus obtained; and a cathode attachment step of attaching a voltage-supplying cathode to the surface of the transparent substrate on which the microstructure is formed.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: September 13, 2011
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Seung Seob Lee, Seok Woo Lee, Jung A Lee
  • Publication number: 20110212553
    Abstract: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.
    Type: Application
    Filed: May 6, 2011
    Publication date: September 1, 2011
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West, Robert L. Willett
  • Publication number: 20110193638
    Abstract: A terahertz oscillator may include a first insulating layer, an electron emitter on the first insulating layer, adapted to emit an electron beam, and including a cathode, an anode, an oscillating circuit, and a collector sequentially disposed, spaced apart from each other, on the first insulating layer in a direction in which the electron beam is emitted from the electron emitter, wherein the oscillating circuit converts energy of the electron beam to energy of an electromagnetic wave, and wherein the collector collects the electron beam, an output unit adapted to emit the electromagnetic wave from the oscillating circuit to outside of the terahertz oscillator, and an electron emitting material layer. The cathode may include a first curved portion that extends in a direction perpendicular to the first insulating layer. The electron emitting material layer may be on an inner surface of the first curved portion of the cathode.
    Type: Application
    Filed: June 22, 2010
    Publication date: August 11, 2011
    Inventors: Chan-wook Balk, Joo-ho Lee
  • Publication number: 20110189799
    Abstract: A method for transferring a nano material formed on a first substrate through deposition techniques to a second substrate, includes: (A) contacting the second substrate with a free end of the nano material on the first substrate; (B) heating the first substrate so that heat is conducted substantially from the first substrate through the nano material to the second substrate to soften a contact portion of a surface of the second substrate that is in contact with the free end of the nano material; (C) after step (B), cooling the second substrate so as to permit hardening of the contact portion of the surface of the second substrate and solid bonding of the nano material to the second substrate; and (D) after step (C), removing the first substrate from the nano material.
    Type: Application
    Filed: May 18, 2010
    Publication date: August 4, 2011
    Inventors: Nyan-Hwa TAI, Tsung-Yen TSAI
  • Patent number: 7989233
    Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Lidija Sekaric, Dureseti Chidambarrao, Xiao H. Liu
  • Publication number: 20110140073
    Abstract: Preferred embodiments of the invention provide semiconducting microcavity plasma devices. Preferred embodiments of the invention are microcavity plasma devices having at least two pn junctions, separated by a microcavity or microchannel and powered by alternate half-cycles of a time-varying voltage waveform. Alternate embodiments have a single pn junction. Microplasma is produced throughout the cavity between single or multiple pn junctions and a dielectric layer isolates the microplasma from the single or multiple pn junctions. Additional preferred embodiments are devices in which the spatial extent of the plasma itself or the n or p regions associated with a pn junction are altered by a third (control) electrode.
    Type: Application
    Filed: October 29, 2010
    Publication date: June 16, 2011
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Paul Tchertchian, Clark J. Wagner, Steve Solomon, Robert Ginn
  • Patent number: 7952113
    Abstract: A flat lighting device (10, 10?) that has light-emitting lighting elements (1) arranged on a carrier, which are connected to current supply and current discharge lines (4?) to supply current. The carrier has the form of a metallic sheet (2), which is covered with an insulating layer (3), on which series connections of a lighting element (3) and a surface resistor (5) are arranged between the current supply and current discharge lines (4?). One lighting element (1) and one surface series resistor (5) of a series connection and the series connections and the current supply and current discharge lines (4?) are connected to one another by conductor paths. There is also a method for producing lighting devices of this type.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: May 31, 2011
    Assignee: Amcor Flexibles Kreuzlingen Ltd.
    Inventors: Hans Layer, Martin Werner
  • Patent number: 7944146
    Abstract: The photocathode lighting device of planar light emission including: a light source unit emitting a first light; a cathode plate contacted face-to-face with the light source unit; a metal mask layer adhered to the cathode plate and including a repetitive plurality of apertures; a photocathode formed on a surface of the metal mask layer, receiving the first light, and emitting an electron; an anode plate facing the cathode plate and spaced apart from the cathode plate; and a phosphor formed in a lower part of the anode plate and emitting a second light when the emitted electron collides with the phosphor.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: May 17, 2011
    Assignee: Photegra Corporation
    Inventors: Hyo-Soo Jeong, Kristopher Warren Keller, Joseph Bradley Culkin
  • Patent number: 7943409
    Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 17, 2011
    Assignees: Lumiense Photonics, Inc., Hanvision Co., Ltd.
    Inventor: Robert Steven Hannebauer
  • Publication number: 20110104832
    Abstract: A method of manufacturing field-emitter arrays by a molding technique includes uniformly controlling a shape of mold holes to obtain field emitter tips having diameters below 100 nm and blunted side edges. Repeated oxidation and etching of a mold substrate formed of single-crystal semiconductor mold wafers is carried out, wherein the mold holes for individual emitters are fabricated by utilizing the crystal orientation dependence of the etching rate.
    Type: Application
    Filed: May 29, 2009
    Publication date: May 5, 2011
    Applicant: PAUL SCHERRER INSTITUT
    Inventors: Eugenie Kirk, Soichiro Tsujino
  • Publication number: 20110101299
    Abstract: A method for preparation of carbon nanotubes (CNTs) bundles for use in field emission devices (FEDs) includes forming a plurality of carbon nanotubes on a substrate, contacting the carbon nanotubes with a polymer composition comprising a polymer and a solvent, and removing at least a portion of the solvent so as to form a solid composition from the carbon nanotubes and the polymer to form a carbon nanotube bundle having a base with a periphery, and an elevated central region where, along the periphery of the base, the carbon nanotubes slope toward the central region.
    Type: Application
    Filed: December 7, 2010
    Publication date: May 5, 2011
    Applicant: Brother International Corporation
    Inventor: Kangning Liang
  • Publication number: 20110089396
    Abstract: Provided is a method for manufacturing a field emission array with a carbon microstructure. The method includes: a photomask attachment step of attaching a photomask with a pattern groove to one surface of a transparent substrate; a photoresist attachment step of attaching a negative photoresist to one surface of the photomask; an exposure step of irradiating light toward the opposite surface of the transparent substrate from the photomask to cure a portion of the negative photoresist with the light irradiated on the negative photoresist through the pattern groove; a developing step of removing an uncured portion of the negative photoresist while leaving the cured portion of the negative photoresist as a microstructure; a pyrolysis step of heating and carbonizing the microstructure thus obtained; and a cathode attachment step of attaching a voltage-supplying cathode to the surface of the transparent substrate on which the microstructure is formed.
    Type: Application
    Filed: July 1, 2008
    Publication date: April 21, 2011
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Seung Seob Lee, Seok Woo Lee, Jung A Lee
  • Publication number: 20110057164
    Abstract: A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.
    Type: Application
    Filed: June 17, 2008
    Publication date: March 10, 2011
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Risaku Toda, Michael J. Bronikowski, Edward M. Luong, Harish Manohara