Electron Emitter Manufacture Patents (Class 438/20)
  • Patent number: 7166482
    Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: January 23, 2007
    Assignee: Sony Corporation
    Inventors: Motohiro Toyota, Ichiro Saito, Toshiki Shimamura, Masakazu Muroyama
  • Patent number: 7151005
    Abstract: A method according to the present invention is for electrifying a plurality of electric conductors arranged on a substrate including the step of setting an average temperature difference during electrifying processing between a region S0 in that the plurality of electric conductors on the substrate are arranged and a circumferential region S1 of the region S0 at 15° C. or more, and the substrate satisfies the relational expression: L1/L0>E??T/?th?1. where L0[m]: the width of the region S0 L1[m]: the width of the region S1 ?T[K]: the average temperature difference E[Pa]: the Young's modulus of the substrate ?[/K]: the coefficient of linear thermal expansion of the substrate ?th[Pa]: the material constant of the substrate.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: December 19, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisanobu Azuma
  • Patent number: 7132304
    Abstract: A field emission device comprises a glass substrate, an emitter electrode formed on the glass substrate, a carbon nanotube (CNT) emitter formed on the emitter electrode, and a gate stack formed around the CNT emitter for extracting electron beams from the CNT emitter and focusing the extracted electron beams onto a given position. The gate stack includes a mask layer covering the emitter electrode and provided around the CNT emitter, a gate insulating layer formed on the mask layer to a predetermined height, a mirror electrode formed on an inclined plane of the gate insulating layer, a gate electrode formed on the gate insulating layer and spaced apart from the mirror electrode, and a focus gate insulating layer and a focus gate electrode sequentially formed on the gate electrode. The field emission device is manufactured and employed in a display device in accordance with the present invention.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: November 7, 2006
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jun-Hee Choi, Andrei Zoulkarneev
  • Patent number: 7130002
    Abstract: The present invention relates to a liquid crystal display panel and a fabricating method thereof that is capable of enhancing crystallization efficiency of an active layer and simplifying the fabricating process. A fabricating method of a liquid crystal display panel includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode formed thereon; forming an amorphous silicon film on the gate insulating film; forming an insulating pattern on the amorphous silicon film; crystallizing the amorphous silicon film into a polycrystalline silicon film using a derivative metal, the polycrystalline silicon film having source, drain and channel areas, wherein the insulating pattern overlaps the channel area of the polycrystalline silicon film; and forming source and drain electrodes on the polycrystalline silicon film, wherein the source and the drain electrodes contacting the source and drain areas of the polycrystalline silicon film, respectively.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: October 31, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Hyun Sik Seo, Hae Yeol Kim
  • Patent number: 7118927
    Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: October 10, 2006
    Assignee: Sony Corporation
    Inventors: Motohiro Toyota, Ichiro Saito, Toshiki Shimamura, Masakazu Muroyama
  • Patent number: 7109515
    Abstract: Systems and methods are described for carbon containing tips with cylindrically symmetrical carbon containing expanded bases. A method includes producing an expanded based carbon containing tip including: fabricating a carbon containing expanded base on a substrate; and then fabricating a carbon containing fiber on the expanded base. An apparatus includes a carbon containing expanded base coupled to a substrate; and a carbon containing extension coupled to said carbon containing expanded base. The carbon containing expanded base is substantially cylindrically symmetrical and said carbon containing extension is substantially cylindrically symmetrical.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: September 19, 2006
    Assignee: UT-Battelle LLC
    Inventors: Vladimir I. Merkulov, Douglas H. Lowndes, Michael A. Guillorn, Michael L. Simpson
  • Patent number: 7098056
    Abstract: A method for producing carbon nanotubes, the method comprising: (a) providing a substrate with a top surface, (b) forming an island of catalyst material on the top surface using a tip having a patterning compound thereon, (c) heating the substrate and catalyst island, and (d) contacting the catalyst island with a carbon-containing gas for a period of time sufficient to form the nanotubes on the catalyst island.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: August 29, 2006
    Assignee: Nanoink, Inc.
    Inventor: Linette Demers
  • Patent number: 7091054
    Abstract: An emitter for an electron-beam projection lithography (EPL) system and a manufacturing method therefor are provided. The electron-beam emitter includes a substrate, an insulating layer overlying the substrate, and a gate electrode including a base layer formed on top of the insulating layer to a uniform thickness and an electron-beam blocking layer formed on the base layer in a predetermined pattern. The manufacturing method includes steps of: preparing a substrate; forming an insulating layer on the substrate; forming a base layer of a gate electrode by depositing a conductive metal on the insulating layer to a predetermined thickness; forming an electron-beam blocking layer of the gate electrode by depositing a metal capable of anodizing on the base layer to a predetermined thickness; and patterning the electron-beam blocking layer in a predetermined pattern by anodizing. The emitter provides a uniform electric field within the insulating layer and simplify the manufacturing method therefor.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: August 15, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-kyeong Yoo, Chang-wook Moon, Soo-hwan Jeong, Dong-wook Kim
  • Patent number: 7084426
    Abstract: To provide an organic EL device which, with simple configuration, exhibits a high brightness, a high light-emitting efficiency and a long life span in organic light-emitting layers for all colors, and has excellent conservation stability to heat. An organic EL device of the present invention has a laminate comprising an anode and a cathode with an organic light-emitting layer interposed therebetween. The organic light-emitting layer is made of a high-molecular-weight light-emitting material. Further, the cathode comprises a first layer made of fluoride or oxide of an alkali metallic material, fluoride or oxide of an alkali earth metallic material, or complex or compound of an organic material, and a second layer made of a magnesium alloy. Here, the first layer and the second layer are sequentially deposited on the organic light-emitting layer.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: August 1, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Masahiro Uchida
  • Patent number: 7078249
    Abstract: A method of forming a sharp silicon structure, such as a silicon field emitter, includes oxidizing the silicon structure to form an oxide layer thereon, then removing the oxide layer. Oxidizing may occur at a low temperature and form a relatively thin (e.g., about 20 ? to about 40 ?) oxide layer on the silicon field emitter. The oxide layer may be removed by etching. A silicon field emitter that has been fabricated in accordance with the method is substantially free of crystalline defects and may include an emitter tip having a diameter as small as about 40 ? to about 20 ? or less.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: July 18, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Tianhong Zhang
  • Patent number: 7074498
    Abstract: The influence of surface geometry on metal properties is studied within the limit of the quantum theory of free electrons. It is shown that a metal surface can be modified with patterned indents to increase the Fermi energy level inside the metal, leading to decrease in electron work function. This effect would exist in any quantum system comprising fermions inside a potential energy box. Also disclosed is a method for making nanostructured surfaces having perpendicular features with sharp edges.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: July 11, 2006
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Stuart Harbron
  • Patent number: 7065857
    Abstract: The method of manufacturing an electric part including a matrix-shaped nonconductive base member, and a carbon nanotube group that is sealed within the nonconductive base member and includes at least one of a carbon nanotube and a plurality carbon nanotubes that are electrically connected to each other. According to the method, substantially only an end portion of the carbon nanotube or at least carbon nanotube contained in the plurality of carbon nanotubes may be exposed from one surface of the nonconductive base member, and an electrode may be connected to a side surface of at least one carbon nanotube included in the carbon nanotube group.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: June 27, 2006
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Miho Watanabe, Hiroyuki Watanabe, Chikara Manabe, Masaaki Shimizu
  • Patent number: 7067336
    Abstract: An electron-emitting device having favorable electron emitting characteristic stable for a long time, which is manufactured by a method comprising the steps of disposing an electrically conductive member having a second gap on a substrate, and applying a voltage to the electrically conductive member while irradiating at least the second gap with an electron beam from electron emitting means disposed apart from the electrically conductive member in an atmosphere comprising a carbon compound.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: June 27, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Kyogaku, Hironobu Mizuno, Takeo Tsukamoto, Hiroyuki Hashimoto, Koki Nukanobu
  • Patent number: 7061006
    Abstract: Structures and methods to inject electrons into an insulator from a semiconductor layer that are then collected in a thin layer of a direct semiconductor material which in turn emits light by bandgap recombination.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 13, 2006
    Inventor: Robert W. Bower
  • Patent number: 7056753
    Abstract: A field emission display with a double gate structure and a method of manufacturing therefor are provided. The field emission display includes a substrate, a cathode layer formed on the substrate, a gate insulating layer which is formed on the substrate and the cathode layer and has a cavity through which part of the cathode layer is exposed, a field emitter provided on the cathode layer exposed on the bottom of the cavity, a first gate layer which is formed in the gate insulating layer and in which a first gate hole having a diameter greater than that of the cavity is formed not to be exposed to an inner surface of the cavity, and a second gate layer which is formed on the gate insulating layer and in which a second gate hole is formed in a portion that corresponds to the cavity.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: June 6, 2006
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Hang-woo Lee, Pil-soo Ahn, Andrei Zoulkarneev
  • Patent number: 7052923
    Abstract: This invention provides a conductive aluminum film and method of forming the same, wherein a non-conductive impurity is incorporated into the aluminum film. In one embodiment, the introduction of nitrogen creates an aluminum nitride subphase which pins down hillocks in the aluminum film to maintain a substantially smooth surface. The film remains substantially hillock-free even after subsequent thermal processing. The aluminum nitride subphase causes only a nominal increase in resistivity (resistivities remain below about 12 ??-cm), thereby making the film suitable as an electrically conductive layer for integrated circuit or display devices.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: May 30, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Kanwal K. Raina
  • Patent number: 7049158
    Abstract: A method is disclosed for creating an emitter having a flat cathode emission surface: First a protective layer that is conductive is formed on the flat cathode emission surface. Then an electronic lens structure is created over the protective layer. Finally, the protective layer is etched to expose the flat cathode emission surface.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 23, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhizhang Chen, Paul J. Benning, Sriram Ramamoorthi, Thomas Novet
  • Patent number: 7044823
    Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: May 16, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhizhang Chen, Michael J. Regan, Brian E Bolf, Thomas Novet, Paul J. Benning, Mark Alan Johnstone, Sriram Ramamoorthi
  • Patent number: 7045807
    Abstract: A field emission device, a field emission display for displaying images with good quality adopting the same, and a manufacturing method thereof are provided. The field emission device allows a mesh grid to closely contact the surface of a field emission array on a substrate and for this purpose, applies a tensile force to the mesh grid using a predetermined tension member.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: May 16, 2006
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Jun-hee Choi
  • Patent number: 7041518
    Abstract: Provided are a low-temperature formation method for emitter tips including copper oxide nanowires or copper nanowires and a display device or a light source manufactured using the same. The low-temperature formation method includes preparing a substrate having an exposed copper surface. The copper surface contacts an oxide solution at a low temperature of 100° C. or less to grow copper oxide nanowires on the surface of the substrate. Optionally, a reduction gas or a heat is supplied to the copper oxide nanowires, or plasma processing is performed on the copper oxide nanowires, thereby reducing the copper oxide nanowires to copper nanowires. Thus, emitter tips including copper oxide nanowires or copper nanowires are formed densely at a low temperature such that the emitter tips have a shape and length suitable for emission of electrons.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: May 9, 2006
    Assignee: Seoul National University Industry Foundation
    Inventors: Ho-Young Lee, Yong-Hyup Kim, Woo Yong Sung
  • Patent number: 7033848
    Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: April 25, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Toru Takayama, Kengo Akimoto
  • Patent number: 7029592
    Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads are dispensed as a hexagonally packed monolayer onto a thermo-adhesive layer. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: April 18, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Joel M. Frendt
  • Patent number: 7025651
    Abstract: Disclosed is a LED which can be mounted at high density on a large area display. Having a hole for heat sink in the ceramic substrate, the LED is superior in heat sink property. In order to fabricate the light emitting device, first, a secondary ceramic sheet is stacked on the ceramic substrate, followed by forming electrodes in a predetermined pattern on the secondary ceramic sheet around the hole for heat sink. On the ceramic substrate, an upper ceramic sheet with an opening is stacked to form a stacked ceramic substrate in such a way that a part of the electrodes are exposed through the opening. After co-firing the stacked ceramic substrate, a light emitting diode chip is mounted on the secondary ceramic sheet at a position corresponding to the hole for heat sink. Then, the electrodes are electrically connected with the LED chip, and the LED chip is sealed with insulating resin. A light emitting device using the LED and a fabrication method therefor are also disclosed.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: April 11, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung-Sub Song, Young-Ho Park, Chang-Yong Lee
  • Patent number: 7026177
    Abstract: A replaceable, electronically-isolated, MCP-based spectrometer detector cartridge with enhanced sensitivity is disclosed. A coating on the MCP that enhances the secondary electron emissivity characteristics of the MCP is selected from aluminum oxide (Al2O3), magnesium oxide (MgO), tin oxide (SnO2), quartz (SiO2), barium flouride (BaF2), rubidium tin (Rb3Sn), berrylium oxide (BeO), diamond and combinations thereof. A mass detector is electro-optically isolated the from a charge collector with a method of detecting a particle including accelerating the particle with a voltage, converting the particle into a multiplicity of electrons and converting the multiplicity of electrons into a multiplicity of photons. The photons then are converted back into electrons which are summed into a charge pulse. A detector also is provided.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: April 11, 2006
    Assignee: Burle Technologies, Inc.
    Inventor: Bruce Laprade
  • Patent number: 7011981
    Abstract: A method for forming a thin film and a method for fabricating a liquid crystal display device using the same are provided. The method provides a process that is simplified. Uniform thin film characteristics can be obtained. The method for forming a thin film includes the steps of forming a diffusion barrier film on a substrate, forming a metal seed layer on the diffusion barrier film, removing a metal oxide film formed on a surface of the metal seed layer using an electric plating method, and depositing metal on the metal seed layer in which the metal oxide film is removed.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: March 14, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Soo Kil Kim, Jong Uk Bae, Jae Jeong Kim
  • Patent number: 7001787
    Abstract: An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 21, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsufumi Tanamoto, Satoshi Saito, Shinobu Fujita
  • Patent number: 6998635
    Abstract: A photocathode includes a first layer having a first energy band gap for providing absorption of light of wavelengths shorter than or equal to a first wavelength, a second layer having a second energy band gap for providing transmission of light of wavelengths longer than the first wavelength, and a third layer having a third energy band gap for providing absorption of light of wavelengths between the first wavelength and a second wavelength. The first wavelength is shorter than the second wavelength. The first, second and third layers are positioned in sequence between input and output sides of the photocathode.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: February 14, 2006
    Assignee: ITT Manufacturing Enterprises Inc.
    Inventors: Roger S. Sillmon, Arlynn W. Smith, Rudy G. Benz
  • Patent number: 6991949
    Abstract: A cold cathode field emission device comprising a cathode electrode 11 formed on a supporting member 10, a gate electrode 13 which is formed above the cathode electrode 11 and has an opening portion 14, and an electron emitting portion 15 formed on a surface of a portion of the cathode electrode 11 which portion is positioned in a bottom portion of the opening portion 14, said electron emitting portion 15 comprising a carbon-group-material layer 23, and said carbon-group-material layer 23 being a layer formed from a hydrocarbon gas and a fluorine-containing hydrocarbon gas.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: January 31, 2006
    Assignee: Sony Corporation
    Inventors: Masakazu Muroyama, Takao Yagi, Kouji Inoue, Ichiro Saito
  • Patent number: 6987027
    Abstract: The invention comprises a method of fabricating a vacuum microtube device comprising the steps of forming a cathode layer comprising an array of electron emitters, forming a gate layer comprising an array of openings for passing electrons from the electron emitters, and forming an anode layer for receiving electrons from the emitters. The cathode gate layer and the anode layer are vertically aligned and bonded together with intervening spacers on a silicon substrate so that electrons from respective emitters pass through respective gate openings to the anode. The use of substrate area is highly efficient and electrode spacing can be precisely controlled. An optional electron multiplying structure providing secondary electron emission material can be disposed between the gate layer and the anode in the path of emitted electrons.
    Type: Grant
    Filed: August 23, 2003
    Date of Patent: January 17, 2006
    Assignee: The Regents of the University of California
    Inventor: Sungho Jin
  • Patent number: 6984535
    Abstract: An electron-emitting device including a protective layer that is formed on a catalyst layer to protect the catalyst layer from the deleterious environmental conditions before or during a cathode process. The present invention further includes a half etching process that is adapted to partially remove portions of the protective layer from the catalyst layer to etch the catalyst layer except carbon nano-tube growing portions. Portions of the protective layer still remain on the catalyst layer to protect the catalyst layer from the deleterious conditions from next cathode formation process.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 10, 2006
    Assignee: cDream Corporation
    Inventors: Jong Woo Son, Chul Ha Chang, Jung-Jae Kim, Koji Suzuki, Takashi Kuwahara
  • Patent number: 6972203
    Abstract: A method according to the present invention is for electrifying a plurality of electric conductors arranged on a substrate including the step of setting an average temperature difference during electrifying processing between a region S0 in that the plurality of electric conductors on the substrate are arranged and a circumferential region S1 of the region S0 at 15° C. or more, and the substrate satisfies the relational expression: L1/L0>E??T/?th?1. where L0[m]: the width of the region S0 L1[m]: the width of the region S1 ?T[K]: the average temperature difference E[Pa]: the Young's modulus of the substrate ?[/K]: the coefficient of linear thermal expansion of the substrate ?th[Pa]: the material constant of the substrate.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: December 6, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisanobu Azuma
  • Patent number: 6972472
    Abstract: An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structure is then formed over the window and conformally extends into the undercut region thereby widening the emitter region and so reducing the distance between the edge of the emitter and the extrinsic base (the base link distance) and therefore reducing the total base resistance of the transistor.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: December 6, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven M. Leibiger, Daniel J. Hahn, Laurence M. Szendrei
  • Patent number: 6964877
    Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: November 15, 2005
    Assignee: GELcore, LLC
    Inventors: Chen-Lun Hsing Chen, Stanton Weaver, Jr., Ivan Eliashevich, Sebastien Libon, Mehmet Arik, David Shaddock
  • Patent number: 6960878
    Abstract: A light emitting diode comprising an LED chip having a light emitting layer made of a nitride compound semiconductor and a light transmitting resin that includes a fluorescent material which absorbs at least a part of light emitted by the LED chip and emits light of a different wavelength, wherein the fluorescent material includes a fluorescent particles of small particle size and a fluorescent particles of large particle size, the fluorescent particles of large particle size being distributed in the vicinity of the LED chip in the light transmitting resin to form a wavelength converting layer, the fluorescent particles of small particle size being distributed on the outside of the wavelength converting layer in the light transmitting resin.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: November 1, 2005
    Assignee: Nichia Corporation
    Inventors: Kensho Sakano, Kazuhiko Sakai, Yuji Okada, Toshihiko Umezu
  • Patent number: 6953375
    Abstract: A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of the emitters and has a thickness substantially equal to a height of the emitters above the substrate. The porous dielectric layer may be formed by oxidation of porous polycrystalline silicon. The display also includes an extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters. The display further includes a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters. The porous dielectric layer results in columns having less capacitance compared to prior art displays.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: October 11, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6953701
    Abstract: A method of sharpening a tapered or pointed silicon structure, such as a silicon field emitter. The method includes oxidizing the silicon field emitter to form an oxide layer thereon and removing the oxide layer. Oxidizing occurs at a low temperature and forms a relatively thin (e.g., about 20 ? to about 40 ?) oxide layer on the silicon field emitter. The oxide layer may be removed by etching. The method may be employed to sharpen existing silicon structures or in fabricating tapered or pointed silicon structures. A silicon field emitter that has been sharpened or fabricated in accordance with the method is substantially free of crystalline defects and includes an emitter tip having a diameter as small as about 40 ? to about 20 ? or less.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: October 11, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Tianhong Zhang
  • Patent number: 6943052
    Abstract: A support substrate having the same size as a device substrate provided with alignment marks is disposed opposite to and adhered to the back side of the device substrate. At least the face side of the device substrate on the support substrate is cut at division lines along a functional region. An organic film is formed on the functional region of the device substrate thus cut. The support substrate is cut along the functional region of the device substrate, thereby removing peripheral portions of the support substrate and the device substrate, to form a display panel. Positioning of the substrate relative to a manufacturing apparatus for each step can be performed with high accuracy, in the manufacturing process including a step of cutting the substrate to a smaller size in the course of manufacture.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: September 13, 2005
    Assignee: Sony Corporation
    Inventors: Isao Kamiyama, Shoji Terada
  • Patent number: 6939728
    Abstract: A high emission electron emitter and a method of fabricating a high emission electron emitter are disclosed. A high emission electron emitter includes an electron injection layer, an active layer of high porosity porous silicon material in contact with the electron injection layer, a contact layer of low porosity porous silicon material in contact with the active layer and including an interface surface with a heavily doped region, and an optional top electrode in contact with the contact layer. The contact layer reduces contact resistance between the active layer and the top electrode and the heavily doped region reduces resistivity of the contact layer thereby increasing electron emission efficiency and stable electron emission from the top electrode. The electron injection layer is made from an electrically conductive material such as n+ semiconductor, n+ single crystal silicon, a metal, a silicide, or a nitride.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: September 6, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Xia Sheng, Nobuyoshi Koshida, Huei-Pei Kuo
  • Patent number: 6936484
    Abstract: An impurity precipitation region is formed by introducing an impurity, e.g., oxygen, into a silicon substrate or a silicon layer and thermally treating it, and performing high selectivity anisotropic etching with the precipitation region used as a micro mask. Thus, a cone (conic body or truncated conic body having an annular leading end) having a very sharp and slender needle shape with an aspect ratio of about 10 and a diameter of about 10 nm to 30 nm in the vicinity of its leading end is obtained with the micro mask used as the top. By forming an insulation layer and a drive electrode such as a gate electrode around the cone, the cone can be used for a field emission device, a single electron transistor, a memory device, a high frequency switching device, a probe of a scanning type microscope or the like.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: August 30, 2005
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Masakazu Kanechika, Kenji Nakashima, Yasuichi Mitsushima, Tetsu Kachi
  • Patent number: 6933665
    Abstract: Improved methods and structures are provided for an array of vertical geometries which may be used as emitter tips, as a self aligned gate structure surrounding field emitter tips, or as part of a flat panel display. The present invention offers controlled size in emitter tip formation under a more streamlined process. The present invention further provides a more efficient method to control the gate to emitter tip proximity in field emission devices. The novel method of the present invention includes implanting a dopant in a patterned manner into the silicon substrate and anodizing the silicon substrate in a controlled manner causing a more heavily doped region in the silicon substrate to form a porous silicon region.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: August 23, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Terry L. Gilton, Paul A. Morgan
  • Patent number: 6924158
    Abstract: A method of forming vertical knife-edge cold-cathode field emission electron sources with self-aligned gate electrodes and sub-micron electrode separations. The method exploits the enhancement of ion-beam erosion rates obtained in metals at oblique ion incidence, which allows the preferential removal of a metal layer at the convex edge of a mesa 2 to create a well-defined separation between the horizontal and vertical surfaces of the metal. The horizontal surface may be used as the gate and the vertical surface as the cathode in a vacuum triode structure. Electrical isolation is obtained by forming the mesa 2 in an insulating layer or substrate 1. Isolation may be improved by removing the insulating material in the vicinity of the metal edges. Field-induced electron emission from the cathode may be obtained at low voltage based on the enhancement of the electric field at the sharp tip of the cathode.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: August 2, 2005
    Assignee: Microsaic Systems Limited
    Inventor: Richard Syms
  • Patent number: 6910936
    Abstract: In manufacturing surface conduction electron-emitting devices, a polymer thin film is arranged to connect a pair of electrodes and then transformed into a low resistivity film (carbon film) by irradiating the polymer film with an energy beam. The energy beam irradiation is scanned over the polymer films plural times so that heat due to the energy beam irradiation does not affect other members which constitute the device and also the processing time for carbonization of polymer film is reduced.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: June 28, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Shimazu, Hironobu Mizuno
  • Patent number: 6911154
    Abstract: A method for manufacturing a structure, including the steps of forming on the substrate a piling of a first insulating layer, a first metallization level, a second insulating layer, and a second metallization level, opening in the second metallization level and in the second insulating layer first windows corresponding to the contour of the first openings and second windows, the external contour of which corresponds to the internal contour of the second openings, forming in a masking layer third windows larger than the first windows, etching the first metallization level in the first windows, removing the second metallization level under the masking layer to as far as the internal periphery of the second windows, etching by a chosen distance the first insulating layer, and simultaneously removing the second insulating layer within the contour of the second windows, and removing the masking layer.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: June 28, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Christophe Bourcheix
  • Patent number: 6910935
    Abstract: A method of manufacturing an electron source, comprising the steps of (A) providing a substrate on which are disposed a plurality of units, each unit including a pair of electrodes and a polymer film connecting the pair of electrodes, and (B) selecting one or more units from the plurality of units. The method also comprises (C) applying a potential difference across the pair of electrodes that is included in each of the selected one or more units, and (D) irradiating light or a particle beam to the polymer film included in each of the selected one or more units in a state of being applied with the potential difference. Step (D) preferably is started after step (C) is started.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: June 28, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yutaka Arai, Takashi Iwaki
  • Patent number: 6902458
    Abstract: An emitter has an electron supply layer and a silicon-based dielectric layer formed on the electron supply layer. The silicon-based dielectric layer is preferably less than about 500 Angstroms. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within which the silicon-based dielectric layer is formed. A cathode layer is formed on the silicon-based dielectric layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: June 7, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhizhang Chen, Michael David Bic, Ronald L. Enck, Michael J. Regan, Thomas Novet, Paul J. Benning
  • Patent number: 6900066
    Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light form a back surface side of the support member through the hole at a mask for exposure.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: May 31, 2005
    Assignee: Sony Corporation
    Inventors: Motohiro Toyota, Ichiro Saito, Toshiki Shimamura, Masakazu Muroyama
  • Patent number: 6897139
    Abstract: A titanium layer and a titanium nitride layer are successively laminated on a substrate and a group III nitride compound semiconductor layer is further formed thereon. When the titanium layer is removed in the condition that a sufficient film thickness is given to the titanium nitride layer, a device having the titanium nitride layer as a substrate is obtained.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: May 24, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Masanobu Senda
  • Patent number: 6896571
    Abstract: In a process of reducing a resistivity of a polymer film for carbonization in a surface conduction electron-emitting device, by irradiating an energy beam onto the polymer film, when an energy intensity of the beam given in a unit area in a unit time is assumed to be W W/m2, W satisfies a formula W?2×T×(?sub·Csub·?sub/?)1/2, where T is defined as a temperature ° C. at which the polymer film is heated for one hour in a vacuum degree of 1×10?4 Pa to reduce a resistivity of the polymer film to 0.1 ?·cm, Csub is a specific heat J/kg·K of the substrate, ?sub is a specific gravity kg/m3 of the substrate, ?sub is a heat conductivity W/m·K of the substrate, and ? is an irradiation time in the range of 10?9 sec to 10 sec.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: May 24, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hironobu Mizuno, Takashi Iwaki, Toshihiko Takeda, Noritake Suzuki, Kazuya Miyazaki, Koki Nukanobu
  • Patent number: 6893886
    Abstract: A method for processing one-dimensional nano-materials includes the following steps: providing a substrate (11); forming one-dimensional nano-materials (12) on the substrate, the one-dimensional nano-materials being substantially parallel to each other and each being substantially perpendicular to the substrate, the one-dimensional nano-materials cooperatively defining a top surface distal from the substrate; and applying physical energy (14) by means of a high-energy pulse laser beam to the top surface of the one-dimensional nano-materials. The resulting one-dimensional nano-materials have sharp, tapered tips (15, 15?). Distances between adjacent tips are approximately uniform, and are relatively large. This reduces shielding between adjacent one-dimensional nano-materials. The tips also contribute to a decreased threshold voltage required for field emission by the one-dimensional nano-materials.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: May 17, 2005
    Assignee: Hon Hai Precision Ind. Co., LTD
    Inventors: Liang Liu, Shoushan Fan
  • Patent number: 6887725
    Abstract: A micro electron gun that is capable of extracting electrons from a semiconductor utilizing a quantum size effect and that can be mounted individually for each of pixels is disclosed, as well as a picture display apparatus using such electron guns which is high in quantum efficiency, of high brightness and thin, as well as methods of manufacture thereof. Conduction electrons from a n-type semiconductor substrate (2) are accelerated under an electric field through a layer or layers (4) of quantum size effect micro particles (3) formed on surfaces of the n-type semiconductor substrate (2) and passed therethrough without undergoing phonon scattering, so that they when arriving at an electrode (5) may possess an amount of energy not less than the work function of the electrode (5) and are thus allowed to spring out into a vacuum.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: May 3, 2005
    Assignee: Japan Science and Technology Agency
    Inventors: Shunri Oda, Xinwei Zhao, Katsuhiko Nishiguchi