Electron Emitter Manufacture Patents (Class 438/20)
  • Publication number: 20090072750
    Abstract: A field emitter array structure is provided. The field emitter array structure includes a plurality of vertical un-gated transistor structures formed on a semiconductor substrate. The semiconductor substrate includes a plurality of vertical pillar structures to define said un-gated transistor structures. A plurality of emitter structures are formed on said vertical un-gated transistor structures. Each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical ungated transistor structure to effectively provide high dynamic resistance with large saturation currents.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 19, 2009
    Inventors: Akintunde I. Akinwande, Luis Fernando Velasquez-Garcia
  • Publication number: 20090065051
    Abstract: Method and structure for hydrogenation of silicon substrates with shaped covers. According to an embodiment, the present invention provides a method for fabricating a photovoltaic material. The method includes providing a semiconductor substrate. The method also includes forming a crystalline material characterized by a plurality of worm hole structures therein overlying the semiconductor substrate. The worm hole structures are characterized by a density distribution from a surface region of the crystalline material to a defined depth within a z-direction of the surface region to form a thickness of material to be detached. The method further includes providing a glue layer overlying a surface region of the crystalline material. The method includes joining the surface region of the crystalline material via the glue layer to a support substrate.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 12, 2009
    Applicant: Silicon China (HK) Limited
    Inventors: Yick Chuen Chan, Pui Yee Ho, Nathan W. Cheung, Chung Chan
  • Publication number: 20090045720
    Abstract: Disclosed herein is a method for producing nanowires, which features the use of a porous glass template in combination with a solid-liquid-solid or vapor-liquid-solid process for growing nanowires which are highly straight and have nanoparticles precisely arranged therein. The nanowires can be grown into composite structures of superlattices and hybrids by modulating the composition of the materials provided thereto. Also disclosed is the use of the nanowires in multi-probes, field emission tips, and devices.
    Type: Application
    Filed: June 8, 2006
    Publication date: February 19, 2009
    Inventors: Eun Kyung Lee, Byoung Lyong Choi, Jong Min Kim, Soon Jae Kwon, Kyung Sang Cho, Jae Ho Lee
  • Patent number: 7492012
    Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Toru Takayama, Kengo Akimoto
  • Patent number: 7492417
    Abstract: Disclosed is an active matrix liquid crystal display device designed mainly for alternating electric current drive, in which orientation processing (monostabilization) is performed by a direct current power supply or a direct current voltage applied to a ferroelectric liquid crystal. The liquid crystal is made to respond, and is made monostable while a voltage level is maintained by a storage capacitor. In addition, the liquid crystal may also be made monostable while maintaining a gate clock pulse at a constant level. After forming a transparent conductive film on an element substrate, elements such as TFTs are formed. An electric field is applied by a direct current voltage source between an electrode formed on an opposing substrate and the transparent conductive film. An electric field is applied by a direct current voltage source between the electrode formed on the opposing substrate and the transparent conductive film formed on the back side of the element substrate.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: February 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Rumo Satake
  • Publication number: 20090023232
    Abstract: An organic electroluminescence element has a layered structure on a surface of a transparent substrate. The layered structure comprises an organic material layer including a light-emitting organic material layer, an opaque electrode layer, an insulating layer, a metal layer and a resin film in order. The organic electroluminescence element is improved in durability because moisture is prevented from permeating into a light-emitting element.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 22, 2009
    Applicants: TOKAI RUBBER INDUSTRIES, LTD.
    Inventors: Yoshio TANIGUCHI, Masato SUGIYAMA, Shingo HIBINO, Tetsuya TAKEUCHI, Ryo MINOSHIMA
  • Publication number: 20090001936
    Abstract: A silicon/lithium battery can be fabricated from a silicon substrate. This allows the battery to be produced as an integrated unit on a chip. The battery includes a silicon anode formed from submicron diameter pillars of silicon fabricated on an n-type silicon wafer. The battery also includes a cathode including lithium.
    Type: Application
    Filed: March 4, 2008
    Publication date: January 1, 2009
    Inventor: Mino Green
  • Patent number: 7470554
    Abstract: A method of forming a stacking structure by forming an electroconductive layer precursor pattern by an electroconductive paste made of a resin component, electroconductive fine particles, and glass fine particles, forming a dielectric layer precursor pattern by a dielectric paste made of a resin component and glass fine particles, and simultaneously baking both of those patterns, wherein they are held for a predetermined time while keeping a baking temperature which is equal to or higher than a decomposing temperature of the resin component and is equal to or lower than a baking start temperature of the glass fine particles and, thereafter, their baking is completed at the baking temperature which is equal to or higher than the baking start temperature of the glass fine particles and is lower than its softening point. Thus, the occurrence of a void and a pin hole in an insulative layer can be prevented in the stacking structure after the baking.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: December 30, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toru Sugeno
  • Patent number: 7462498
    Abstract: Substantially enhanced field emission properties are achieved by using a process of covering a non-adhesive material (for example, paper, foam sheet, or roller) over the surface of the CNTs, pressing the material using a certain force, and removing the material.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: December 9, 2008
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Dongsheng Mao, Richard Fink, Zvi Yaniv
  • Patent number: 7462499
    Abstract: A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: December 9, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: John F. Conley, Jr., Yoshi Ono, Lisa H. Stecker, Sheng Teng Hsu, Josh M. Green, Lifeng Dong, Jun Jiao
  • Patent number: 7456491
    Abstract: The present invention relates to a various systems for generating and directing electron flow, and related methods, manufacturing techniques and related componentry, such as can be used in lithography, microscopy and other applications. In one embodiment, the present invention involves a system that includes an electron source having a plurality of independently-actuatable emission surfaces each of which is capable of emitting electrons, and an optical column adjacent to the electron source through which the emitted electrons pass. The optical column includes a plurality of actuatable electrodes that are capable of influencing paths taken by the emitted electrons.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: November 25, 2008
    Inventor: Subrahmanyam V. S. Pilla
  • Patent number: 7452735
    Abstract: Composition of carbon nanotubes (CNTs) are produced into inks that are dispensable via printing or stencil printing processes. The CNT ink is dispensed into wells formed in a cathode structure through a stencil.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: November 18, 2008
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Yunjun Li, Richard Fink, Mohshi Yang, Zvi Yaniv
  • Patent number: 7445535
    Abstract: An electron source producing apparatus for forming an electron-emission part on a conductive member disposed on a substrate in an atmosphere containing a desired gas. The apparatus includes a container for forming a hermetic atmosphere between the container and a surface of the substrate on which the conductive member is formed. The container has a gas inlet and a gas outlet. A diffusing member is for diffusing an introduced gas, and is disposed between the gas inlet and the surface of the substrate. A resisting member provides exhaust resistance, and is disposed between the gas outlet and the surface of the substrate and is separated from the gas outlet. The resisting member is disposed closer to the surface of the substrate than is the diffusing member.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: November 4, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazumasa Takatsu, Shigeto Kamata
  • Publication number: 20080258604
    Abstract: Methods and systems for absorbing infrared light, and for emitting current are described. A sample, such as a sample containing mainly silicon, is microstructured by at least one laser pulse to produce cone-like structures on the exposed surface. Such microstructuring enhances the infrared absorbing, and current emission properties of the sample.
    Type: Application
    Filed: June 23, 2008
    Publication date: October 23, 2008
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Eric Mazur, James Edward Carey, Catherine H. Crouch, Rebecca Jane Younkin, Claudia Wu
  • Publication number: 20080261337
    Abstract: A method of fabricating an electron source having a self-aligned gate aperture is disclosed. A substrate is deposited on a first conductive layer. Over the first conductive layer an emitter layer is deposited. The emitter layer includes one or a plurality of spaced-apart nano-structures and a solid surface with nano-structures protruding above the surface. An insulator is conformally deposited over the emitter layer surface and forms a post from each protruding nano-structure. A second conductive layer is deposited over the insulator and the second conductive layer and the insulator are removed from the nano-structures such that apertures are formed in the second conductive layer and at least the ends of the nano-structures are exposed at the centers of said apertures.
    Type: Application
    Filed: October 29, 2007
    Publication date: October 23, 2008
    Inventor: Zhidan Li Tolt
  • Patent number: 7435689
    Abstract: A process for fabricating an electron emitting device comprises a cathode electrode and a gate electrode are laminated through an insulating layer and an electron emitting film on the cathode electrode located in a gate hole penetrating through the gate electrode and the insulating layer. Wherein, a second hole penetrating through at least the gate electrode between the insulating layer and the gate electrode is juxtaposed with a first hole as a gate hole is formed, and the insulating layer between the second hole and the first hole in which the electron emitting film is deposited to the inner wall surface is etched until the first hole and the second hole are communicated with each other. Thereby, electron emitting film material is removed form the hole to reduce a leakage current.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: October 14, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoji Teramoto
  • Publication number: 20080238702
    Abstract: An exemplary electrostatic discharge protection device includes: an electrostatic discharge part configured for discharging electrostatic when the electrostatic is larger than a threshold value; and a light emitting part configured for emitting light when electrostatic discharge happens.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Inventor: Shuo-Ting Yan
  • Patent number: 7419843
    Abstract: A method of manufacturing a semiconductor probe having a resistive tip. The method includes forming first and second mask films having a rectangular shape on a silicon substrate, first etching an upper surface of the silicon substrate, forming a third mask film corresponding to a width of a tip neck by etching the first mask film, forming the width of the tip neck to a predetermined width by second etching of the silicon substrate using the third mask film as a mask, and forming a peak forming portion of the tip by annealing the silicon substrate after removing the third mask film. A semiconductor probe having a uniform height and tips having a uniform neck width can be manufactured.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-min Park, Hong-sik Park, Hyoung-soo Ko, Seung-bum Hong
  • Patent number: 7411341
    Abstract: The present invention relates to gated nanorod field emission devices, wherein such devices have relatively small emitter tip-to-gate distances, thereby providing a relatively high emitter tip density and low turn on voltage. Such methods employ a combination of traditional device processing techniques (lithography, etching, etc.) with electrochemical deposition of nanorods. These methods are relatively simple, cost-effective, and efficient; and they provide field emission devices that are suitable for use in x-ray imaging applications, lighting applications, flat panel field emission display (FED) applications, etc.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 12, 2008
    Assignee: General Electric Company
    Inventors: Heather Diane Hudspeth, Reed Roeder Corderman, Renee Bushey Rohling, Lauraine Denault
  • Patent number: 7405092
    Abstract: A method of manufacturing an electron-emitting device with a stable electrical characteristics without variation per each of the devices is provided, by forming, on a substrate, a cathode electrode, a carbon layer on the cathode electrode, and a gate electrode, disposing an anode electrode, and applying to the carbon layer a voltage higher than that at a driving of the electron-emitting device.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: July 29, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Michiyo Nishimura
  • Patent number: 7402445
    Abstract: Methods of forming a nano-structure for electron extraction are disclosed. One method of forming a nano-structure comprises irradiating an area on a first surface of a thermal conductive film to melt the area across the film. The film is insulated on a second surface to provide two-dimensional heat transfer across the film. The liquid density of the film is greater than the solid density thereof. The method further comprises cooling the area inwardly from the periphery thereof to form a nano-structure having an apical nano-tip for electron extraction.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: July 22, 2008
    Assignee: Wayne State University
    Inventors: Daniel G. Georgiev, Ivan Avrutsky, Ronald J. Baird, Golam Newaz, Gregory W. Auner
  • Publication number: 20080129177
    Abstract: The system and method provided herein for limiting the effects of arcing in field-type electron emitter arrays improves the robustness of such arrays. Field-type electron emitter arrays generally have a substrate, an insulator, and a gating electrode. By including a resistive substance in the gate of the emitter array, arcing events may be isolated to a single emitter such that the remaining emitters of an array can continue electron emission and/or the short circuit current of the arc can be limited.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventors: Colin R. Wilson, Ji-Ung Lee
  • Patent number: 7381578
    Abstract: A method according to the present invention is for electrifying a plurality of electric conductors arranged on a substrate including the step of setting an average temperature difference during electrifying processing between a region S0 in that the plurality of electric conductors on the substrate are arranged and a circumferential region S1 of the region S0 at 15° C. or more, and the substrate satisfies the relational expression: L1/L0>E??T/?th?1. where L0[m]: the width of the region S0 L1[m]: the width of the region S1 ?T[K]: the average temperature difference E[Pa]: the Young's modulus of the substrate ?[/K]: the coefficient of linear thermal expansion of the substrate ?th[Pa]: the material constant of the substrate.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: June 3, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisanobu Azuma
  • Patent number: 7368306
    Abstract: It is an object to provide techniques for forming a field emission device of a field emission display device with the use of an inexpensive large-sized substrate according to the process that enables improving productivity. A field emission device according to the present invention includes a cathode electrode formed on an insulating surface of a substrate and a convex electron emission portion formed at a surface of the cathode electrode, and the cathode electrode and the electron emission portion include the same semiconductor film. The electron emission portion has a conical shape or a whiskers shape.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: May 6, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Yukie Nemoto
  • Patent number: 7368305
    Abstract: A method of fabricating high aspect ratio micromechanical tips is provided. The method includes, but is not limited to, forming an etchant protective island on a surface of a silicon substrate with the silicon substrate exposed around the island; isotropically etching the silicon substrate by reactive ion etching around the protective island to partially undercut the silicon substrate beneath the protective island; anisotropically etching, by deep reactive ion etching, the silicon surrounding the island to a desired depth to define a tip shaft of the desired height supported at a base by the substrate; removing the protective island from the tip; and sharpening the top of the tip shaft to an apex. Using the method, micromechanical tips having heights greater than at least 30 ?m have been obtained while maintaining the vertical sidewall necessary for both AFM and scanning near-field microwave microscopy (SNMM) profiling applications.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: May 6, 2008
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Daniel W. van der Weide, Yaqiang Wang
  • Patent number: 7364924
    Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: April 29, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Fengyan Zhang, Gregory M. Stecker, Robert A. Barrowcliff
  • Patent number: 7354781
    Abstract: A method of manufacturing a field emission device (FED) using a photoresist for performing multi-patterning processes, whereby different structures can be multi-patterned using a single photoresist mask. The photoresist has a solubility to a solvent by post-exposure heat-treatment, and a complicated structure can be formed using the photoresist.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: April 8, 2008
    Assignees: Samsung SDI Co., Ltd., E.I. Du Pont De Nemours and Company
    Inventors: Shang-Hyeun Park, Young-Hwan Kim
  • Patent number: 7354780
    Abstract: A method for producing an optical output, including the following steps: providing first and second electrical signals; providing a bipolar light-emitting transistor device that includes collector, base, and emitter regions; providing a collector electrode coupled with the collector region and an emitter electrode coupled with the emitter region, and coupling electrical potentials with respect to the collector and emitter electrodes; providing an optical coupling in optical communication with the base region; providing first and second base electrodes coupled with the base region; and coupling the first and second electrical signals with the first and second base electrodes, respectively, to produce an optical output emitted from the base region and coupled into the optical coupling, the optical output being a function of the first and second electrical signals.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: April 8, 2008
    Assignee: The Board of Trustees of The University of Illinois
    Inventors: Milton Feng, Nick Holonyak, Jr., Richard Chan
  • Patent number: 7329552
    Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device includes a transistor configured to control the emission of electrons from an emitter.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: February 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Ji Ung Lee, John Lee, Benham Moradi
  • Patent number: 7322287
    Abstract: Improved apparatus for imprint lithography involves using direct fluid pressure to press a mold into a substrate-supported film. Advantageously the mold and/or substrate are sufficiently flexible to provide wide area contact under the fluid pressure. Fluid pressing can be accomplished by sealing the mold against the film and disposing the resulting assembly in a pressurized chamber. The result of this fluid pressing is enhanced resolution and high uniformity over an enlarged area.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: January 29, 2008
    Assignee: Nanonex Corporation
    Inventors: Hua Tan, Linshu Kong, Mingtao Li, Stephen Y. Chou
  • Patent number: 7320897
    Abstract: A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: January 22, 2008
    Assignee: Sharp Laboratories of Amrica, Inc.
    Inventors: Sheng Teng Hsu, Tingkai Li, Wei-Wei Zhuang
  • Publication number: 20070284573
    Abstract: This invention relates to a process for fabricating ZnO nanowires with high aspect ratio at low temperature, which is associated with semiconductor manufacturing process and a gate controlled field emission triode is obtained. The process comprises providing a semiconductor substrate, depositing a dielectric layer and a conducting layer, respectively, on the semiconductor substrate, defining the positions of emitter arrays on the dielectric layer and conducting layer, depositing an ultra thin ZnO film as a seeding layer on the substrate, growing the ZnO nanowires as the emitter arrays by using hydrothermal process, and etching the areas excluding the emitter arrays, then obtaining the gate controlled field emission triode.
    Type: Application
    Filed: December 20, 2006
    Publication date: December 13, 2007
    Applicant: National Chiao Tung University
    Inventors: Tseung-Yuen Tseng, Chia-Ying Lee, Seu-Yi Li, Pang Lin
  • Publication number: 20070254389
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Min OH, Jeong-Nam HAN, Chang-Ki HONG, Kun-Tack LEE, Dae-Hyuk KANG, Sung-Il CHO
  • Patent number: 7288419
    Abstract: In a microstructure: minute pores are formed at a surface of a substrate in such a manner that the minute pores are dispersedly distributed over the surface, and the gaps between the minute pores are 1 micrometer or smaller; minute metal particles are arranged at the minute pores and have such sizes that the minute metal particles can cause localized plasmon resonance; the minute metal particles have head portions protruding from the surface; and the diameters of the head portions are greater than the diameters of the minute pores. In Raman spectrometry, a specimen material is absorbed by the surface from which the head portions protrude, light is applied to the surface, and a spectrum of scattered light is obtained.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: October 30, 2007
    Assignee: FujiFilm Corporation
    Inventor: Masayuki Naya
  • Patent number: 7285428
    Abstract: In a production method of an electron source wherein a plurality of electron-emitting devices are connected by and driven by matrix wirings, the upper wiring of the matrix wiring is partially removed at a short circuit region at a cross portion between the matrix wirings, thereby removing the short circuit and effectively repairing an electrical connecting relation of the matrix wirings.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: October 23, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Patent number: 7271018
    Abstract: A semiconductor die package having an elastomeric substrate with a first support frame and a second support frame. The first support frame has a cavity within which a semiconductor die is placed. The second support frame may have an optional cavity. The optional cavity in the second support frame may have an optional rigid structure. The rigid structure may have a heating element formed within it.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Gregory M. Chapman
  • Patent number: 7271017
    Abstract: An electroluminescent display device includes first and second substrates facing each other, data and gate lines crossing each other on the first substrate to define a plurality of pixel regions, a switching transistor connected to the gate and data lines, a driving transistor connected to the switching transistor, a dummy pattern on the first substrate, a connection electrode on the dummy pattern and connected to the driving transistor, a power line connected to the driving transistor, and an emitting diode on the second substrate and connected to the connection electrode.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: September 18, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Jae-Yong Park
  • Patent number: 7268004
    Abstract: An active matrix display that does not require a transistor or similar current switching device at each pixel. Instead, the display employs in each pixel a temperature-controlled current source that provides to the field emitters of the pixel an amount of electrical current which varies in response to the temperature of a temperature sensor. Each pixel further includes a thermoelectric heat transfer circuit which transfers heat to or from the sensor in an amount which varies in response to the video signal. Consequently, the video signal controls the temperature of the sensor within a pixel's temperature-controlled current source, which controls the current flow through the pixel's field emitters.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventor: John K. Lee
  • Patent number: 7264978
    Abstract: A field emission type cold cathode, comprising a substrate having a conductivity at least on the surface thereof, an insulation layer formed on the substate and having a first opening part, a gate electrode layer formed on the insulation layer, having a center generally aligned with the center of the first opening part, and having, therein, a second opening part having an opening diameter larger than the opening diameter of the first opening part, and an emitter layer formed in the first opening part, the emitter layer characterized by further comprising the bottom surface and the side surfaces of the first opening part.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: September 4, 2007
    Assignee: NEC Corporation
    Inventor: Fuminori Ito
  • Patent number: 7259029
    Abstract: A method for forming a protective structure of active matrix triode field emission device is provided. The method comprises the steps of forming a silicon active region; depositing a gate oxide layer over the silicon active region; depositing and patterning a first metal layer over the gate oxide layer; doping impurities into portions of the said silicon active region to form a source/drain in a first conductive type and simultaneously to form a diode having a terminal in the first conductive type; forming ILD layer over the first metal layer and forming a plurality of contact holes thereon; depositing and patterning a second metal layer; forming a passivation layer over the second metal layer and forming a plurality of via holes thereon, depositing and patterning a third metal layer to form a gate and a tip structure.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: August 21, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Huai-Yuan Tseng, Chun-Tao Lee
  • Publication number: 20070166849
    Abstract: A method of manufacturing a member with concave portions includes preparing a base material, forming a mask formation film on the base material, forming a number of openings in the mask formation film by laser irradiation treatments using a branching filter, and etching the base material to form the concave portions in the base material. The branching filter branches laser light into first laser beams and second laser beams. Each of irradiation regions of the mask formation film sequentially is subjected to the laser irradiation treatment, so that first openings are formed by the first laser beams and second openings are formed by the second laser beams. Each of the irradiation regions has portions where no opening is formed by the first beams of the laser irradiation treatment for the irradiation region while openings will be formed by the second laser beams in one or more of the subsequent laser irradiation treatments.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 19, 2007
    Inventors: Nobuo Shimizu, Kazuto Yoshimura
  • Patent number: 7220984
    Abstract: The influence of surface geometry on metal properties is studied within the limit of the quantum theory of free electrons. It is shown that a metal surface can be modified with patterned indents to increase the Fermi energy level inside the metal, leading to decrease in electron work function. This effect would exist in any quantum system comprising fermions inside a potential energy box. Also disclosed is a method for making nanostructured surfaces having perpendicular features with sharp edges.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: May 22, 2007
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Stuart Harbron
  • Patent number: 7214553
    Abstract: The invention relates to a process for the controlled growth of nanotubes or nanofibers on a substrate, characterized in that it furthermore comprises the production, on the substrate (11), of a bi-layer structure composed of a layer of catalyst material (71), for catalyzing the growth of nanotubes or nanofibers, and a layer of associated material, said associated material being such that it forms a noncatalytic alloy with the catalyst material at high temperature. The invention also relates to a process for fabricating a field-emission cathode using the above nanotube or nanofiber fabrication process. These processes allow very precise positioning of the catalyst spots from which the nanotubes and nanofibers can be grown and allow the fabrication of cathodes for which the nanotubes or nanofibers are self-aligned with the aperture in the extraction grid. Applications: electron tubes, nanolithography.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: May 8, 2007
    Assignee: Thales
    Inventors: Pierre Legagneux, Gilles Pirio, Didier Pribat, William Ireland Milne, Kenneth Boh Khin Teo
  • Patent number: 7214117
    Abstract: The present invention relates to a deflector of a micro-column electron beam apparatus and method for fabricating the same, which forms a seed metal layer and a mask layer on both sides of a substrate, and exposes some of the seed metal layer on which deflecting plates, wirings and pads are to be formed by lithography process using a predetermined mask. The wirings and pads are formed by plating metal on the exposed portion, and some of the metal layer is also exposed on which the deflecting plates are to be formed using a predetermined mask, and then the metal is plated with desired thickness, thereby the deflecting plates are completed. Therefore, by forming plurality of deflecting plates on both sides of the substrate at the same time through plating process, alignment between the deflecting plates formed on both sides of the substrate can be exactly made, and by fabricating a deflector integrated with the substrate and deflecting plates in a batch process, productivity and reproducibility is improved.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: May 8, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Kuk Choi, Dae Yong Kim, Dong Yel Kang
  • Patent number: 7202181
    Abstract: Fabrication of a light emitting device includes etching of a substrate of the light emitting device. The etch may be an aqueous etch sufficient to increase an amount of light extracted through the substrate. The etch may be a direct aqueous etch of a silicon carbide substrate. The etch may remove damage from the substrate that results from other processing of the substrate, such as damage from sawing the substrate. The etch may remove an amorphous region of silicon carbide in the substrate.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: April 10, 2007
    Assignee: Cres, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 7198966
    Abstract: A method for producing a durable electron-emitting device having a uniform electron emission characteristic, an electron source, and an image-forming apparatus having a uniform display characteristic for a long period are provided. The method for producing an electron-emitting device according to the present invention includes the steps of: disposing a cathode electrode on a surface of a substrate; providing an electrode opposite the cathode electrode; disposing plural pieces of fiber containing carbon as a main component on the cathode electrode; and applying potential higher than potential applied to the cathode electrode under depressurized condition to an electrode opposite the cathode electrode.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: April 3, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kitamura, Takeo Tsukamoto
  • Patent number: 7195943
    Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: March 27, 2007
    Assignee: Sony Corporation
    Inventors: Motohiro Toyota, Ichiro Saito, Toshiki Shimamura, Masakazu Muroyama
  • Patent number: 7195938
    Abstract: Particles, which may include nanoparticles, are mixed with carbon nanotubes and deposited on a substrate to form a cold cathode. The particles enhance the field emission characteristics of the carbon nanotubes. An additional activation step may be performed on the deposited carbon nanotube mixture to further enhance the emission of electrons.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: March 27, 2007
    Assignee: Nano-Proprietary, Inc.
    Inventors: Zvi Yaniv, Richard Lee Fink, Mohshi Yang, Dongsheng Mao
  • Patent number: 7175714
    Abstract: An electrode-built-in susceptor comprises a mounting plate and a supporting plate which are made of an aluminium-nitride-group-sintered member, an inner electrode which is made of a conductive aluminium-nitride-tantalum-nitride-composite-sintered-member or a conductive aluminium-nitride-tungsten-composite-sintered-member so as to be formed between the mounting plate and the supporting plate, power supplying terminals 16, 16 which is disposed in fixing holes 13, 13 which are formed on the supporting plate so as to be attached to the inner electrode. The power supplying terminals are made of a conductive aluminium-nitride-tantalum-nitride-composite-sintered-member. By doing this, it is possible to provide an electrode-built-in susceptor which has superior durability under a high temperature oxidizing atmosphere condition and a method for manufacturing an electrode-built-in susceptor with a high product yield and a low production cost.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: February 13, 2007
    Assignee: Sumitomo Osaka Cement Co., Ltd.
    Inventors: Takeshi Ootsuka, Kazunori Endou
  • Patent number: 7169628
    Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: January 30, 2007
    Assignee: Sony Corporation
    Inventors: Motohiro Toyota, Ichiro Saito, Toshiki Shimamura, Masakazu Muroyama