Abstract: A method for fabricating field emission arrays employs a single mask to define emitter tips, their corresponding resistors, and, optionally, conductive lines. One or more material layers from which the emitter tips and resistors will be defined are formed over and laterally adjacent substantially parallel conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. The emitter tips and underlying resistors are then defined. Substantially longitudinal center portions of the conductive lines may be exposed between adjacent lines of emitter tips, with at least a lateral edge portion of each conductive line being shielded by material that remains following the formation of the emitter tips and resistors. The exposed portions of the conductive lines may be removed in order to define conductive traces. Field emission arrays and display devices fabricated by such methods are also disclosed.

Abstract: A plurality of kinds of ink jet devices (109 and 110) are properly used for regions. For element electrode pairs (2 and 3) arranged in the vicinity of the fixed position of a spacer (91), for example, there is used an ink jet device (109) having an excellent performance such as a drop placement accuracy or a drop volume accuracy. For the remaining element electrode pairs (2 and 3), there are used ink jet devices (110) having an inferior performance. As a result, an electron source substrate of a high quality can be manufactured at a low cost and in a high throughput.

Abstract: Nanotip arrays are formed by exposing a substrate to a process gas mixture that simultaneously forms nanomasks on the substrate surface and etches exposed portions of the substrate surface to form the nanotip array. Components of the process gas mixture form nanocrystallites on the surface of the substrate, thereby masking portions of the substrate from other components of the process gas mixture, which etch exposed portions of the substrate. Accordingly, nanotip arrays formed using this technique can have nanocrytallite endpoints.

Abstract: A method is provided for forming a device. The method provides a substrate, and provides a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.

Abstract: A method is disclosed for creating an emitter having a flat cathode emission surface: First a protective layer that is conductive is formed on the flat cathode emission surface. Then an electronic lens structure is created over the protective layer. Finally, the protective layer is etched to expose the flat cathode emission surface.

Abstract: An InAsP active region for a long wavelength light emitting device and a method for growing the same are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium arsenide phosphide (InAsP) film, forming a quantum well layer of InAsP, and forming a barrier layer adjacent the quantum well layer, where the quantum well layer and the barrier layer are formed at a temperature of less than 520 degrees C. Forming the quantum well layer and the barrier layer at a temperature of less than 520 degrees C. results in fewer dislocations by suppressing relaxation of the layers. A long wavelength active region including InAsP quantum well layers and InGaP barrier layers is also disclosed.

Abstract: A method of fabricating a layered structure including a substrate, a first semiconductor layer with a first thermal expansion coefficient &agr;A, and a second semiconductor layer with a second thermal expansion coefficient &agr;B deposited on the first semiconductor layer, wherein &agr;Ais greater than &agr;B or smaller than &agr;B, includes: forming the first semiconductor layer, the second semiconductor layer, and a third semiconductor layer with a third thermal expansion coefficient &agr;C in this order on the substrate at a first temperature using a film deposition technique such as MOCVD, thereby forming a structural body including the substrate and the first to third semiconductor layers, wherein &agr;C is greater than &agr;B if &agr;A is greater than &agr;B or &agr;C is smaller than &agr;B if &agr;A is smaller than &agr;B; cooling the structural body to a second temperature, which is lower than the first temperature; and removing the third semiconductor layer from the structural body to expose the seco

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pad and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed.

Abstract: A method for fabricating a field emission structure is disclosed. A first dielectric layer and a second material layer are disposed over a substrate and at least one emitter tip thereon. Planarization of the second layer exposes regions of the first layer that cover the emitter tip, which regions may then be removed through the second layer. Substantially Substantial removal of the second layer reduces any conductive defects that protrude from a surface of the first layer. A third, dielectric layer and fourth, grid layer are then formed. Planarization of the fourth layer forms grid openings and exposes dielectric material of the third layer which overlies the emitter tip. Dielectric material of one or both underlying layers may then be removed to expose the outer surfaces of the emitter tip.

Abstract: A cathode structure for a field emission device, which is an essential component of a field emission device, and a method of fabricating the same are provided. An emitter material for electron emission constituting cathodes is formed in a particulate emitter, the particulate emitter is formed of a material from which electrons can be easily emitted at a low electric field. A significant advantage of the present invention over a conventional art is that the present invention patterns an emitter material to a cathode electrode using a photolithography process or a lift-off process. In the lift-off process, the emitting compound is patterned using a sacrifice layer. Also, in another embodiment of the present invention, there is disclosed a method of easily fabricating cathodes for a triode-type field emission device using a particulate emitter material at a low process temperature.

Abstract: A method is disclosed for the induction of a suitable band gap and electron emissive properties into a substance, in which the substrate is provided with a surface structure corresponding to the interference of electron waves. Lithographic or similar techniques are used, either directly onto a metal mounted on the substrate, or onto a mold which then is used to impress the metal. In a preferred embodiment, a trench or series of nano-sized trenches are formed in the metal.

Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads which have a core and a spacer coating are dispensed as a hexagonally-packed monolayer onto a thermo-adhesive layer, which is on a target layer. The beads are kept in place by a bead confinement wall. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.

Abstract: At least a lower cladding layer, an active layer for generating laser light, a first upper cladding layer, an etching stopper layer and a second upper cladding layer are stacked on a substrate. An impurity for restraining laser light absorption is diffused into the second upper cladding layer along a region where a light-emitting end surface is to be formed, under a condition that allows the etching stopper layer to maintain a function of stopping etching for the second upper cladding layer (First annealing process). Etching is performed until the etching stopper layer is reached such that the second upper cladding layer is left in a ridge shape. The impurity in the second upper cladding layer is re-diffused into the active layer to thereby cause local intermixing of the active layer in a portion extending along the light-emitting end surface and located just under the ridge (Second annealing process).

Abstract: A method for etching a metal layer on a scale of nano meters, includes preparing a substrate on which a metal layer is formed, positioning a micro tip over the metal layer, generating an electron beam from the micro tip by applying a predetermined voltage between the metal layer and the micro tip, and etching the surface of the metal layer into a predetermined pattern with the electron beam. Accordingly, it is possible to form an etched pattern by applying a negative bias to a micro tip without applying a strong mechanical force to the micro tip, and heating/melting the metal layer with the use of an electron beam emitted from the micro tip which is negative-biased.

Abstract: A method of manufacturing wiring includes a step of forming a conductive layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and a conductive material, a step of forming an insulating layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and an insulating material, and a baking step for baking the conductive layer pattern and the insulating layer pattern. Thus, a wiring pattern can be formed with high precision by reducing an edge curl.

Abstract: Systems and methods are described for carbon tips with expanded bases. A method includes producing an expanded based carbon containing tip including: fabricating a carbon containing expanded base on a substrate; and then fabricating a carbon containing fiber on the expanded base. An apparatus includes a carbon containing expanded base coupled to a substrate; and a carbon containing fiber coupled to said carbon containing expanded base.

Abstract: A field emitter having a high current density even at a low voltage using a carbon nanotube film, a method of manufacturing the same, and a field emission display device having the field emitter, are provided, The field emitter includes an insulating substrate. a thin film transistor formed on the insulating substrate, the thin film transistor having a semiconductor layer, a source electrode, a drain electrode and a gate electrode, and an electron emitting unit formed of a carbon nanotube film on the drain electrode of the thin film transistor The thin film transistor can be a coplanar-type transistor, a stagger-type transistor, or an inverse stagger-type transistor. The surface of a portion of the drain electrode, which contacts the carbon nanotube film, contains catalytic metal which is transition metal such as nickel or cobalt. Alternatively, the drain electrode itself can be formed of catalytic metal for carbon nanotube growth.

Abstract: A CMOS imager having an epitaxial layer formed below pixel sensor cells is disclosed. An epitaxial layer is formed between a semiconductor substrate and a photosensitive region to improve the cross-talk between pixel cells. The thickness of the epitaxial layer is optimized so that the collection of signal carriers by the photosensitive region is maximized.

Abstract: An active matrix current source controlled gray level tunable FED. The inventive FED uses active devices to convert a voltage-controlled signal into an output current and a capacitor to record and hold the voltage-controlled signal, thereby producing a low control voltage and active current source driving FED. As such, adjustment and maintenance of the gray level brightness of the FED is achieved because the brightness fixed by the active devices and the capacitor can obtain a high transient brightness when the FED operates in a lower voltage and brightness, thereby producing a high average brightness and avoiding an arc from high-voltage operation or poor vacuum.

Abstract: A method for fabricating row lines over a field emission array employs only two mask steps to define row lines and pixel openings. A layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material and a layer of passivation material is disposed over the layer of conductive material. Row lines and pixel openings may be formed through the passivation and conductive layers by use of a first mask. The row lines may be further defined by using a second mask to remove semiconductive material of the grid. Alternatively, a first mask may be used to fully define row lines from the layers of passivation, conductive, and semiconductive material, while a second mask may be used to define pixel openings through the layers of passivation and conductive material. Field emission arrays fabricated by such methods are also disclosed.

Abstract: An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.

Abstract: A process is provided for forming sharp asperities useful as field emitters. The process comprises patterning and doping a silicon substrate. The doped silicon substrate is anodized. The anodized area is then used for field emission tips. The process of the present invention is also useful for low temperature sharpening of tips fabricated by other methods. The tips are anodized, and then exposed to radiant energy and the resulting oxide is removed.

Abstract: A fieldless CMOS image sensor that include a non-LOCOS isolation structure surrounding the photodiode diffusion region of each pixel. The isolation structure is formed by an anti-punchthrough (APT) implant isolation region formed in the substrate around the photodiode diffusion region, and spacer oxide that is formed using a special mask to cover the APT implant region. The APT implant isolation region is self-aligned with the special spacer oxide mask. A width of the isolation structure between two adjacent photodiodes is 0.5 &mgr;m or more. Similarly, LOCOS structures that are used, for example, in the image sensor active circuitry, are separated from the image-sensing (e.g., photodiode) region of each pixel by portions of the isolation structure having a width of 0.5 &mgr;m or more.

Abstract: A method for fabricating tiny field emitter tips across the surface of a substrate. A substrate is first exposed to reactive molecular, ionic, or free radical species to produce nanoclusters within a thin surface layer of the substrate. The substrate may then be thermally annealed to produce regularly sized and interspaced nanoclusters. Finally, the substrate is etched to produce the field emitter tips.

Abstract: A method for fabricating a thin-film edge emitter device includes the steps of providing a first conductive layer having a top surface; providing an insulating layer having a top surface disposed above the top surface of the first conductive layer; providing a second conductive layer on the insulating layer; and providing a well in the insulating layer over the first conductive layer and an edge in the second conductive layer proximate the well. Providing the well and the edge includes processing the first conductive, insulating, and second conductive layers by at least one of lift-off processing, photolithography processing, and processing with the use of a pre-formed insulating layer having at least one opening associated with a location of the well. The first conductive layer forms an anode. Lastly, the second conductive layer forms at least one of a cladded cathode having an emissive edge and a control electrode.

Abstract: An improved optical modulator and photodetector suitable for high frequency operation and compatible with monolithic microwave integrated circuit technology. Typical implementations use a reversed biased diode containing not intentionally doped (NID) optically active region sandwiched between conductive layers of p-doped and n-doped semiconductor layers, respectively. With monochromatic optical radiation incident upon the device a photocurrent (comprising of an electron-hole pair created for each photon absorbed) can be generated using the optical nonlinearity of the multiple quantum well structure inside the active region. This photocurrent can be used in an external circuit to provide photocurrent feedback to the device itself.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: A method of sharpening a tapered or pointed silicon structure, such as a silicon field emitter. The method includes oxidizing the silicon field emitter to form an oxide layer thereon and removing the oxide layer. Oxidizing occurs at a low temperature and forms a relatively thin (e.g., about 20 Å to about 40 Å) oxide layer on the silicon field emitter. The oxide layer may be removed by etching. The method may be employed to sharpen existing silicon structures or in fabricating tapered or pointed silicon structures. A silicon field emitter that has been sharpened or fabricated in accordance with the method is substantially free of crystalline defects and includes an emitter tip having a diameter as small as about 40 Å to about 20 Å or less.

Abstract: A method for fabricating a field emission structure is disclosed. A first dielectric layer and a second material layer are disposed over a substrate and at least one emitter tip thereon. Planarization of the second layer exposes regions of the first layer that cover the emitter tip, which regions may then be removed through the second layer. Substantially removal of the second layer reduces any conductive defects that protrude from a surface of the first layer. A third, dielectric layer and fourth, grid layer are then formed. Planarization of the fourth layer forms grid openings and exposes dielectric material of the third layer which overlies the emitter tip. Dielectric material of one or both underlying layers may then be removed to expose the outer surfaces of the emitter tip.

Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.

Abstract: An improved nanotip structure and method for forming the nanotip structure and a display system using the improved nanotip structure is described. The described nanotip is formed from a semiconductor having a crystalline structure such as gallium nitride. The crystalline structure preferably forms dislocations oriented in the direction of the nanotips. One method of forming the nanotip structure uses the relatively slow etching rates that occur around the dislocations compared to the faster etch rates that occur in other parts of the semiconductor structure. The slower etching around dislocations enables the formation of relatively high aspect ratio nanotips in the dislocation area.

Abstract: An improved nanotip structure and method for forming the nanotip structure and a display system using the improved nanotip structure is described. The described nanotip is formed from a semiconductor having a crystalline structure such as gallium nitride. The crystalline structure preferably forms dislocations oriented in the direction of the nanotips. One method of forming the nanotip structure uses the relatively slow etching rates that occur around the dislocations compared to the faster etch rates that occur in other parts of the semiconductor structure. The slower etching around dislocations enables the formation of relatively high aspect ratio nanotips in the dislocation area.

Abstract: The present invention relates to a method of forming a small gap using CMP and a method for manufacturing a lateral FED. In the present invention, a small gap is determined by the thickness of an oxide film, and so uniform small gaps of about 100 Å that have been impossible to attain with the art of prior lithography can be formed with repeatability. Prior lateral field emission devices have the problem of repeatability in forming a gap for field emission because they are fabricated by means of a thermal stress method or an electrical stress method. But if the method of forming a small gap according to the present invention is used to fabricate a lateral FED, a FED can be made that has low voltage drive and high current drive characteristics and uniform field emission characteristics.

Abstract: A field emitter cell includes a thin-film-edge emitter normal to the gate layer. The field emitter cell may include a conductive substrate layer, an insulator layer having a perforation, a gate layer having a perforation, an emitter layer, and other optional layers. The perforation in the gate layer is larger and concentrically offset with respect to the perforation in the insulating layer and may be of a tapered construction. Alternatively, the perforation in the gate layer may be coincident with, or larger or smaller than, the perforation in the insulating layer, provided that the gate layer is shielded from the emitter from a direct line-of-sight by a nonconducting standoff layer. Optionally, the thin-film-edge emitter may include incorporated nanofilaments. The field emitter cell has low gate current, making it useful for various applications such as field emitter displays, high voltage power switching, microwave, RF amplification and other applications that require high emission currents.

Abstract: An n-GaN layer is provided as an emitter layer for supplying electrons. A non-doped (intrinsic) AlxGa1−xN layer (0≦x≦1) having a compositionally graded Al content ratio x is provided as an electron transfer layer for transferring electrons toward the surface. A non-doped AlN layer having a negative electron affinity (NEA) is provided as a surface layer. Above the AlN layer, a control electrode and a collecting electrode are provided. An insulating layer formed of a material having a larger electron affinity than that of the AlN layer is interposed between the control electrode and the collecting electrode. This provides a junction transistor which allows electrons injected from the AlN layer to conduct through the conduction band of the insulating layer and then reach the collecting electrode.

Abstract: Particles, which may include nanoparticles, are mixed with carbon nanotubes and deposited on a substrate to form a cold cathode. The particles enhance the field emission characteristics of the carbon nanotubes. An additional activation step may be performed on the deposited carbon nanotube mixture to further enhance the emission of electrons.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: An extraction grid for field emitter tip structures and method of forming are described. A conductive layer is deposited over an insulative layer formed over the field emitter tip structures. The conductive layer is milled using ion milling. Owing to topographical differences along an exposed surface of the conductive layer, ions strike the exposed surface at various angles of incidence. As etch rate from ion milling is dependent at least in part upon angle of incidence, a selectivity based on varying topography of the exposed surface (“topographic selectivity”) results in non-uniform removal of material thereof. In particular, portions of the conductive layer in near proximity to the field emitter tip structures are removed faster than portions of the conductive layer between emitter tip structures. Thus, portions of the insulative layer in near proximity to the field emitter tip structures may be exposed while leaving intervening portions of the conductive layer for forming the extraction grid.

Abstract: A method for producing a field emission display, especially for producing a carbon nanotube field emission display, is invented. The invention is to produce a field emission display via different control media, e.g. diode or triode field emission arrays. In addition, the invention discloses the procedure of controlling the field emission array of carbon nanotube stably by thin film transistor technology, and provides the method of producing the collimated carbon nanotube.

Abstract: A manufacturing method for an electron-emitting source of triode structure, including forming a cathode layer on a substrate, forming a dielectric layer on the cathode layer, and positioning an opening in the dielectric layer to expose the cathode layer, wherein the opening has a surrounding region, forming a gate layer on the dielectric layer, except on the surrounding region, forming a hydrophilic layer in the opening, forming a hydrophobic layer on the gate layer and the surrounding region, wherein the hydrophobic layer contacts the ends of the hydrophilic layer, dispersing a carbon nanotube solution on the hydrophilic layer using ink jet printing, executing a thermal process step, and removing the hydrophobic layer. According to this method, carbon nanotubes are deposited over a large area in the gate hole.

Abstract: In one aspect, the invention includes a method of forming field emission emitter tips, comprising: a) providing a masking material over a semiconductor substrate to form a masking-material-covered substrate; b) submerging at least a portion of the masking-material-covered semiconductor substrate in a liquid; c) providing particulates suspended on an upper surface of the liquid; d) while the particulates are suspended, moving the submerged masking-material-covered substrate relative to the suspended particulates to form tightly packed monolayer of the particulates supported on the masking material of the masking-material-covered substrate; e) decreasing a dimension of the particulates to leave some portions of the masking material covered by the particulates and other portions of the masking material uncovered by the particulates; f) after decreasing the dimension and while the particulates are supported on the upper surface, exposing the masking-material-covered substrate to first etching conditions which rem

Abstract: Field emission transistors where either N type or P type devices are made with an insulated gate isolated from both the emitter and the collector. Such devices have input voltage levels that match the output levels, and as such are fully cascadable and integrable. Emitter and collector functions are combined in combinations to make complimentary pairs, NAND gates and NOR gates.

Abstract: An electronic device has an alloy layer containing magnesium oxide and at least one of zinc oxide and cadmium oxide and having a cubic structure on a substrate. The alloy layer may be directly on the substrate or, alternatively, one or more buffer layers may be between the alloy layer and the substrate. The alloy layer may be domain-matched epitaxially grown directly on the substrate, or may be lattice-matched epitaxially grown directly on the buffer layer. The cubic layer may also be used to form single and multiple quantum wells. Accordingly, electronic devices having wider bandgap, increased binding energy of excitons, and/or reduced density of growth and/or misfit dislocations in the active layers as compared with conventional III-nitride electronic devices may be provided.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multilayer work piece having different layers formed of the same material, or it may be a single layer of material. The process can be used to manufacture a base structure for a conical cathode emitter tip.

Abstract: A method of forming emitter tips for use in a field emission display. A dielectric layer, an insulating layer, and a conductor layer are formed on a substrate in sequence. An annular groove is formed the conductive layer and the insulating layer. A tip cavity with an insulating tip within is formed by isotropic wet etching. A molybdenum metal layer is formed on the insulating tip. The method of the present invention can substantially reduce the consumption of molybdenum.

Abstract: An electron source 10 has an n-type silicon substrate 1, a drift layer 6 formed on one surface of the substrate 1, and a surface electrode 7 formed on the drift layer 6. A voltage is applied so that the surface electrode 7 becomes positive in polarity relevant to the substrate 1, whereby electrons injected from the substrate 1 into the drift layer 6 drift within the drift layer 6, and are emitted through the surface electrode 7. In a process for manufacturing this electron source 10, when the drift layer 6 is formed, a porous semiconductor layer containing a semiconductor nanocrystal is formed in accordance with anodic oxidation. Then, an insulating film is formed on the surface of each semiconductor nanocrystal. Anodic oxidation is carried out while emitting light that essentially contains a wavelength in a visible light region relevant to the semiconductor layer.

Abstract: A field emission array (FEA) using carbon nanotubes having characteristics of low work function, durability and thermal stability, and a method for fabricating the same are provided. The field emission array uses carbon nanotubes as electron emission sources, thereby lowering a work function and dropping driving voltage. Accordingly, a device can be driven at low voltage. In addition, resistance to gases, which are generated during the operation of a device, is improved, thereby increasing the life span of an emitter. The method prints a mixed paste using extrusion or screen printing and performs sintering, thereby fusing carbon nanotubes such that the carbon nanotubes are aligned in a single direction.

Abstract: A method of reducing electronic work function, reducing threshold field emission values, converting semiconducting behavior to metallic behavior, increasing the electron density state at the Fermi level, and increasing electron emission site density, of nanostructure or nanotube-containing material, the method including: forming openings in the nanotube-containing material; introducing a foreign species such as an alkali metal into at least some of the openings; and closing the openings, thereby forming capsules filled with the foreign species, and forming field emission cathode and flat panel displays using these capsules.

Abstract: To attain an increase in production speed and suitable for mass production in a substrate processing operation such as film formation requiring a hermetic atmosphere. A substrate processing method for performing a predetermined processing on a substrate is provided, which includes the steps of: arranging a surface of the substrate to be processed in a hermetic atmosphere; evacuating said hermetic atmosphere; and performing a predetermined processing on the substrate, in which the processing step is conducted after moving the evacuated hermetic atmosphere from the station for evacuation to a ifferent station.

Abstract: A microcathode which integrates both an electron emitter, or cathode, and an extractor electrode. The electron emitter is attached to the back side of a thin film microstructure on a first surface of a substrate. Electrons are emitted from the electron emitter and into a via extending through the substrate. An electron beam is formed which is pulled through the via and out of the microcathode by an extractor electrode on a second surface of the substrate. The extractor electrode modulates the electron beam current, defines the beam profile, and accelerates the electrons toward an anode located outside of the microcathode. Microcathode of this invention are particularly suitable as electron emitting devices useful for various types of electron beam utilizing equipment such as flat cathode ray tube displays, microelectronic vacuum tube amplifiers, electron beam exposure devices and the like.