Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.

Abstract: Disclosed is a field effect transistor including an insulating film disposed between a source/drain region and a substrate. Since the insulating film prevents current leakage under a channel, it is not necessary to form a punch-through stopper. Further disclosed is a method of forming a field effect transistor.

Abstract: A three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a top surface of a substrate and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, and each of the insulating layers contains a metal-organic framework (MOF) material portion. The MOF material portion has a low dielectric constant, and reduces RC coupling between the electrically conductive layers. An optional airgap may be located within the MOF material portion to further reduce the effective dielectric constant. Optionally, discrete charge storage regions or floating gates may be formed only at the levels of the electrically conductive layers to reduce program disturb and noise in the device.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode. The second insulating cover layer has an oxygen getter property.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process in a process chamber. The atomic layer deposition process includes alternately and sequentially introducing a first precursor gas and a second precursor gas over the sidewall of the gate stack to form the sealing layer. The second precursor gas has a different atomic concentration of carbon than that of the first precursor gas. The atomic layer deposition process also includes removing a reaction byproduct from the process chamber after the first precursor gas is introduced and before the second precursor gas is introduced. The method also includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.

Abstract: A semiconductor device includes a field effect transistor including: a semiconductor substrate including a channel forming region; a gate insulating film formed at the channel forming region on the semiconductor substrate; a gate electrode formed over the gate insulating film; a first stress application layer formed over the gate electrode and applying stress to the channel forming region; a source/drain region formed on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and a second stress application layer formed over the source/drain region in a region other than at least a region of the first stress application layer and applying stress different from the first stress application layer to the channel forming region.

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

Abstract: One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate contact opening that exposes at least a portion of a front face of the conductive source/drain metallization structure and a portion of an upper surface of a gate structure of the gate. In this example, the method further includes forming an internal insulating spacer within the gate contact opening that is positioned on and in contact with the exposed portion of the front face, wherein the spacer leaves at least a portion of the upper surface of the gate structure exposed, and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

Abstract: In one aspect, organic thin film transistors are described herein. In some embodiments, an organic thin film transistor comprises a source terminal, a drain terminal and a gate terminal; a dielectric layer positioned between the gate terminal and the source and drain terminals; and a vibrationally-assisted drop-cast organic film comprising small molecule semiconductor in electrical communication with the source terminal and drain terminal, wherein the transistor has a carrier mobility (?eff) of at least about 1 cm2/V·s.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gates over a semiconductor fin. An interlayer dielectric is formed around and between the dummy gates. The dummy gates are etched away, leaving gate voids. A first planarizing material is deposited in and over the gate voids. The first planarizing material is removed in a gate cut region. A gate cut plug is deposited in the gate cut region. The remaining first planarizing material is removed to expose the gate voids outside of the gate cut region. A gate stack is formed in the gate voids outside of the gate cut region.

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

Abstract: A semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. The semiconductor device may include: a substrate; a fin-shaped first semiconductor layer spaced apart from the substrate; a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer; an isolation layer formed on the substrate, exposing at least a part of the second semiconductor layer, wherein the exposed part of the second semiconductor layer extends in a fin shape; and a gate stack formed on the isolation layer and intersecting the second semiconductor layer.

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

Abstract: A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

Abstract: A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.

Abstract: A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

Abstract: A method for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It further comprises subsequently performing at least twice the following cycle: applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are positioned in proximity to each other such that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After performing the cycle at least twice, the overall pattern is transferred to the substrate.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

Abstract: Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film.

Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

Abstract: An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate trench. After forming the n-typed work function metal layer, a nitridation process is performed to form a first protecting layer on the n-typed work function metal layer. After forming the first protecting layer, an oxidation process is performed to the first protecting layer to form a second protecting layer on the n-typed work function metal layer. Then, a gap filling metal layer is formed to fill up the first gate trench.

Abstract: A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.

Abstract: A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening.

Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.

Abstract: Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor.

Abstract: A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.

Abstract: A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

Abstract: A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

Abstract: A method of forming transistors and structures thereof. A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS device may be doped with either an n type or a p type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.