Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) Patents (Class 438/199)
  • Patent number: 11322601
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Tahir Ghani, Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11322598
    Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.
    Type: Grant
    Filed: June 21, 2020
    Date of Patent: May 3, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: YI-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 11315796
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a substrate having a first region, second regions and third regions; and forming a patterned structure on the substrate. The patterned structure includes at least one first patterned layer on the first region, at least one second patterned layer on the second region and at least one third patterned layer on the third region, the at least one first patterned layer is discrete from the at least one second region and the at least one second region is discrete from the at least one third region. The method also includes removing the second patterned layer; and etching the substrate using the first patterned layer and the third patterned layer as an etching mask to form a base substrate, the first fin on the base substrate and the third fin on the base substrate.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 26, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11302794
    Abstract: An embodiment of the invention may include a method for of forming a semiconductor device and the resulting device. The method may include forming a gate dielectric on a gate region of a substrate. The method may include forming an inner dummy gate on a first portion of the gate dielectric. The method may include forming an outer dummy gate adjacent to the inner dummy gate on a second portion of the gate dielectric. The method may include forming spacers adjacent to the outer dummy gate. The method may include removing the outer dummy gate and depositing a first work function metal. The method may include removing the inner dummy gate and depositing a second work function metal.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Takashi Ando, Alexander Reznicek, Pouya Hashemi
  • Patent number: 11289339
    Abstract: A plasma processing method executed by a plasma processing apparatus includes a first step, a second step, and an etching step. In the first step, the plasma processing apparatus forms a first film on a processing target in which a plurality of openings having a predetermined pattern are formed. In the second step, the plasma processing apparatus forms a second film having an etching rate lower than that of the first film on the processing target on which the first film is formed, and having different film thicknesses on the side surfaces of the openings according to the sizes of the openings. In the etching step, the plasma processing apparatus performs etching from above the second film under a predetermined processing condition until a portion of the first film is removed from at least a portion of the processing target.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 29, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masahiro Tabata
  • Patent number: 11245022
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M. Bernal Ramos, Luping Li, Shih Chung Chen, Jacqueline S. Wrench, Yixiong Yang, Steven C. H. Hung, Srinivas Gandikota, Naomi Yoshida, Lin Dong
  • Patent number: 11231326
    Abstract: This infrared imaging element includes: a substrate which has a front surface and a back surface and to which a circuit unit is provided; a support leg wiring line that is disposed above the front surface of the substrate; and an infrared-ray detection unit which is held on the support leg wiring line and to which a diode electrically connected to the circuit unit via the support leg wiring line is provided, wherein the temperature change of the infrared-ray detection unit is detected as an electrical signal change of the diode by the circuit unit. The substrate, the support leg wiring line, and the infrared-ray detection unit are laminated at intervals in a direction perpendicular to the front surface of the substrate.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 25, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tomohiro Maegawa
  • Patent number: 11189705
    Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a first metal gate stack disposed over the stack of semiconductor layers, a second metal gate stack interleaved between the stack of semiconductor layers, a source/drain (S/D) feature disposed in the stack of semiconductor layers, and an S/D contact disposed over the S/D feature. In many examples, the S/D feature is separated from a sidewall of the second metal gate stack by a first air gap and the S/D contact is separated from a sidewall of the first metal gate stack by a second air gap.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11171575
    Abstract: A Modular Multilevel Converter (MMC) circuit for converting DC power to AC and vice versa. At each respective connection to the AC power-source/load, the MMC circuit uses one Pulse Width Modulation Insulated Gate Bipolar Transistor (PWM IGBT) to control the switching between upper and lower arms of sub-modules. The circuit eliminates the inter-phase inductors often used in MMCs, and replaces the inductors by two complementary-gated PWM IGBTs, thereby eliminating circulating current. Moreover, the multilevel converter topology disclosed herein requires less number of components including PWM IGBTs and capacitors. In fact, at least two submodules per-phase are eliminated: one submodule in the upper arm and one submodule in the lower arm. In other words, the MMC topology not only mitigates the circulating current but also eliminates at least one submodule in the upper arm and at least one submodule in the lower arm per-phase.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 9, 2021
    Assignee: The Regents of the University of California
    Inventors: Keith Corzine, Vahid Dargahi
  • Patent number: 11152354
    Abstract: A bipolar junction transistor, a BiCMOS device including same, and a method of manufacturing the BiCMOS device are disclosed. To fabricate the BiCMOS device, a bipolar region and a CMOS region are on a lightly doped substrate to enhance isolation between devices. First-conductivity-type deep well regions are in the bipolar region and/or the CMOS region to prevent well-to-substrate diffusion.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: October 19, 2021
    Assignee: DB HiTek Co., Ltd.
    Inventors: Hyun-Jin Kim, Sang-Gil Kim, Seung-Hyun Eom, Yong-Jin Kim
  • Patent number: 11139271
    Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Min Kim, Dae Won Ha
  • Patent number: 11139213
    Abstract: Methods for 3D fabrication of source/drain regions in different stacks of 3D transistors in which multiple planes are fabricated simultaneously are described. The methods allow any sequence of 3D source/drains to be made to customize the logic layout for a given 3D logic circuit or design. Examples are described of forming a stacked SRAM device, a dual stacked SRAM device and a plurality of stacked inverters based on NMOS and PMOS field effect transistors.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 5, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11087984
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first material and a second material on a semiconductor substrate. The first material is different from the second material. The method also includes heating the first material to a first temperature and the second material to a second temperature with a laser beam. The first temperature is different from the second temperature. The method also includes depositing a third material on the first material.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Christine Y Ouyang
  • Patent number: 11081393
    Abstract: A method of splitting a semiconductor wafer includes: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and/or a passivation layer over the plurality of device structures; attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device structures.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Christian Beyer, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Marko Swoboda
  • Patent number: 11049869
    Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 29, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideaki Yamakoshi, Shinichiro Abe, Takashi Hashimoto, Yuto Omizu
  • Patent number: 11049858
    Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Michael P. Belyansky
  • Patent number: 11018232
    Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Lin, Peng-Soon Lim, Zi-Wei Fang
  • Patent number: 11018160
    Abstract: A thin-film transistor substrate includes a pixel circuit, an interlayer insulating film, electrodes, and a hard mask metal. The pixel circuit includes a thin film transistor. The interlayer insulating film has contact holes and covers the pixel circuit. The electrodes are exposed above a surface of the interlayer insulating film, and electrically coupled to the pixel circuit via the contact holes. The hard mask metal has openings at portions facing the contact holes and is provided on the surface of the interlayer insulating film.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 25, 2021
    Assignee: JOLED INC.
    Inventors: Ryosuke Ebihara, Yasuhiro Terai, Atsuhito Murai
  • Patent number: 10993044
    Abstract: The present invention provides a MEMS device such as a capacitive MEMS microphone that comprises a new design of air flow restrictor having a pair of continuous looped insert and trench. An air channel/space includes a first internal wall and a second internal wall for air to flow between. A continuous looped trench is recessed from the first internal wall, and a continuous looped insert is extended from the second internal wall and inserted into the trench. The spatial relationship between the insert and the trench can vary or oscillate. Air resistance of the channel/space may be controlled by the trench's depth. The invention has a significant effect on, for example, keeping the sound frequency response plot more flat on the low frequency part ranging from 20 Hz to 1000 Hz.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: April 27, 2021
    Assignee: GMEMS TECH SHENZHEN LIMITED
    Inventors: Guanghua Wu, Xingshuo Lan
  • Patent number: 10950725
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Hsueh-Chang Sung
  • Patent number: 10930757
    Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Arnaud Regnier, Dann Morillon, Franck Julien, Marjorie Hesse
  • Patent number: 10921314
    Abstract: Methods of making an integrated circuit for a single-molecule nucleic-acid assay platform. In one example, the method includes adhering a carbon nanotube to a surface of a transfer film, the transfer film comprising gold or a polymer; placing the surface of the transfer film on a CMOS integrated circuit; releasing the carbon nanotube from the transfer film; and forming a pair of post-processed electrodes proximate opposing ends of the carbon nanotube, the post-processed electrodes electrically connecting the carbon nanotube to the CMOS integrated circuit. The method can also include exposing the carbon nanotube to a diazonium salt solution to form a point defect on a portion of the carbon nanotube.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 16, 2021
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Kenneth L. Shepard, Steven Warren, Scott Trocchia, Yoonhee Lee, Erik Young
  • Patent number: 10896891
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yu Suzuki, Shoko Kikuchi, Merii Inaba, Jun Murakami, Takashi Shigeoka, Hiroshi Inagaki, Takashi Okuhata
  • Patent number: 10867867
    Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chung-Wei Hsu, Lung-Kun Chu, Jia-Ni Yu, Chih-Hao Wang, Mao-Lin Huang
  • Patent number: 10861953
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10818767
    Abstract: A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The semiconductor device includes a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line. The gate electrode stack includes a work function layer covering the sidewall and the bottom surface of the metal filling line. The gate electrode stack includes a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer. The capping layer includes TaC and at least one of TiN or TaN. The gate electrode stack includes a barrier layer interposed between the capping layer and the sidewalls of the work function layer. The barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsueh Wen Tsau
  • Patent number: 10797173
    Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 10763259
    Abstract: A semiconductor device manufacturing method is presented. The manufacturing method includes providing a semiconductor structure, comprising: a substrate, a plurality of semiconductor fins comprising a first semiconductor fin and a second semiconductor fin on the substrate, a plurality of trenches surrounding the semiconductor fins, and a first insulation layer filling the trenches; conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein; removing at least a portion of the first insulation layer from the trenches; forming a second insulation layer filling a portion of the trenches not filled by the first insulation layer; and conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein. This inventive concept reduces the chance of a dopant in the first doping process diffusing into the second semiconductor fin.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 1, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10748819
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, SangHoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10734523
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
  • Patent number: 10720425
    Abstract: An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Alain Loiseau
  • Patent number: 10714615
    Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
  • Patent number: 10672882
    Abstract: A semiconductor device includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the semiconductor region and the gate electrode and containing a material having a chemical composition expressed by (SiO2)n (Si3N4)m (wherein n and m are positive integers), in the material, at least one silicon atom being bonded with at least one oxygen atom and at least one nitrogen atom.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 2, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito
  • Patent number: 10636895
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10607540
    Abstract: Provided are a display panel and a display device. A pixel circuit in the disclosed display panel includes a driving module, a data writing module, a storage module, and at least one control module. The data writing module is configured to write a data signal into a control terminal of the driving module. The storage module is electrically connected to the control terminal of the driving module for maintaining a voltage on the control terminal of the driving module in an emit-lighting phase. The control module is electrically connected to the control terminal of the driving module for writing a signal into the control terminal of the driving module prior to the light-emitting stage. At least one hollowed structure is provided on the continuous gate structure of the control transistor of the control module. At least one channel's width-to-length ratio is different from others among the overlapping portions' channels.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 31, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Kerui Xi, Tingting Cui, Baiquan Lin, Junting Ouyang, Ruiyuan Zhou
  • Patent number: 10600783
    Abstract: A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10600912
    Abstract: A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10586739
    Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 10573723
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, SangHoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10546788
    Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Jie Yang
  • Patent number: 10529712
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate in a direction perpendicular to an upper surface of the substrate, the fin structure including first fin regions extending in a first direction and second fin regions extending in a second direction different from the first direction, source/drain regions disposed on the fin structure, a gate structure intersecting the fin structure, a first contact connected to one of the source/drain regions, and a second contact connected to the gate structure and being between the second fin regions in plan view.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim
  • Patent number: 10505003
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10488265
    Abstract: An camera, the camera including: an photosensitive device and an image processor, wherein the photosensitive device includes a plurality of photosensitive units, a measuring device and a data processor; the plurality of photosensitive units are distributed in an array, wherein each photosensitive unit is configured to receive and convert light signal to form a temperature difference or a potential difference; the measuring device is configured to measure the temperature difference or the potential difference; a data processor is configured to analyze and calculate the potential difference or the temperature difference.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 26, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ling Zhang, Yang Wu, Kai-Li Jiang, Chang-Hong Liu, Jia-Ping Wang, Shou-Shan Fan
  • Patent number: 10475808
    Abstract: A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction into the substrate from a surface thereof. The multi-layers stack includes a plurality of conductive layers and a plurality of insulating layers alternatively stacked along the first direction on a bottom of the concave portion. The multi-layers stack also has at least one recess passing through the conductive layers and the insulating layers along the first direction, wherein the recess has a cross-sectional bottom profile and a cross-sectional opening profile perpendicular to the first direction and the cross-sectional bottom profile has a size substantially greater than that of the cross-sectional opening profile. The dielectric material is at least partially filled in the recess.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Jia-Rong Chiou
  • Patent number: 10475708
    Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yong-Liang Li, Hao Su
  • Patent number: 10461186
    Abstract: Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Ruilong Xie, Mahender Kumar
  • Patent number: 10460996
    Abstract: A fin field effect transistor (FinFET) and a method for fabricating the FinFET are provided. The method includes providing a plurality of discrete fins on a semiconductor substrate, and forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins. The method also includes forming an interlayer dielectric layer, covering the dummy gate and the fins, and forming an opening in the interlayer dielectric layer. In addition, the method includes forming a gate dielectric layer in the opening and on the interlayer dielectric layer, and forming a barrier layer on the gate dielectric layer. Moreover, the method includes removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer, and performing an annealing treatment. Further, the method includes removing the barrier layer in the opening, and forming a metal gate in the opening.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 29, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10446652
    Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming gate structures on the base substrate; forming source/drain doped regions in the base substrate on sides of each gate structure, where the source/drain doped regions have recessed top surfaces and are doped with source/drain ions; and doping into the recessed top surfaces of the source/drain doped regions with contact ions to form contact doped regions in top portions of the source/drain doped regions, where the contact ions have a conductivity type same as the source/drain ions.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: October 15, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10439023
    Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 8, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
  • Patent number: RE48942
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng