Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) Patents (Class 438/199)
  • Patent number: 10950725
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Hsueh-Chang Sung
  • Patent number: 10930757
    Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Arnaud Regnier, Dann Morillon, Franck Julien, Marjorie Hesse
  • Patent number: 10921314
    Abstract: Methods of making an integrated circuit for a single-molecule nucleic-acid assay platform. In one example, the method includes adhering a carbon nanotube to a surface of a transfer film, the transfer film comprising gold or a polymer; placing the surface of the transfer film on a CMOS integrated circuit; releasing the carbon nanotube from the transfer film; and forming a pair of post-processed electrodes proximate opposing ends of the carbon nanotube, the post-processed electrodes electrically connecting the carbon nanotube to the CMOS integrated circuit. The method can also include exposing the carbon nanotube to a diazonium salt solution to form a point defect on a portion of the carbon nanotube.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 16, 2021
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Kenneth L. Shepard, Steven Warren, Scott Trocchia, Yoonhee Lee, Erik Young
  • Patent number: 10896891
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yu Suzuki, Shoko Kikuchi, Merii Inaba, Jun Murakami, Takashi Shigeoka, Hiroshi Inagaki, Takashi Okuhata
  • Patent number: 10867867
    Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chung-Wei Hsu, Lung-Kun Chu, Jia-Ni Yu, Chih-Hao Wang, Mao-Lin Huang
  • Patent number: 10861953
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10818767
    Abstract: A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The semiconductor device includes a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line. The gate electrode stack includes a work function layer covering the sidewall and the bottom surface of the metal filling line. The gate electrode stack includes a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer. The capping layer includes TaC and at least one of TiN or TaN. The gate electrode stack includes a barrier layer interposed between the capping layer and the sidewalls of the work function layer. The barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsueh Wen Tsau
  • Patent number: 10797173
    Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 10763259
    Abstract: A semiconductor device manufacturing method is presented. The manufacturing method includes providing a semiconductor structure, comprising: a substrate, a plurality of semiconductor fins comprising a first semiconductor fin and a second semiconductor fin on the substrate, a plurality of trenches surrounding the semiconductor fins, and a first insulation layer filling the trenches; conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein; removing at least a portion of the first insulation layer from the trenches; forming a second insulation layer filling a portion of the trenches not filled by the first insulation layer; and conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein. This inventive concept reduces the chance of a dopant in the first doping process diffusing into the second semiconductor fin.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 1, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10748819
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, SangHoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10734523
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
  • Patent number: 10720425
    Abstract: An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Alain Loiseau
  • Patent number: 10714615
    Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
  • Patent number: 10672882
    Abstract: A semiconductor device includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the semiconductor region and the gate electrode and containing a material having a chemical composition expressed by (SiO2)n (Si3N4)m (wherein n and m are positive integers), in the material, at least one silicon atom being bonded with at least one oxygen atom and at least one nitrogen atom.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 2, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito
  • Patent number: 10636895
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10607540
    Abstract: Provided are a display panel and a display device. A pixel circuit in the disclosed display panel includes a driving module, a data writing module, a storage module, and at least one control module. The data writing module is configured to write a data signal into a control terminal of the driving module. The storage module is electrically connected to the control terminal of the driving module for maintaining a voltage on the control terminal of the driving module in an emit-lighting phase. The control module is electrically connected to the control terminal of the driving module for writing a signal into the control terminal of the driving module prior to the light-emitting stage. At least one hollowed structure is provided on the continuous gate structure of the control transistor of the control module. At least one channel's width-to-length ratio is different from others among the overlapping portions' channels.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 31, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Kerui Xi, Tingting Cui, Baiquan Lin, Junting Ouyang, Ruiyuan Zhou
  • Patent number: 10600783
    Abstract: A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10600912
    Abstract: A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10586739
    Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 10573723
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, SangHoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10546788
    Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Jie Yang
  • Patent number: 10529712
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate in a direction perpendicular to an upper surface of the substrate, the fin structure including first fin regions extending in a first direction and second fin regions extending in a second direction different from the first direction, source/drain regions disposed on the fin structure, a gate structure intersecting the fin structure, a first contact connected to one of the source/drain regions, and a second contact connected to the gate structure and being between the second fin regions in plan view.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim
  • Patent number: 10505003
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10488265
    Abstract: An camera, the camera including: an photosensitive device and an image processor, wherein the photosensitive device includes a plurality of photosensitive units, a measuring device and a data processor; the plurality of photosensitive units are distributed in an array, wherein each photosensitive unit is configured to receive and convert light signal to form a temperature difference or a potential difference; the measuring device is configured to measure the temperature difference or the potential difference; a data processor is configured to analyze and calculate the potential difference or the temperature difference.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 26, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ling Zhang, Yang Wu, Kai-Li Jiang, Chang-Hong Liu, Jia-Ping Wang, Shou-Shan Fan
  • Patent number: 10475808
    Abstract: A 3D memory device includes a substrate, a multi-layers stack and a dielectric material. The substrate has a concave portion extending along a first direction into the substrate from a surface thereof. The multi-layers stack includes a plurality of conductive layers and a plurality of insulating layers alternatively stacked along the first direction on a bottom of the concave portion. The multi-layers stack also has at least one recess passing through the conductive layers and the insulating layers along the first direction, wherein the recess has a cross-sectional bottom profile and a cross-sectional opening profile perpendicular to the first direction and the cross-sectional bottom profile has a size substantially greater than that of the cross-sectional opening profile. The dielectric material is at least partially filled in the recess.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Jia-Rong Chiou
  • Patent number: 10475708
    Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yong-Liang Li, Hao Su
  • Patent number: 10460996
    Abstract: A fin field effect transistor (FinFET) and a method for fabricating the FinFET are provided. The method includes providing a plurality of discrete fins on a semiconductor substrate, and forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins. The method also includes forming an interlayer dielectric layer, covering the dummy gate and the fins, and forming an opening in the interlayer dielectric layer. In addition, the method includes forming a gate dielectric layer in the opening and on the interlayer dielectric layer, and forming a barrier layer on the gate dielectric layer. Moreover, the method includes removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer, and performing an annealing treatment. Further, the method includes removing the barrier layer in the opening, and forming a metal gate in the opening.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 29, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10461186
    Abstract: Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Ruilong Xie, Mahender Kumar
  • Patent number: 10446652
    Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming gate structures on the base substrate; forming source/drain doped regions in the base substrate on sides of each gate structure, where the source/drain doped regions have recessed top surfaces and are doped with source/drain ions; and doping into the recessed top surfaces of the source/drain doped regions with contact ions to form contact doped regions in top portions of the source/drain doped regions, where the contact ions have a conductivity type same as the source/drain ions.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: October 15, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10435292
    Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claus Waechter, Edward Fuergut, Bernd Goller, Michael Ledutke, Dominic Maier
  • Patent number: 10439023
    Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 8, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
  • Patent number: 10431652
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee
  • Patent number: 10403714
    Abstract: A semiconductor device includes a semiconductor substrate, first and second device fins extending from the semiconductor substrate, and a fill fin disposed on the semiconductor substrate and between the first and second device fins, wherein the fill fin has an opening. The semiconductor device further includes a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10388644
    Abstract: A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang, Ko-Bin Kao, Ru-Gun Liu, Shun Li Chen
  • Patent number: 10388531
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 10355109
    Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thamarai Selvi Devarajan, Sanjay C. Mehta, Eric R. Miller, Soon-Cheon Seo
  • Patent number: 10355020
    Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 16, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10332902
    Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunghwan Son, Jaesung Sim, Shinhwan Kang, Youngwoo Park, Jaeduk Lee
  • Patent number: 10325919
    Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a stack of gate dielectric precursor layers is formed on a plurality of logic sub-region and is then selectively removed from at least two logic sub-regions. Then, a gate dielectric precursor layer is formed, and a plasma treatment process and an annealing process are subsequently performed. The gate dielectric precursor layer is then selectively removed from a low-voltage logic sub-region, but not a high-voltage logic sub-region. By removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region prior to performing the plasma treatment process and the annealing process, less gate dielectric precursor material is treated, annealed, and removed from the low-voltage logic sub-region. Thus, the resulting residues are reduced, and the defects introduced by the residues are also reduced or eliminated.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Feng Teng, Wei Cheng Wu
  • Patent number: 10256295
    Abstract: A semiconductor device includes an outside-of-well n-type region, a p-type well region surrounded by the outside-of-well n-type region, an inside-of-well n-type region, and a gate electrode. The outside-of-well n-type region includes an impurity low-concentration region that is in contact with the p-type well region, and an impurity high-concentration region that is separated from the p-type well region by the impurity low-concentration region.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masahiro Kawakami, Tomohiko Mori, Hiroyuki Ueda
  • Patent number: 10236293
    Abstract: A substrate having a silicon region and a silicon germanium region is provided. A first set of fins in the silicon region and a second set of fins in the silicon germanium region is etched into the substrate. A set of protective caps on upper portions of the first and second sets of fins. A lower portion of each of the first and second sets of fins is oxidized. The silicon germanium portion of the lower portion of fin in the second set of fins is completely oxidized. The lower portion of the first set of fins is partially oxidized. A punchthrough stop isolation region is formed in the lower portion of the first set of fins.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S Basker, Kangguo Cheng, Theodorus E Standaert, Junli Wang
  • Patent number: 10163915
    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Jerome Ciavatti
  • Patent number: 10164102
    Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
  • Patent number: 10153214
    Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se Jung Park, Ju-Hyun Kim, Hoyoung Kim, Boun Yoon, TaeYong Kwon, Sangkyun Kim, Sanghyun Park
  • Patent number: 10147652
    Abstract: At least one method, apparatus and system disclosed involves a semiconductor substrate on which NMOS and PMOS devices with enhanced current drives may be formed. A first substrate having an enhanced electron mobility is formed. A second substrate having an enhanced hole mobility is formed. The first substrate and the second substrate are bonded for forming a third substrate. A first channel on the third substrate characterized by the enhanced electron mobility is formed. A second channel on the third substrate characterized by the enhanced hole mobility is formed.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Srinivasa Banna
  • Patent number: 10115643
    Abstract: A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Sandeep Kumar Goel
  • Patent number: 10083985
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 25, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Patent number: 10032667
    Abstract: When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished.
    Type: Grant
    Filed: February 4, 2017
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaaki Shinohara
  • Patent number: 10032625
    Abstract: A method of making a semiconductor device includes forming a titanium nitride layer over a gate dielectric layer. The method further includes performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer. The method further includes driving silicon from the at least one silicon monolayer into the titanium nitride layer to form a TiSiON layer.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hao Hou, Xiong-Fei Yu
  • Patent number: 10002926
    Abstract: A semiconductor structure is provided that includes a fin structure of, from bottom to top, a semiconductor punch through stop (PTS) doping fin portion, a dielectric material fin portion, and a topmost semiconductor fin portion that is present on a wider semiconductor fin base. A functional gate structure straddles the semiconductor fin structure. Portions of the wider semiconductor fin base that are not located directly beneath the fin structure of the present application and that are not covered by the functional gate structure can be used as an area for epitaxial growth of source/drain structures. The wide semiconductor fin base improves source/drain epitaxy for better dopant incorporation and strain enhancement.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Alexander Reznicek