Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.

Abstract: A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.

Abstract: In some examples, a flash memory comprises a first gate and a second gate located over a semiconductor substrate a third gate located between the first gate and the second gate a floating gate located between the third gate and the semiconductor substrate; and a doped region located within the semiconductor substrate and proximate the second gate, wherein the doped region is configured to receive a positive bias voltage with respect to the semiconductor substrate during an erase cycle.

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.

Abstract: A semiconductor device includes an active region, a gate conductor and a source electrode. The active region includes a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region. The active region is formed of a silicon semiconductor layer. The gate conductor is embedded within a trench, which is formed from the source region to the drain region penetrating through the channel region. The source electrode is formed to come in contact with the source region and includes an adhesion layer. The source electrode is formed of a metal layer having a film thickness of 150 ? or smaller. The interface between the source electrode and the source region is silicidized.

Abstract: The present invention provides a polysilicon manufacturing method that controls a growth direction of polysilicon, including the following steps: (1) forming a first buffer layer (20) on a substrate (10) through deposition; (2) applying a masking operation to form a lens-like structure (22) on a surface of the first buffer layer (20); (3) depositing and forming an amorphous silicon layer (40) on the first buffer layer (20) of which the surface comprises the lens-like structure (22) formed thereon; (4) subjecting the amorphous silicon layer (40) to rinsing; (5) irradiating the amorphous silicon layer (40) with an intense light (50) from the side of the substrate (10) so as to generate a crystal seed at a bottom of the amorphous silicon layer (40); and (6) applying a laser annealing operation to the amorphous silicon layer (40) that comprises a crystal seed generated therein so as to have amorphous silicon contained in the amorphous silicon layer (40) crystallized and forming a polysilicon layer (70).

Abstract: A technique for forming nanostructures including introducing a plurality of molecular-size scale and/or nanoscale building blocks to a region near a substrate and simultaneously scanning a pattern on the substrate with an energy beam, wherein the energy beam causes a change in at least one physical property of at least a portion of the building blocks, such that a probability of the portion of the building blocks adhering to the pattern scanned by the energy beam is increased, and wherein the building blocks adhere to the pattern to form the structure. The energy beam and at least a portion of the building blocks may interact by electrostatic interaction to form the structure.

Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract: A field effect transistor (1) including: a semiconducting substrate (2) having two areas doped with electric charge carriers forming a source area (3) and a drain area (4), respectively; a dielectric layer positioned above the semiconducting substrate (2) between the source (3) and the drain (4) and forming the gate dielectric (9) of the field effect transistor (1); a gate (11) consisting of a reference electrode (8) and of a conductive solution (10), the solution (10) being in contact with the gate dielectric (9); and the gate dielectric (9) consists of a layer of lipids (13) in direct contact with the semiconducting layer (2). The invention also relates to a method for manufacturing such a field effect transistor (1) is disclosed.

Abstract: A nonvolatile semiconductor storage device including a memory cell region including a memory cell having a charge storing layer above a gate insulating film and a control electrode above the charge storing layer via an interelectrode insulating film; and a peripheral circuit region including a peripheral element having a first polysilicon and a first insulating film above the first polysilicon; wherein the charge storing layer includes a polysilicon doped with P-type impurity including a first upper region contacting the interelectrode insulating film and having a first doped layer doped with carbon or nitrogen, and at least a portion of a region below the first doped layer is neither doped with carbon nor nitrogen, and wherein the first polysilicon includes a second upper region contacting the first insulating film and having a second doped layer doped with carbon or nitrogen, the first and the second doped layers having equal thickness.

Abstract: Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.

Abstract: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.

Abstract: Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask. The methods may further include depositing a compound semiconductor layer including the first and second semiconductor materials directly onto sidewalls of the first and second semiconductor fins not covered by the mask and oxidizing the compound semiconductor layer. The oxidization process oxidizes the first semiconductor material within the compound semiconductor layer while driving the second semiconductor material within the compound semiconductor layer into the sidewalls of the first and second semiconductor fins not covered by the mask.

Abstract: A nonvolatile memory device includes a plurality of channel connection layers formed over a substrate; a first gate electrode layer filling a space between the plurality channel connection layers; a gate dielectric layer interposed between each of the channel connection layers and the first gate electrode layer; a stacked structure formed over the plurality channel connection layers and the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality second gate electrode layers, which are alternately stacked; a pair of channel layers, formed through the stacked structure and connected to each channel connection layer of the plurality of channel connection layers; and a memory layer interposed between each of the channel layers and each of the second gate electrode layers.

Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.

Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P? doped regions. Another N+ doped region, functioning as a bit line, is positioned adjacent and between the two P? doped regions on the substrate. An anti-fuse is defined over the N+ doped region. Two insulator regions are deposited over the two P? doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.

Abstract: Embodiments of the current invention describe methods of forming different types of crystalline silicon based solar cells that can be combinatorially varied and evaluated. Examples of these different types of solar cells include front and back contact silicon based solar cells, all-back contact solar cells and selective emitter solar cells. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single crystalline silicon substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.

Abstract: Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate including a protruding active area, a gate insulating layer on the active area, floating gate electrodes on the gate insulating layer, an insulating layer on the floating gate electrodes extending in a row direction, and a control gate electrode on the insulating layer extending in the row direction. The floating gate electrodes include a semiconductor layer on the gate insulating layer and a metal layer on the semiconductor layer. The width of the semiconductor layer of the floating gate electrodes in the row direction is narrower than the width of the metal layer in the row direction.

Abstract: In one embodiment, a memory device includes a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate.

Abstract: Embodiments of the current invention describe methods of forming different types of crystalline silicon based solar cells that can be combinatorially varied and evaluated. Examples of these different types of solar cells include front and back contact silicon based solar cells, all-back contact solar cells and selective emitter solar cells. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single crystalline silicon substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.

Abstract: A manufacturing method of a semiconductor element from a pattern formed body capable of attaining patterning efficiently with a high precision. The method includes a photoresist pattern formation step, a hydrophilicity imparting step and a photoresist pattern peeling step.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.

Abstract: A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.

Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.

Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.

Abstract: A method of making a uniform nanoparticle array, including performing diblock copolymer thin film self assembly over a first dielectric on silicon, creating a porous polymer film, transferring a pattern into the first dielectric, selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array.

Abstract: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.

Abstract: A method of fabricating a thin film device having conductive front and backside electrodes or contacts. Top-side cavities are first formed on a first dielectric layer, followed by the deposition of a metal layer on the first dielectric layer to fill the cavities. Defined metal structures are etched from the metal layer to include the cavity-filled metal, followed by depositing a second dielectric layer over the metal structures. Additional levels of defined metal structures may be formed in a similar manner with vias connecting metal structures between levels. After a final dielectric layer is deposited, a top surface of a metal structure of an uppermost metal layer is exposed through the final dielectric layer to form a front-side electrode, and a bottom surface of a cavity-filled portion of a metal structure of a lowermost metal layer is also exposed through the first dielectric layer to form a back-side electrode.

Abstract: A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the memory cell transistor are arranged in and on a semiconductor substrate. The impurity concentration of the source/drain diffusion layer shared by the memory cell transistor and the select transistor in each of the plurality of memory cells is set lower than the impurity concentration of the other source/drain diffusion layers in each of the memory cells.

Abstract: A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions, and a control gate electrode serving as a word line and disposed on the floating gate electrode with an interelectrode insulating film interposed therebetween. The interelectrode insulating film covers whole side portions of the floating gate electrode located in a direction different from a direction in which the word line extends, and the control gate electrode covers the side portions of the floating gate electrode located in the direction different from the direction in which the word line extends.

Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

Abstract: The present invention provides a method for making an electrode. Firstly, a conducting substrate is provided. Secondly, a plurality of nano-sized structures is formed on the conducting substrate by a nano-imprinting method. Thirdly, a coating is formed on the nano-sized structures. The nano-sized structures are configured for increasing specific surface area of the electrode.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.

Abstract: According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures. A conductive layer is formed over the first and second isolation structures and between the first and second isolation structures to form a floating gate. The conductive layer and the first isolation structure are etched to form a third trench having an upper portion and a lower portion, the upper portion having vertical sidewalls and the lower portion having sloping sidewalls. The third trench is filled with a conductive material to form a control gate.

Abstract: A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.

Abstract: Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

Abstract: A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.

Abstract: A semiconductor memory devices and a method of fabricating the same includes sequentially stacking a tunnel insulating layer, a first nano-grain film, a conductive layer for a floating gate, and a second nano-grain film over a semiconductor substrate, forming a trench by etching the second nano-grain film, the conductive layer for the floating gate, the first nano-grain film, the tunnel insulating layer, and the semiconductor substrate, gap-filling the trench with an insulating layer, thus forming an isolation layer, and forming a third nano-grain film on sidewalls of the conductive layer for the floating gate.

Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.