Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) Patents (Class 438/257)
  • Patent number: 10784280
    Abstract: According to one embodiment, a semiconductor memory device includes the following structure. First conductive layers are stacked in first direction and extends in second and third directions. The first conductive layers each includes a pair of first portions, and second and third portions. The first portions extend in second direction, is provided separately from each other in third direction and includes a metal. The second portion is provided between the first portions and includes silicon. The third portion is provided on at least one side of the second portion in second direction, extends in third direction, electrically connects the first portions and includes a metal. Memory pillars extend through the second portions in first direction. Contact plugs are respectively provided on the third portion of one of the first conductive layers.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Ohtori, Satoshi Seto, Takashi Fukushima
  • Patent number: 10756108
    Abstract: A vertical memory device includes a substrate including a first region including a cell array formed thereon and a second region surrounding the first region, the second region including a stair structure formed thereon, gate electrodes stacked on the substrate to be spaced apart from each other in a first direction vertical to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate and including a pad at an end portion thereof in the second direction, a channel extending through the gate electrodes in the first direction on the first region of the substrate, and contact plugs formed on the second region, the contact plugs extending in the first direction to contact the pads of the gate electrodes respectively.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hae-Min Lee
  • Patent number: 10741658
    Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10693059
    Abstract: Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Kisup Chung, Injo Ok, Seyoung Kim, Choonghyun Lee
  • Patent number: 10692883
    Abstract: A semiconductor memory device includes a substrate; a stacked body on the substrate and including a first stacked body formed of stacked first electrode layers and a second stacked body on the first stacked body and including a second electrode layer; a hole passing through the stacked bodies in a first direction and having a first insulator, and a channel film between the first insulator and first electrode layers and between the first insulator and second electrode layer and having first and second portions facing each other, with the first insulator placed therebetween. A first memory between the first electrode layers and the first portion and a second memory between the first electrode layers and the second portion are insulated. A third memory between the second electrode layer and the first portion and a fourth memory between the second electrode layer and the second portion are connected.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Uchiyama
  • Patent number: 10643900
    Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xinyuan Dou, Hong Yu, Zhenyu Hu, Xing Zhang
  • Patent number: 10644235
    Abstract: A reduced parasitic capacitance radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM. A PCM contact connects a PCM routing interconnect with a passive segment of the PCM, wherein the passive segment extends outward and is transverse to the heating element. A heating element contact connects a heating element routing interconnect with a terminal segment of the heating element. The heating element contact is situated cross-wise to the PCM contact. The heating element routing interconnect is situated at a different interlayer metal level relative to the PCM routing interconnect so as to achieve the reduced parasitic capacitance. The heating element routing interconnect can be situated above the heating element. Alternatively, the heating element routing interconnect can be situated below the heating element.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 5, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Patent number: 10636649
    Abstract: A method for forming a silicon oxide film on a tungsten film includes performing a first process of arranging an object to be processed in a processing container kept under a reduced pressure, the object including a tungsten film and a natural oxide film being formed on a surface of the tungsten film, performing a second process of forming a silicon seed layer by adsorbing a silicon-containing gas to the tungsten film, subsequently performing a third process of annealing the object and forming the silicon oxide film by a reaction of the natural oxide film and the silicon seed layer and subsequently performing a fourth process of forming an ALD silicon oxide film by ALD using a silicon-containing gas and an oxygen active species.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 28, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kyungseok Ko, Koji Sasaki, Toshiyuki Ikeuchi
  • Patent number: 10629753
    Abstract: A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 21, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Ankit Kumar, Chia-Hao Lee
  • Patent number: 10593673
    Abstract: A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Jingyun Zhang, Alexander Reznicek, Choonghyun Lee
  • Patent number: 10593772
    Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 17, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Julien Delalleau
  • Patent number: 10566524
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre
  • Patent number: 10566337
    Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
  • Patent number: 10536127
    Abstract: A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Yeop Kim, Jae-Jun Lee
  • Patent number: 10528862
    Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: January 7, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 10515971
    Abstract: A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 24, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ankit Kumar, Manoj Kumar, Chia-Hao Lee
  • Patent number: 10510610
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 17, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10510544
    Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ling Hsu, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Shihkuang Yang
  • Patent number: 10475993
    Abstract: In fabricating a radio frequency (RF) switch, a heat spreader is provided and a heating element is deposited. A thermally conductive and electrically insulating material is deposited over the heating element. The heating element and the thermally conductive and electrically insulating material are patterned, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A layer of an upper dielectric is deposited. A conformability support layer is optionally deposited over the upper dielectric and the thermally conductive and electrically insulating material. A phase-change material is deposited over the optional conformability support layer and the underlying upper dielectric and the thermally conductive and electrically insulating material.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 12, 2019
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, Jefferson E. Rose, David J. Howard, Michael J. DeBar, Nabil El-Hinnawy
  • Patent number: 10468259
    Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Vinod Robert Purayath, Nitin K. Ingle
  • Patent number: 10468496
    Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: November 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Hisada, Koichi Arai
  • Patent number: 10446559
    Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 15, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Chao-An Liu, Ching-Hsiang Chang, Yi-Wei Chen
  • Patent number: 10431577
    Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Kenneth W. Marr
  • Patent number: 10411139
    Abstract: Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiro Yamashita
  • Patent number: 10388605
    Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Tae Kyung Kim, Chul Young Park, Hyoung Soon Yune
  • Patent number: 10283566
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: May 7, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Tuan Pham, Mitsuteru Mushiga, Yoshihiro Ikeda, Daewung Kang, Akio Nishida
  • Patent number: 10269823
    Abstract: The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 10249629
    Abstract: The present invention provides a method for forming buried word lines. Firstly, a substrate is provided, having a plurality of shallow trench isolations disposed therein, next, a plurality of first patterned material layers are formed on the substrate, a plurality of first recesses are disposed between every two adjacent first patterned material layers, a second patterned material layer is formed in the first recesses, and using the first patterned material layers and the second patterned material layer as the protect layers, and a first etching process is then performed, to form a plurality of second recesses in the substrate.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 2, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Chieh-Te Chen, Hsien-Shih Chu
  • Patent number: 10224413
    Abstract: A radio-frequency (RF) carbon-nanotube (CNT) field effect transistor (FET) device. The device includes a source contact, a drain contact, semi-conducting CNTs positioned between the source and drain contacts, high-? gate dielectric, and a local backgate positioned below the semi-conducting CNTs, in which the local backgate is capable of RF performance and is capable of being used in a backgate burnout process used to enhance the semiconducting to metallic tube ratio of the device.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: March 5, 2019
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Joseph A. Payne, Wayne S. Miller, Monica P. Lilly, Silai V. Krishnaswamy
  • Patent number: 10211213
    Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A selection gate electrode is formed over a semiconductor substrate via a first insulation film. Over the opposite side surfaces of the selection gate electrode, second insulation films of sidewall insulation films are formed. Over the semiconductor substrate, a memory gate electrode is formed via a third insulation film having a charge accumulation part. The selection gate electrode and the memory gate electrode are adjacent to each other via the second insulation film and the third insulation film. The second insulation film is not formed under the memory gate electrode. The total thickness of the second insulation film and the third insulation film interposed between the selection gate electrode and the memory gate electrode is larger than the thickness of the third insulation film interposed between the semiconductor substrate and the memory gate electrode.
    Type: Grant
    Filed: November 22, 2015
    Date of Patent: February 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10170484
    Abstract: In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a first semiconductor material and the stack includes alternating layers of a second and the first semiconductor material. Recess(es) filled with sacrificial material are formed in certain area(s) of the stack. The stack is patterned into fins and gate-all-around (GAA) FET processing is performed. GAAFET processing includes removing sacrificial gates to form gate openings for GAAFETs and removing the second semiconductor material and any sacrificial material (if present) from the gate openings such that, within each gate opening, nanoshape(s) that extend laterally between source/drain regions remain. Gate openings for GAAFETs where sacrificial material was removed will have fewer nanoshapes than other gate openings. Thus, in the structure, some GAAFETs will have fewer channel regions and, thereby lower drive currents than others.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Ruilong Xie, Bipul C. Paul
  • Patent number: 10163721
    Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie, Peng Xu
  • Patent number: 10115721
    Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Walid M. Hafez, Peter J Vandervoorn, Chia-Hong Jan
  • Patent number: 10109631
    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
  • Patent number: 10103162
    Abstract: Provided is a vertical neuromorphic devices stacked structure comprising a main gate which is formed on a substrate and has a vertical pillar shape, a main gate insulating layer stack formed on outer side surface of the main gate; a semiconductor region formed on outer side surface of the main gate insulating layer stack, a plurality of electrode layers formed on the side surface of the semiconductor region, a plurality of control gates formed on the side surface of the semiconductor region; and a plurality of control gate insulating layer stacks which are surrounding surfaces of the control gates and are formed between the control gate and the semiconductor region, and between the control gate and the electrode layer, and wherein the electrode layers and the control gates surrounded by the control gate insulating layer stack are stacked sequentially and alternately on the side surface of the semiconductor region.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 16, 2018
    Assignee: SNU R&DB FOUNDATION
    Inventors: Jong-Ho Lee, Chul-Heung Kim, Suhwan Lim
  • Patent number: 10103160
    Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Srikant Jayanti, Fatma Arzum Simsek-Ege, Pavan Kumar Reddy Aella
  • Patent number: 10090328
    Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junggil Yang, Dong Il Bae, Geumjong Bae, Seungmin Song, Jongho Lee
  • Patent number: 10043713
    Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xinyuan Dou, Hong Yu, Zhenyu Hu, Xing Zhang
  • Patent number: 10038139
    Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chin-Chieh Yang, Chih-Yang Chang, Yu-Wen Liao
  • Patent number: 10026622
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuhiro Omura, Tsubasa Imamura, Itsuko Sakai
  • Patent number: 10020198
    Abstract: The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes forming a polysilicon stripe over a semiconductor fin, forming a nitride sidewall spacer surrounding a long side of the polysilicon stripe, forming a raised source/drain region in the semiconductor fin, and forming a carbonitride etch stop layer surrounding the nitride sidewall spacer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shiang-Bau Wang, Victor Y. Lu
  • Patent number: 9997641
    Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 12, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 9997524
    Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Tsun-Kai Tsao, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
  • Patent number: 9947864
    Abstract: In one embodiment, a method for etching a workpiece including a lower electrode and a multi-layer film disposed on the lower electrode, the multi-layer film including a first magnetic layer, a second magnetic layer, and an insulating layer interposed between the first magnetic layer and the second magnetic layer, through a mask, is provided. The method includes exposing the workpiece to plasma of first processing gas which contains first rare gas and second rare gas having an atomic number larger than that of the first rare gas, and does not contain hydrogen gas.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: April 17, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tamotsu Morimoto, Song yun Kang
  • Patent number: 9882030
    Abstract: A method for manufacturing a fin-type semiconductor device includes providing a semiconductor structure comprising a plurality of fins, and a plurality of trenches each disposed between two adjacent fins, filling each of the trenches with a spacer, and performing a first dopant implantation into the spacer to form an etch stop layer. The thus formed etch stop layer can decrease the etch rate of the HF/SiCoNi etchant towards oxide, e.g., silicon oxide, thereby reducing the spacer loss in a subsequent HF/SiCoNi etch of the dummy gate insulation layer, and improving the device performance.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 30, 2018
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 9882018
    Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: January 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jin Noh, Jae Ho Choi, Bio Kim, Kwang Min Park, Jae Young Ahn, Dong Chul Yoo, Seung Hyun Lim, Jeon Il Lee
  • Patent number: 9865332
    Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: January 9, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 9837603
    Abstract: Encapsulation of the magnetoresistive device after formation protects the sidewalls of the magnetoresistive device from degradation during subsequent deposition of interlayer dielectric material. The encapsulation also helps prevent short circuits between the top electrode of the magnetoresistive device and underlying layers within the magnetoresistive device. The encapsulation can be accomplished by depositing a layer of encapsulating material after device formation, where an etch back operation selectively removes the portions of the layer of encapsulating material other than the material on the sidewalls of the magnetoresistive device.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 5, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • Patent number: 9831258
    Abstract: A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 9825036
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the substrate; two fins extending from the substrate and through the isolation structure; a gate stack engaging channel regions of the two fins; a dielectric layer disposed over the isolation structure and adjacent to S/D regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. The lower portions of the four S/D features are surrounded at least partially by the dielectric layer. The upper portions of the four S/D features merge into two merged second S/D features with one on each side of the gate stack. Each of the two merged S/D features has a curvy top surface.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu