Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) Patents (Class 438/257)
  • Patent number: 11127729
    Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 21, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Murshed Chowdhury, Koichi Matsuno, Johann Alsmeier
  • Patent number: 11121043
    Abstract: There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 14, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Cyrille Le Royer, Yves Morand
  • Patent number: 11121042
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret
  • Patent number: 11114529
    Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang
  • Patent number: 11094578
    Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different. The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-layer stack and under the switch device. The air void is surrounded by dielectric filling material.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 17, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Li-Han Lu
  • Patent number: 11049909
    Abstract: The present disclosure provides an organic light-emitting display device that includes a substrate. A plurality of sub-pixels are arranged on the substrate, and each of the sub-pixels includes an organic light-emitting diode having a first electrode. A first bank has a plurality of first openings, and each of the first openings at least partially exposes a respective first electrode. A second bank has a plurality of second openings, and each of the second openings at least partially exposes one or more of the first electrodes. Each of a first set of the second openings exposes n first electrodes (n is a natural number equal to or greater than 1), and each of a second set of the second openings exposes m first electrodes (m is a natural number equal to or greater than 1), wherein n and m are different values.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 29, 2021
    Assignee: LG Display Co., Ltd.
    Inventor: Kanghyun Kim
  • Patent number: 11031508
    Abstract: A semiconductor device includes a source region, a drain region, a SiGe channel region, an interfacial layer, a high-k dielectric layer and a gate electrode. The source region and the drain region are over a substrate. The SiGe channel region is laterally between the source region and the drain region. The interfacial layer forms a nitrogen-containing interface with the SiGe channel region. The high-k dielectric layer is over the interfacial layer. The gate electrode is over the high-k dielectric layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Chang, Hsiang-Pi Chang, Zi-Wei Fang
  • Patent number: 11024637
    Abstract: A semiconductor device includes a semiconductor substrate and a pair of memory device structures. The semiconductor substrate includes a common source/drain region and a pair of individual source/drain regions, in which the common source/drain region is between the individual source/drain regions. The memory device structures each corresponds to one of the individual source/drain regions. Each memory device structure includes a trap storage structure, a control gate, a cap structure, and a word line. The trap storage structure is between the common source/drain region and the corresponding individual source/drain region. The control gate is over the trap storage structure. The cap structure is over the control gate, in which the cap structure comprises a nitride layer over the control gate and an oxide layer over the nitride layer. The word line is over the semiconductor substrate and laterally spaced from the control gate.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10991704
    Abstract: A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 27, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Khee Yong Lim, Kiok Boone Elgin Quek
  • Patent number: 10978341
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Patent number: 10978360
    Abstract: A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventor: Zhonghua Li
  • Patent number: 10957704
    Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
  • Patent number: 10930673
    Abstract: According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kyosuke Nanami, Kenichi Fujii
  • Patent number: 10916664
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.
    Type: Grant
    Filed: September 19, 2020
    Date of Patent: February 9, 2021
    Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: Geeng-Chuan Chern
  • Patent number: 10878922
    Abstract: A radiation detection system may include a mobile device having a flash memory. The device may monitor various characteristics of the flash memory to determine when damage to the flash memory has occurred from radiation exposure. The device may associate damage to the flash memory with a radiation dose, and determine a level of radiation to which the memory, and thus the device, has been exposed. The device also may determine a length of time and locations where the radiation exposure has occurred. If the device determines that the level of radiation exposure exceeds a threshold associated with a safe level of radiation exposure for a human user, the device may generate an alert to the user.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: December 29, 2020
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventor: Biswajit Ray
  • Patent number: 10878214
    Abstract: Provided is a complex biometric sensor. The complex biometric sensor includes a substrate including a light emitting region, a first light receiving region, and a second light receiving region, a light emitting part disposed adjacent to the substrate in the light emitting region, a color conversion layer disposed on the substrate in the light emitting region and vertically overlapping the light emitting part; a first light receiving layer disposed on the substrate in the first light receiving region, and a second light receiving layer disposed on the substrate in the second light receiving region. The light emitting part generates light of a first wavelength. The color conversion layer receives light of the first wavelength and emits the light of the first wavelength and light of the second wavelength. The first light receiving layer detects the light of the first wavelength. The second light receiving layer detects the light of the second wavelength.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: December 29, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chul Woong Joo, Seung Youl Kang, Jaehyun Moon, Seongdeok Ahn, Jae-Eun Pi, Young Sam Park, Byoung-Hwa Kwon, Sung Haeng Cho, Jeong Ik Lee, Nam Sung Cho, Su Jae Lee
  • Patent number: 10867851
    Abstract: A contact structure and semiconductor device and method of forming the same are disclosed. The contact structure includes a first metal layer and a second metal layer. The first metal layer is disposed in a first dielectric layer. The second metal layer is disposed in a second dielectric layer and extended into the first dielectric layer to electrically connect the first metal layer, wherein the first metal layer and the second metal layer include different metals.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying Lee, Hsien-Ming Tai, Jian-Ming Huang
  • Patent number: 10868193
    Abstract: A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rwik Sengupta, Mark Stephen Rodder, Joon Goo Hong, Titash Rakshit
  • Patent number: 10868187
    Abstract: In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 15, 2020
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Yung Jung Chang
  • Patent number: 10855230
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 1, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson, Bryan Schwitter, Chuanxin Lian, Rajesh Baskaran, Frank Gao
  • Patent number: 10847628
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: November 24, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Atsushi Amo
  • Patent number: 10833205
    Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 10833099
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Patent number: 10825770
    Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akitsugu Hatazaki, Hiroko Tahara, Naomi Fukumaki, Masayuki Kitamura, Takashi Ohashi
  • Patent number: 10790787
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 29, 2020
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Simon John Mahon, Allen W. Hanson, Chuanxin Lian, Frank Gao, Rajesh Baskaran, Bryan Schwitter
  • Patent number: 10784280
    Abstract: According to one embodiment, a semiconductor memory device includes the following structure. First conductive layers are stacked in first direction and extends in second and third directions. The first conductive layers each includes a pair of first portions, and second and third portions. The first portions extend in second direction, is provided separately from each other in third direction and includes a metal. The second portion is provided between the first portions and includes silicon. The third portion is provided on at least one side of the second portion in second direction, extends in third direction, electrically connects the first portions and includes a metal. Memory pillars extend through the second portions in first direction. Contact plugs are respectively provided on the third portion of one of the first conductive layers.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Ohtori, Satoshi Seto, Takashi Fukushima
  • Patent number: 10756108
    Abstract: A vertical memory device includes a substrate including a first region including a cell array formed thereon and a second region surrounding the first region, the second region including a stair structure formed thereon, gate electrodes stacked on the substrate to be spaced apart from each other in a first direction vertical to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate and including a pad at an end portion thereof in the second direction, a channel extending through the gate electrodes in the first direction on the first region of the substrate, and contact plugs formed on the second region, the contact plugs extending in the first direction to contact the pads of the gate electrodes respectively.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hae-Min Lee
  • Patent number: 10741658
    Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10693059
    Abstract: Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Kisup Chung, Injo Ok, Seyoung Kim, Choonghyun Lee
  • Patent number: 10692883
    Abstract: A semiconductor memory device includes a substrate; a stacked body on the substrate and including a first stacked body formed of stacked first electrode layers and a second stacked body on the first stacked body and including a second electrode layer; a hole passing through the stacked bodies in a first direction and having a first insulator, and a channel film between the first insulator and first electrode layers and between the first insulator and second electrode layer and having first and second portions facing each other, with the first insulator placed therebetween. A first memory between the first electrode layers and the first portion and a second memory between the first electrode layers and the second portion are insulated. A third memory between the second electrode layer and the first portion and a fourth memory between the second electrode layer and the second portion are connected.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Uchiyama
  • Patent number: 10643900
    Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xinyuan Dou, Hong Yu, Zhenyu Hu, Xing Zhang
  • Patent number: 10644235
    Abstract: A reduced parasitic capacitance radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM. A PCM contact connects a PCM routing interconnect with a passive segment of the PCM, wherein the passive segment extends outward and is transverse to the heating element. A heating element contact connects a heating element routing interconnect with a terminal segment of the heating element. The heating element contact is situated cross-wise to the PCM contact. The heating element routing interconnect is situated at a different interlayer metal level relative to the PCM routing interconnect so as to achieve the reduced parasitic capacitance. The heating element routing interconnect can be situated above the heating element. Alternatively, the heating element routing interconnect can be situated below the heating element.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 5, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Patent number: 10636649
    Abstract: A method for forming a silicon oxide film on a tungsten film includes performing a first process of arranging an object to be processed in a processing container kept under a reduced pressure, the object including a tungsten film and a natural oxide film being formed on a surface of the tungsten film, performing a second process of forming a silicon seed layer by adsorbing a silicon-containing gas to the tungsten film, subsequently performing a third process of annealing the object and forming the silicon oxide film by a reaction of the natural oxide film and the silicon seed layer and subsequently performing a fourth process of forming an ALD silicon oxide film by ALD using a silicon-containing gas and an oxygen active species.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 28, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kyungseok Ko, Koji Sasaki, Toshiyuki Ikeuchi
  • Patent number: 10629753
    Abstract: A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 21, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Ankit Kumar, Chia-Hao Lee
  • Patent number: 10593673
    Abstract: A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Jingyun Zhang, Alexander Reznicek, Choonghyun Lee
  • Patent number: 10593772
    Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 17, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Julien Delalleau
  • Patent number: 10566524
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre
  • Patent number: 10566337
    Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
  • Patent number: 10536127
    Abstract: A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Yeop Kim, Jae-Jun Lee
  • Patent number: 10528862
    Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: January 7, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 10515971
    Abstract: A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 24, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ankit Kumar, Manoj Kumar, Chia-Hao Lee
  • Patent number: 10510544
    Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ling Hsu, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Shihkuang Yang
  • Patent number: 10510610
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 17, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10475993
    Abstract: In fabricating a radio frequency (RF) switch, a heat spreader is provided and a heating element is deposited. A thermally conductive and electrically insulating material is deposited over the heating element. The heating element and the thermally conductive and electrically insulating material are patterned, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A layer of an upper dielectric is deposited. A conformability support layer is optionally deposited over the upper dielectric and the thermally conductive and electrically insulating material. A phase-change material is deposited over the optional conformability support layer and the underlying upper dielectric and the thermally conductive and electrically insulating material.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 12, 2019
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, Jefferson E. Rose, David J. Howard, Michael J. DeBar, Nabil El-Hinnawy
  • Patent number: 10468259
    Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Vinod Robert Purayath, Nitin K. Ingle
  • Patent number: 10468496
    Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: November 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Hisada, Koichi Arai
  • Patent number: 10446559
    Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 15, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Chao-An Liu, Ching-Hsiang Chang, Yi-Wei Chen
  • Patent number: 10431577
    Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Kenneth W. Marr
  • Patent number: 10411139
    Abstract: Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiro Yamashita
  • Patent number: 10388605
    Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Tae Kyung Kim, Chul Young Park, Hyoung Soon Yune