Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) Patents (Class 438/257)
  • Patent number: 11923427
    Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Wei-Cheng Wu, Te-Hsin Chiu
  • Patent number: 11915751
    Abstract: A method for forming a nonvolatile PCM logic device may include providing a PCM film component having a first end contact distally opposed from a second end contact, positing a first proximity adjacent to a first surface of the PCM film component, positing a second proximity heater adjacent to a second surface of the PCM film component, wherein the first proximity heater and the second proximity heater are electrically isolated from the PCM film component. The method may further include applying a combination of pulses to one or more of the first proximity heater and the second proximity heater to change a resistance value of the PCM film component corresponding to a logic truth table. Further, the method may include simultaneously applying a first combination of reset pulses to program, or set pulses to initialize, the PCM film component, to the first proximity heater and the second proximity heater.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Nanbo Gong, Takashi Ando
  • Patent number: 11916129
    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Chandra Mouli
  • Patent number: 11915967
    Abstract: The present disclosure discloses a semiconductor device manufacturing method and a semiconductor device, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate, the semiconductor substrate comprising a shallow trench and active areas isolated from the shallow trench; forming an oxygen-containing layer on exposed outer surfaces of the shallow trench and the active areas; filling a first sacrificial layer of a set height in the shallow trench comprising the oxygen-containing layer on its surface; forming an etch stop layer on an upper surface of the first sacrificial layer; removing the first sacrificial layer below the etch stop layer to form an air gap; filling an isolation layer on the etch stop layer in the shallow trench to form a shallow trench isolation(STI) structure containing the air gap; and etching the active areas and the (STI) structure to form wordline trenches.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: February 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kui Zhang, Zhan Ying
  • Patent number: 11895831
    Abstract: A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Junchao Zhang, Tao Chen
  • Patent number: 11895926
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 11889693
    Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 30, 2024
    Inventors: Srikant Jayanti, Fatma Arzum Simsek-Ege, Pavan Kumar Reddy Aella
  • Patent number: 11882696
    Abstract: A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoonsung Choi, Jinwoo Park
  • Patent number: 11871571
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: January 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 11844209
    Abstract: A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang
  • Patent number: 11839075
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: December 5, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chih-Jung Ni, Chuan-Chi Chou, Yao-Ting Tsai
  • Patent number: 11830918
    Abstract: A memory device is provided. The memory device includes a semiconductor substrate, a tunneling layer, a floating gate electrode, a dielectric layer, and a control gate electrode. The semiconductor substrate has an active region. The tunneling layer is over the active region of the semiconductor substrate. The floating gate electrode is over the tunneling layer. The floating gate electrode has a first portion and a second portion electrically connected to the first portion. The dielectric layer is over the floating gate electrode. The control gate electrode is over the dielectric layer. The control gate electrode has a first portion interposed between the first and second portions of the floating gate electrode.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Yen-Di Wang, Jia-Yang Ko, Men-Hsi Tsai
  • Patent number: 11830926
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first metal gate stack and a second metal gate stack over the semiconductor substrate. The first metal gate stack and the second metal gate stack are electrically isolated from each other, and the first metal gate stack has a curved edge facing the second metal gate stack. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Hsiao, Shu-Yuan Ku, Chih-Chang Hung, I-Wei Yang, Chih-Ming Sun
  • Patent number: 11818887
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: November 14, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Hsueh-Wei Chen, Woan-Yun Hsiao, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 11805655
    Abstract: A memory device includes a cell stacked structure on a substrate, the cell stacked structure including insulation layers and gate patterns alternately stacked, a channel structure passing through the cell stacked structure, the channel structure extending in a vertical direction, a dummy structure on the substrate, the dummy structure being spaced apart from the cell stacked structure, and the dummy structure including insulation layers and metal patterns alternately stacked, a first through via contact passing through the dummy structure, the first through via contact extending in the vertical direction, and a first capping insulation pattern between a sidewall of the first through via contact and each of the metal patterns in the dummy structure, the first capping insulation pattern insulating the first through via contact from each of the metal patterns.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghoon Kwon, Junsuk Kim, Jongheun Lim
  • Patent number: 11804484
    Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11805652
    Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia
  • Patent number: 11800820
    Abstract: A method for programming a phase change memory including a first layer of a phase change material capable of switching between a crystalline and an amorphous state and vice versa, the method including applying a programming current through the first layer so that an evolution of the areal density of this current as a function of time t decreases from a first level, between a first time and a second time, following a first evolution in time respecting, or being close to J 0 ? ( t ) = K t where K is a constant.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 24, 2023
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Gabriele Navarro, Anna-Lisa Serra, Guillaume Bourgeois, Chiara Sabbione
  • Patent number: 11791264
    Abstract: The present disclosure relates to a method for preparing a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The method includes forming a conductive layer over a semiconductor substrate, and forming a dielectric layer covering the conductive layer. The method also includes etching the dielectric layer to form an opening exposing the conductive layer, and etching the dielectric layer to form a first recess and a second recess connecting to the opening. A depth of the opening is greater than a depth of the first recess and a depth of the second recess, and the first recess and the second recess have tapering profiles that taper toward the conductive layer. The method further includes forming a conductive contact over the conductive layer. The opening, the first recess and the second recess are filled by the conductive contact.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: October 17, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11785777
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
  • Patent number: 11778830
    Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: October 3, 2023
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang
  • Patent number: 11769837
    Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Ming-Hong Su, Yung-Han Chen, Mei-Chen Su, Chia-Ming Pan
  • Patent number: 11764291
    Abstract: In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: September 19, 2023
    Assignee: SK hynix Inc.
    Inventors: Bo Yun Kim, Se Ho Lee
  • Patent number: 11758720
    Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: September 12, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Min Hung, Ping-Chia Shih, Che-Hao Kuo, Kuei-Ya Chuang, Ssu-Yin Liu, Po-Hsien Chen, Wan-Chun Liao
  • Patent number: 11749721
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, David J. Michalak, Jeanette M. Roberts
  • Patent number: 11749328
    Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 5, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11742405
    Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
  • Patent number: 11742433
    Abstract: Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: August 29, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Woo Jong Yu, Ui Yeon Won, Quoc An Vu
  • Patent number: 11729970
    Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 15, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11721728
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: August 8, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sipeng Gu, Jiehui Shu, Halting Wang, Yanping Shen
  • Patent number: 11721731
    Abstract: A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: August 8, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zar Lwin Zin, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 11716847
    Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 1, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Tingting Gao, Lei Xue, Xiaoxin Liu, Wanbo Geng
  • Patent number: 11715524
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells; and a peripheral circuit for performing a program operation and an erase operation on the memory block. The program operation is performed by using a hole injection method, and the erase operation is performed by using an electron charging method. The plurality of memory cells are programmed when a threshold voltage of each of at least some of the plurality of memory cells is decreased to be less than a set level in the program operation, and are erased when the threshold voltage of each of the plurality of memory cells is increased to be the set level or higher in the erase operation.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 1, 2023
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 11707002
    Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: July 18, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, Takashi Ando, Reinaldo Vega, Praneet Adusumilli
  • Patent number: 11688699
    Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mihir Bohra, Tarun Mudgal
  • Patent number: 11683933
    Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 20, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11682716
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
  • Patent number: 11678484
    Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: June 13, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Yao-Ting Tsai, Hsiu-Han Liao, Che-Fu Chuang
  • Patent number: 11678485
    Abstract: A vertical memory device, including: a substrate including a cell array region and an extension region; gate electrodes stacked on each other with a plurality of levels, wherein each of the gate electrodes includes a pad, and wherein the pads disposed on the gate electrodes form at least one staircase structure on the extension region of the substrate; a channel extending in a first direction on the cell array region of the substrate through at least one of the gate electrodes; and dummy gate electrode groups disposed on the extension region of the substrate, wherein the dummy gate electrode groups includes dummy gate electrodes, wherein each of the dummy gate electrodes are spaced apart from a corresponding gate electrode among the gate electrodes stacked at a same level, wherein the dummy gate electrode groups are spaced apart from each other in a second direction.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok-Cheon Baek
  • Patent number: 11672124
    Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
  • Patent number: 11672125
    Abstract: A semiconductor memory device includes a substrate including a first region, as second region, a third region and a fourth regions, the first region including a memory cell array, the second region including a circuit for controlling the memory cell array, the third region separating the first region and the second region, and the fourth region surrounding the third region, a first transistor provided in the second region, a second transistor provided in the third region between the first region and the first transistor, a third transistor provided in the third region between the first transistor and the second transistor, and a first insulating layer including a first portion disposed above the first to third transistors, and a second portion disposed in contact with the substrate between the second transistor and the third transistor.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 6, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Shigehiro Yamakita
  • Patent number: 11664070
    Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: May 30, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee
  • Patent number: 11665972
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a conductive layer in the substrate and having a surface exposed by the substrate. A groove is formed in the substrate and adjacent to the conductive layer, and a sidewall of the groove exposes a portion of a sidewall surface of the conductive layer. The semiconductor structure also includes a lower electrode layer located in the groove and on a top surface of the conductive layer. The lower electrode layer covers the top surface and the portion of the sidewall surface of the conductive layer.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: May 30, 2023
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 11658224
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A first select gate is arranged over the substrate, and a first memory gate is arranged over the substrate and separated from the source/drain region by the first select gate. An inter-gate dielectric structure is arranged between the first memory gate and the first select gate. The inter-gate dielectric structure extends under the first memory gate. A height of the inter-gate dielectric structure decreases along a direction extending from the first select gate to the first memory gate.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Patent number: 11658132
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Patent number: 11653496
    Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Chang Wan Ha, Chuan Lin, Deepak Thimmegowda, Zengtao Liu, Binh N. Ngo, Soo-yong Park
  • Patent number: 11646381
    Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: May 9, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shiangshiou Yen, Bo-An Tsai
  • Patent number: 11646363
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 11637019
    Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 25, 2023
    Inventors: Chang Sun Hwang, Han Sol Seok, Hyun Ku Kang, Byoung Ho Kwon, Chung Ki Min
  • Patent number: 11638378
    Abstract: A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: April 25, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Fu Chuang, Hsiu-Han Liao