Abstract: In one aspect of the invention, an amorphous layer of silicon is provided which has a gradient of thickness variation. The amorphous layer of silicon is transformed into a hemispherical grain polysilicon layer that has varying grain size therein. In another aspect of the invention, a material is provided and has an upper surface and inwardly tapered openings. A first electrically conductive electrode layer is formed within the openings and includes a plurality of hemispherical grain polysilicon layers. At least one of the hemispherical grain polysilicon layers has a grain size gradient defined by a smaller grain size in a region proximate the upper surface and a larger grain size beneath the region with the smaller grain size. An electrically insulative layer is formed over the first electrode layer and a second electrically conductive electrode layer is formed over the electrically insulative layer.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers are formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers are removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. The oxide is then removed, and a further oxide is re-deposited on the gate and substrate. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate.

Abstract: A semiconductor flash memory device comprises a subrate, a plurality of buried bit lines, an insulation film, a floating gate, an inter-layer insulation film, and a control gate formed on the inter-layer insulation film. The fabrication method comprises forming the patterned first insulation films on the substrate, forming the gate insulation film on the substrate and between the patterned first insulation films, depositing a first poly-silicon layer on the gate insulation film and the patterned first insulation film, forming a floating gate by etching the first poly-silicon layer, forming a second insulation film on each of the floating gate and the substrate having the buried bit lines therein, and forming a control gate on the second insulation film. The flash memory device realizes high yield rate due to the simplified fabrication steps and facilitated fabrication.

Abstract: Floating gates with field enhancement features are produced by a technique that makes possible structures smaller than the lithographically defined image. The floating gates produced having sharp tips for source-side injection flash memory cells. Moreover, the process provides an insulator cap over the floating gate that is self-aligned.

Abstract: A system and method for providing a small device formed on a semiconductor is disclosed. The method and system include controlling the surface by providing a very thin oxide layer and providing a shallow implant through the very thin oxide layer.

Abstract: A flash memory cell and a method of fabricating the same are disclosed in the present invention. A method of fabricating a flash memory cell having a substrate includes the steps of forming a buried data line in the substrate, forming an insulating layer on the substrate including the buried data line, forming an erase gate on the insulating layer, forming an isolation layer by etching the insulating layer with the erase gate as a mask, forming a floating gate having an indentation at least, the indentation of the floating gate corresponding to the erase gate, and forming a control gate on the floating gate.A flash memory cell includes a substrate, first and second buried data lines in the substrate, an isolation layer on the substrate, a floating gate including a indentation at least on the substrate between the first and second buried data lines, an erase gate over the isolation layer, a part of the erase gate being inserted into the indentation, and a control gates on the floating gate.

Abstract: The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited on the substrate and then the tunnel oxide region is defined by a standard photolithography process followed by an anisotropic etching. A high temperature steam oxidation process is used to grow a thick thermal oxide on the non-tunnel region. After removing the masking silicon nitride layer, the n+ impurity ions is implanted to form the source and drain, and a thermal annealing is performed to recover the implantation damage and to drive in the doped ions. Next, the pad oxide film is etched back and an ultra-thin undoped .alpha.-Si, or HSG-Si, film is deposited. A thermal oxidation process is carried out to convert the undoped .alpha.-Si or HSG-Si into textured tunnel oxide.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanocal polishing the layer. A rugged silicon layer is subsequently deposited over the gate and the polished polysilicon. Then, the floating gate is defined. A dielectric is formed at the top of the rugged silicon. A conductive layer is formed on the dielectric layer as a control gate.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanical polishing the layer. A conductive layer is formed on the polysilicon layers. Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer. A high k dielectric layer is next formed on the JVD nitride.

Abstract: There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate. A conductive layer is formed on the dielectric layer as control gate.

Abstract: This invention discloses a method of forming an electrode of semiconductor device. In the present invention, an amorphous silicon film is formed on a substrate, and silicon seeds are formed on the silicon film. Thereinafter, the heat treatment is performed for growing, thereby forming an hemispherical roughness structure on surface of said charge storage electrode and increasing a surface area in unit area.

Abstract: A method of forming a semiconductor memory device with a variable thickness gate oxide layer including a tunnel oxide layer and a thicker gate oxide layer includes the following steps. Provide a doped silicon semiconductor substrate coated with a tunnel oxide layer, a first floating gate conductor layer and a dielectric layer. Form a mask with an gate oxide opening through the mask. Etch through the gate oxide opening to form a gate oxide trench through the first polysilicon layer, the dielectric layer and the tunnel oxide layer down to the substrate. Form a gate oxide layer at the base of the gate oxide trench. Deposit a second floating gate conductor layer over the device on the exposed surfaces of the dielectric layer and down into the gate oxide trench including the gate oxide layer. Form a thin interelectrode dielectric layer upon the floating gate conductor layer. Deposit a control gate conductor layer over the device covering the device.

Abstract: The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220.

Abstract: A method of making a semiconductor device includes forming a semiconductor substrate having an undulated surface, a gate insulating layer on the semiconductor substrate, a gate electrode on the gate insulating layer, and a source/drain impurity diffusion region in the substrate. The method of fabricating the semiconductor device includes the steps of forming an undulated surface on the substrate by using HSG (hemispherical grain), forming a gate insulating layer on the substrate, forming a gate electrode on the gate insulating layer, and forming an impurity region in the substrate.

Abstract: A method for forming a high-performance oxide as a tunneling dielectric for non-volatile memory applications. A silicon film containing amorphous silicon and good crystalline silicon micrograins is deposited in a silicon substrate by a LPCVD system. Then, a oxidation is performed at a temperature selected in a range such that non-uniform epitaxial silicon growth occurs at the silicon substrate. During an initial thermal oxidation process, the amorphous silicon region is quickly oxidized to form SiO.sub.2 and the good-crystalline silicon micrograins are also quickly oxidized to form the silicon-rich SiO.sub.2 (TOAS). In a following oxidation process, silicon precipitates are formed at the silicon-enriched region and the non-uniform epitaxial silicon growth is also enhanced at the silicon-enriched region. The enhanced non-uniformed silicon growth creates mild microtips. The silicon precipitates connect to the mild silicon microtips.

Abstract: A method for fabricating an MOSFET device on a lightly doped semiconductor substrate with a first dielectric layer thereon comprises forming a floating gate layer over the first dielectric layer. The floating gate layer is formed into a floating gate line. A doped source region and a doped drain region in the substrate are formed by ion implantation adjacent to the periphery of the floating gate line. The first dielectric layer is etched, exposing the surface of the substrate and the surface of the source region and the drain region aside from the floating gate line. Textured dielectric spacers are formed about the periphery of the floating gate line. Polycrystalline spacers are formed about the periphery of the polysilicon oxide dielectric spacers in electrical contact with the doped regions.