Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

Abstract: A substrate processing method includes: (a) carrying a substrate having a first film with a recess, and a mask into a first chamber; (b) adjusting the substrate temperature to 200° C. or higher; (c-1) supplying silicon-containing reactive species into the first chamber, thereby adsorbing the species onto the side wall of the recess; and (c-2) supplying nitrogen-containing reactive species into the first chamber, thereby forming a second film on the side wall of the recess; (d) carrying the substrate into a second chamber; and (e) adjusting the substrate temperature to 100° C. or lower; and (f) etching the bottom of the recess. Further, (a) to (f) are repeated in this order until an aspect ratio of a depth dimension from the opening of the mask to the bottom of the recess becomes 50 or more.

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: A display device includes a first substrate; light-emitting elements disposed on the first substrate; an encapsulation film covering the light-emitting elements; a second substrate facing the first substrate; a first outermost film disposed on the second substrate to face the encapsulation film and including AOXNY (where A is a metal or non-metal element and X>Y); and a filler material disposed between the encapsulation film and the first outermost film and placed in direct contact with the first outermost film.

Abstract: Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

Abstract: A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.

Abstract: Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

Abstract: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

Abstract: Provided herein are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes an etch stop pattern having a top surface and a sidewall disposed over a gate stack having interlayer insulating layers alternately stacked with conductive patterns. The semiconductor device also includes a plurality of channel structures passing through the etch stop pattern and the gate stack. The semiconductor device further includes an insulating layer extending to cover the top surface and the sidewall of the etch stop pattern, wherein a depression is included in a sidewall of the insulating layer. The semiconductor device additionally includes a contact plug passing through the insulating layer so that the contact plug is coupled to a channel structure of the plurality of channel structures.

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

Abstract: A semiconductor memory device includes a first insulating layer over a semiconductor substrate, a metal layer, an adhesive layer on a first region of the metal layer, a conductive layer on a second region of the metal layer and on the adhesive layer, a second insulating layer on the conductive layer, a plurality of wiring layers that are separated from each other and are stacked above the second insulating layer, a semiconductor layer that extends in a first direction perpendicular to the semiconductor substrate and includes a bottom surface connected to the conductive layer, a storage portion disposed between at least one of the plurality of wiring layers and the semiconductor layer, and a slit that extends in the first direction, includes aside surface in contact with the plurality of wiring layers and a bottom surface reaching the conductive layer, and is filled with an insulating material.

Abstract: An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. The method includes depositing in a stack of alternating insulator layers and memory cell layers a layer of silicon oxide, a layer of silicon nitride, and a layer of amorphous silicon; removing the layer of amorphous silicon while maintaining the layer of amorphous silicon in a recess of the memory cells; selectively oxidizing the layer of amorphous silicon and the layer of silicon nitride to remove the layer of amorphous silicon from the recess and the layer of silicon nitride from the insulator layers; and removing oxidizing material from the recess and the insulator layers such that the layer of silicon nitride remains only in the recess of each memory cell of the memory cell layers and the layer of silicon oxide remains on both the insulator layers and the memory cell layers.

Abstract: A lower source-level semiconductor layer, a sacrificial semiconductor layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. An array of memory stack structures containing vertical semiconductor channels that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer is formed. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the sacrificial semiconductor layer. A doped source contact layer is formed on each of the vertical semiconductor channels in the source cavity. A silicon nitride liner is formed on the doped source contact layer. The sacrificial material layers are replaced with electrically conductive layers. A dielectric wall structure is formed in the backside trench.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, drain-select-level gate electrodes located over the alternating stack, memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes, and memory opening fill structures located in the memory openings. The memory opening fill structures can have a stepped profile to provide a smaller lateral dimension at the level of the drain-select-level gate electrodes than within the alternating stack. Each of the drain-select-level gate electrodes includes a planar portion having two sets of vertical sidewall segments, and a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures. The memory opening fill structures can be formed on-pitch as a two-dimensional array.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.

Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a semiconductor substrate. A first structure and a second structure are respectively disposed on the semiconductor substrate and connected to each other. The second structure includes a limiting layer disposed on the upper surface of the semiconductor substrate, a first polysilicon layer disposed conformally on the limiting layer and the semiconductor substrate, and a second polysilicon layer disposed conformally on the first polysilicon layer. A ridge of the second polysilicon layer is disposed near an edge of the second structure beside the first structure, vertically aligned with the limiting layer and defined as a limiting block.

Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.

Abstract: A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on a second region of the substrate, extending in a second direction. A first dual liner is formed on a lateral surface of the first fin. The first dual liner includes a first liner and a second liner. The first liner is interposed between the second liner and the lateral surface of the first fin. A second dual liner is formed on a lateral surface of the second fin. The second dual liner includes a third liner and a fourth liner. The third liner is interposed between the fourth liner and the lateral surface of the second fin. An epitaxial layer surrounds a top portion of the second fin. The first liner and the third liner have different thicknesses.

Abstract: A semiconductor device includes a first source seed layer, a second source seed layer disposed over the first source seed layer while being spaced apart from the first source seed layer, a stacked structure formed on the second source seed layer, channel layers extending inside the first source seed layer by penetrating the stacked structure, and an interlayer source layer extending into a space between the first source seed layer and the second source seed layer while contacting each of the channel layers, the first source seed layer, and the second source seed layer.

Abstract: A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

Abstract: Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect.

Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract: A semiconductor device has a semiconductor layer, a floating gate electrode provided over the semiconductor layer via a first insulation film, and an erase gate electrode to which an erase voltage is applied. The floating gate electrode has an opposing region that opposes via a second insulation film to the erase gate electrode. The opposing region has such a shape that multiple electric field concentrating portions are formed when the erase voltage is applied to the erase gate electrode.

Abstract: An improved semiconductor device results from the use of an amorphous silicon layer in a gate structure disposed between a dielectric layer and an upper conductive layer such as a control gate. Both a semiconductor device and method of manufacturing a semiconductor device using an amorphous silicon layer are provided.

Abstract: An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.

Abstract: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.

Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Abstract: A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.

Abstract: A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.

Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.

Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.

Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.

Abstract: A method includes forming a patterned gate stack for a memory device, the patterned gate stack including a gate insulation layer, a charge storage layer, a blocking insulation layer and a gate electrode, the gate insulation layer and the blocking insulation layer having an initial width. An etching process is performed on the patterned gate stack to selectively remove at least a portion of each of the gate insulation layer and the blocking insulation layer, the etching process reducing a width of each of the gate insulation layer and the blocking insulation layer from the initial width to a final width. After performing the etching process, at least one material layer is formed proximate sidewalls of the patterned gate stack, the at least one material layer laterally confining each of the gate insulation layer, the charge storage layer, the blocking insulation layer, and the gate electrode.