Tunneling Insulator Patents (Class 438/264)
  • Patent number: 10283612
    Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.
    Type: Grant
    Filed: March 3, 2018
    Date of Patent: May 7, 2019
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Chih-Ming Sun, Hsin-Hui Hsu, Ming-Han Tsai
  • Patent number: 10269796
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Patent number: 9947759
    Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a semiconductor substrate. A first structure and a second structure are respectively disposed on the semiconductor substrate and connected to each other. The second structure includes a limiting layer disposed on the upper surface of the semiconductor substrate, a first polysilicon layer disposed conformally on the limiting layer and the semiconductor substrate, and a second polysilicon layer disposed conformally on the first polysilicon layer. A ridge of the second polysilicon layer is disposed near an edge of the second structure beside the first structure, vertically aligned with the limiting layer and defined as a limiting block.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Shih Lin, Chiang-Ming Chuang, Kun-Tsang Chuang, Yung-Lung Hsu
  • Patent number: 9941379
    Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.
    Type: Grant
    Filed: March 12, 2016
    Date of Patent: April 10, 2018
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Chih-Ming Sun, Hsin-Hui Hsu, Ming-Han Tsai
  • Patent number: 9865597
    Abstract: A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on a second region of the substrate, extending in a second direction. A first dual liner is formed on a lateral surface of the first fin. The first dual liner includes a first liner and a second liner. The first liner is interposed between the second liner and the lateral surface of the first fin. A second dual liner is formed on a lateral surface of the second fin. The second dual liner includes a third liner and a fourth liner. The third liner is interposed between the fourth liner and the lateral surface of the second fin. An epitaxial layer surrounds a top portion of the second fin. The first liner and the third liner have different thicknesses.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hoon Cha, Sang-Woo Lee
  • Patent number: 9716099
    Abstract: A semiconductor device includes a first source seed layer, a second source seed layer disposed over the first source seed layer while being spaced apart from the first source seed layer, a stacked structure formed on the second source seed layer, channel layers extending inside the first source seed layer by penetrating the stacked structure, and an interlayer source layer extending into a space between the first source seed layer and the second source seed layer while contacting each of the channel layers, the first source seed layer, and the second source seed layer.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 25, 2017
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 9490371
    Abstract: A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: November 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jin Noh, Bio Kim, Kwangmin Park, Jaeyoung Ahn, SeungHyun Lim, JaeHo Choi, Jumi Yun, Ji-Hoon Choi
  • Patent number: 9312015
    Abstract: Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect.
    Type: Grant
    Filed: October 25, 2014
    Date of Patent: April 12, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Chia-Lin Hsiung, Fumiaki Toyama, Masaaki Higashitani
  • Patent number: 9224746
    Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 29, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Yuan Zhang, Akira Matsudaira
  • Patent number: 9219063
    Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Juergen Holz, Ronald Kakoschke, Thomas Nirschl, Christian Pacha, Klaus Schruefer, Thomas Schulz, Doris Schmitt-Landsiedel
  • Patent number: 9219078
    Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 22, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICOROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning
  • Patent number: 9219134
    Abstract: A semiconductor device has a semiconductor layer, a floating gate electrode provided over the semiconductor layer via a first insulation film, and an erase gate electrode to which an erase voltage is applied. The floating gate electrode has an opposing region that opposes via a second insulation film to the erase gate electrode. The opposing region has such a shape that multiple electric field concentrating portions are formed when the erase voltage is applied to the erase gate electrode.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hideto Fukumoto
  • Patent number: 9196493
    Abstract: An improved semiconductor device results from the use of an amorphous silicon layer in a gate structure disposed between a dielectric layer and an upper conductive layer such as a control gate. Both a semiconductor device and method of manufacturing a semiconductor device using an amorphous silicon layer are provided.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yude Huang, Junmin Zheng
  • Patent number: 9165775
    Abstract: An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 20, 2015
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Pascal Fornara
  • Patent number: 9111857
    Abstract: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: August 18, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fabio Pellizzer, Antonino Rigano, Marcello Mariani, Augusto Benvenuti
  • Patent number: 9082787
    Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 14, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
  • Patent number: 9059094
    Abstract: A semiconductor gate structure is provided having a trench, the trench assembled by a dielectric structure and a stack structure. A first conductive layer may be conformally applied to the dielectric structure and the stack structure. An oxide layer is formed along the first conductive layer and may then be substantially removed from the first conductive layer. In certain gate structures, a conductive fill structure having the first conductive layer and a second conductive layer may be disposed on the stack structure and the dielectric structure.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: June 16, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun Ling Chiang, Chun Ming Cheng, Kuang Chao Chen
  • Patent number: 9059301
    Abstract: A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventor: Kyu S. Min
  • Patent number: 9034707
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Publication number: 20150129950
    Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.
    Type: Application
    Filed: December 19, 2014
    Publication date: May 14, 2015
    Inventors: Georg Tempel, Ernst-Otto Andersen, Achim Gratz
  • Patent number: 9029936
    Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Patent number: 9029930
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Publication number: 20150117117
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Francesco La Rosa, Stephan Niel, Julien Delalleau, Arnaud Regnier
  • Patent number: 9018061
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Itokawa
  • Publication number: 20150108559
    Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
    Type: Application
    Filed: April 5, 2012
    Publication date: April 23, 2015
    Applicant: X-FAB Semiconductor Foundries AG
    Inventors: Eng Gek Hee, Ka Siong Wisley Ung
  • Patent number: 9012290
    Abstract: A method includes forming a patterned gate stack for a memory device, the patterned gate stack including a gate insulation layer, a charge storage layer, a blocking insulation layer and a gate electrode, the gate insulation layer and the blocking insulation layer having an initial width. An etching process is performed on the patterned gate stack to selectively remove at least a portion of each of the gate insulation layer and the blocking insulation layer, the etching process reducing a width of each of the gate insulation layer and the blocking insulation layer from the initial width to a final width. After performing the etching process, at least one material layer is formed proximate sidewalls of the patterned gate stack, the at least one material layer laterally confining each of the gate insulation layer, the charge storage layer, the blocking insulation layer, and the gate electrode.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventor: Shyue Seng Tan
  • Publication number: 20150099337
    Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Inventors: Sung-Jin WHANG, Dong-Sun SHEEN, Seung-Ho PYI, Min-Soo KIM
  • Publication number: 20150091075
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is provided. The element isolation insulating bodies form active areas extending in one direction along a surface of a semiconductor substrate in a surface region of the semiconductor substrate, and partition the surface region into the active areas. The tunnel insulating films are formed on the active areas respectively. The floating gate electrodes are formed on the tunnel insulating films respectively. The inter-gate insulating films are formed on the floating gate electrodes. The control gate electrodes are provided on the inter-gate insulating films. The source regions and drain regions are formed in the active areas respectively. Each of the active areas has steps at side surfaces. A width of a portion of each of the active areas deeper than the steps is larger than that of a portion of each of the active areas shallower than the steps.
    Type: Application
    Filed: September 4, 2014
    Publication date: April 2, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhito NISHITANI, Katsuhiro SATO
  • Patent number: 8987087
    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 24, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Henry Chien, Donovan Lee, Vinod R. Purayath, Yuan Zhang, James K. Kai, George Matamis
  • Patent number: 8980711
    Abstract: A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Pang Hsieh, Kun-Tsang Chuang, Chia Hsing Huang
  • Publication number: 20150072488
    Abstract: A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
  • Publication number: 20150063025
    Abstract: According to one embodiment, a memory cell string stacked body includes first memory cell transistors above a semiconductor substrate, and second memory cell transistors below a first channel semiconductor film, and one of the first memory cell transistors and one of the second memory cell transistors share with a control gate electrode. The control gate electrodes of the first memory cell transistors cover an upper surface of a first charge storage layer and at least a part of a side surface in a second direction via a first insulating film in the one of the first memory cell transistors. The control gate electrodes of the second memory cell transistors cover only a lower surface of a second charge storage layer via a second insulating film in one of the second memory cell transistors.
    Type: Application
    Filed: January 8, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hideto TAKEKIDA
  • Patent number: 8952484
    Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: February 10, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
  • Patent number: 8946022
    Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
  • Patent number: 8946024
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Publication number: 20150024562
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Publication number: 20150008502
    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
    Type: Application
    Filed: May 20, 2014
    Publication date: January 8, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Henry Chien, Donovan Lee, Vinod R. Purayath, Yuan Zhang, James K. Kai, George Matamis
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8927353
    Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 8927370
    Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: January 6, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Yuan Lo, Chun-Pei Wu
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8921917
    Abstract: A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 30, 2014
    Assignee: Wafertech, LLC
    Inventor: Yimin Wang
  • Publication number: 20140367762
    Abstract: A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventors: Ming Tian, Jayavel Pachamuthu, Atsushi Suyama, James Kai, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien, Masanori Terahara, Hirofumi Watatani
  • Patent number: 8912057
    Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8912061
    Abstract: A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventor: Martin M. Frank
  • Patent number: 8912592
    Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-heun Lim, Ki-ho Bae, Hyo-jung Kim, Kyung-hyun Kim, Chan-wook Seo, Young-beom Pyon
  • Publication number: 20140353738
    Abstract: A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric inside the back side recesses and the back side opening. The blocking dielectric has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
    Type: Application
    Filed: August 20, 2014
    Publication date: December 4, 2014
    Inventors: Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Rahul Sharangpani, George Matamis, Johann Alsmeier, Seiji Shimabukuro, Genta Mizuno, Naoki Takeguchi
  • Patent number: 8901636
    Abstract: A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kil-Su Jeong
  • Publication number: 20140346584
    Abstract: An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Akira Matsudaira, Yuan Zhang
  • Patent number: 8895391
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor memory device, the method including: forming isolation layers in trenches dividing active regions of a substrate; depositing a tunnel insulating layer and a charge storing layer on an entire structure including the isolation layers; forming mask patterns on the charge storing layer to cover the active regions and to expose the isolation layers; and etching the charge storing layer by using the mask patterns as an etch barrier, thereby forming charge storing layer patterns on the active regions.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 25, 2014
    Assignee: SK Hynix Inc.
    Inventor: Won Ki Kim