Abstract: A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.

Abstract: A method of making an EPROM transistor in a high density CMOS integrated circuit having a substrate to gate electrode material capacitor. The EPROM transistor is made using only the steps used to make the other components of the high density CMOS integrated circuit. The EPROM transistor is programmable at low voltages which high density CMOS transistors can handle.

Abstract: A floating gate transistor is formed on an active device region defined between field isolation structures. A first polysilicon layer, or a layer of another conductor which can be used in diffusing impurities into the underlying silicon substrate, is provided on the active device region of the substrate and is covered by a layer of insulating material such as silicon oxide. The first polysilicon layer is doped by implantation of impurities, but no annealing step is performed at this time. An opening is formed through the polysilicon layer to expose the surface of the active device region. Oxide spacers and then nitride spacers are formed on the sidewalls of the opening in the first polysilicon layer to define a narrower opening.

Abstract: A making method of a semiconductor device comprising the step of forming a first silicon layer on a silicon substrate, forming a second silicon layer comprising amorphous silicon on the first silicon layer, then crystallizing the second silicon layer and further forming a conductive layer made of a metal silicide or a metal on the second silicon layer, wherein the method comprises forming an intermediate layer to the surface of the first silicon layer after forming the first silicon layer and before forming the second silicon layer, in which the interlayer film has a film thickness within such a range as electrons are conducted by direct tunneling and such a film thickness as disconnecting the succession of the crystallinity of the first silicon layer upon crystallization of the second silicon layer. Accordingly, fluctuation of Vth caused by inter-diffusion of impurities by way of the metal silicide layer is reduced in CMOS of the dual layered polysilicon polycide structure is decreased.

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 .ANG. to 500 .ANG. thick porous oxide over the device to protect the silicide from excessivie exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract: A semiconductor device and a method of manufacturing the same provide a structure which can be easily integrated to a higher extent without providing an alignment margin taking an alignment accuracy of photolithography into consideration. In the semiconductor device, a gate electrode and a pair of source/drain electrodes are formed inside a transistor opening formed at first and second insulating films forming a flat element isolating film. Thereby, an end of the gate electrode in the width direction is defined in an aligned manner by the transistor opening in the step of forming the gate electrode so that it is not necessary to provide the alignment margin taking the alignment accuracy into consideration. This allows high integration.

Abstract: A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.

Abstract: A method of manufacturing a semiconductor memory device having a plurality of memory cells arranged in matrix includes forming a first masking layer on a semiconductor substrate of a first conductivity type and patterning the first masking layer to form a plurality of parallel strips which extend in first direction. A second masking layer is formed on the patterned first masking layer and the second masking layer is patterned to form a plurality of parallel strips which extend in a second direction perpendicular to the first direction. First impurities of a second conductivity type are implanted into the semiconductor substrate, using the patterned first and second masking layers as a mask, to form impurity regions of the second conductivity type. The patterned second masking layer is then removed and an insulating film is formed in the spaces between the parallel strips of the patterned first masking layer for isolating element regions on the semiconductor substrate.

Abstract: A method for fabricating a semiconductor integrated circuit device comprising a nonvolatile memory cell, comprises the steps of forming a first gate material which comprises a silicon film containing no impurities, whose top surface is covered with an oxidation-resistant mask, and whose width in the gate-length direction is prescribed, on part of the surface of a first gate insulating film, forming a thermal-oxidation insulating film on the surface of an active region of a semiconductor substrate through thermal oxidation, removing an oxidation-resistant mask, forming a second gate material which comprises a silicon film into which impurities are introduced and whose width in the gate-length direction is prescribed, on each surface of the thermal-oxidation insulating film and the first gate material forming a second gate insulating film on the surface of the second gate material, and forming a third gate material on the surface of the second gate insulating film.

Abstract: A split gate flash memory manufacturing process comprises the steps of: (a) providing a silicon substrate having a first insulating layer, and forming a first conductive layer on said first insulating layer, and forming a third insulating layer on said first conductive layer; (b) removing part of said third insulating layer and part of said first conductive layer to expose left and right sidewalls of said first conductive layer and part area of said first insulating layer; (c) performing an oxidation process to form a second insulating layer on left and right sidewalls of said first conductive layer and on said part area of said first insulating layer, wherein by a blocking function of the third insulating layer on said second insulating layer an asperity effect on left and right edges of said first conductive layer is reduced; and (d) forming a second conductive layer on said second and third insulating layers to form said split gate flash memory unit.

Abstract: Disclosed is a process for producing p-type doped layers, in particular, in II-VI semiconductors, in which the p-type doped layer is produced in a CVD-step by means of plasma activation of nitrogenated gases.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming memory cell sections in a nonvolatile semiconductor memory device which has the memory cell sections and peripheral circuit transistor sections formed on a semiconductor substrate, coating a stacked region of the memory cell sections and a top surface of the peripheral circuit transistor sections with an oxidation-resistant layer, and forming an oxide layer over the surface of the semiconductor substrate by thermal oxidation. The peripheral circuit transistor gate oxide layer is suitably oxidized to have sufficient dielectric strength while preventing the interlayer insulating layer between the control gate edge and the floating gate edge of a memory cell from being oxidized more than necessary.

Abstract: The present invention includes a process of growing a compound semiconductor layer locally, after applying radical particles that do not become an etchant of a compound semiconductor layer to an insulating mask so as to terminate the surface of the insulating mask in a state that the compound semiconductor layer is covered with the insulating mask, on the surface of the compound semiconductor layer exposed from the insulating mask.

Abstract: This invention describes a device structure and a method of forming the device structure using trenches with sidewalls formed in the substrate of an integrated circuit. A highly doped polysilicon layer is formed on the walls of the trench or the trench is filled with highly doped polysilicon to form the source and drain of a field effect transistor in an integrated circuit. The invention provides reduced source and drain resistance. The capacitances between the gate and source and the gate and drain are reduced as well.

Abstract: A method of reducing undesired electron depletion through sidewalls of a floating gate of a floating gate transistor comprising providing a non-oxide or oxynitride layer over said sidewalls. Integrated circuitry including a non-volatile field effect transistor includes, a) a floating gate transistor having a gate construction and a pair of opposing source/drain regions, the gate construction having at least one sidewall; b) a shielding layer over the gate sidewall; and c) a dielectric layer on the shielding layer, the dielectric layer being of a different material than the shielding layer. The shielding layer might be provided over an oxide layer previously provided on sidewalls of the gate construction. The shielding layer might be provided over sidewall spacers previously provided relative to sidewalls of the gate construction. Example and preferred shielding layer materials include Si.sub.3 N.sub.4, oxynitride compounds, and aluminum.

Abstract: A stack of oxide (16) and silicon nitride (18) is grown/deposited over a patterned polysilicon line, which typically acts as a bottom capacitor plate. A thin layer of amorphous or polycrystalline silicon (20) is deposited over the blanket silicon nitride film. The thickness of the deposited silicon layer must be optimized according to the final amount of oxide desired over the silicon nitride, which will be roughly twice the thickness of the deposited silicon film. The oxide/nitride/silicon stack is then patterned and etched, stopping either at or underneath the bottom oxide. Any subsequent cleaning in potentially oxide-etching chemistries (including HF) is done with the protective silicon deposit on top of the silicon nitride. The entire structure is then thermally oxidized, transforming the deposited silicon into silicon oxide (30). Where the structure has been cleared down to the substrate by etching, a second gate oxide is simultaneously formed.

Abstract: A method of forming a line for floating gate transistors is described and which includes, providing a substrate having a plurality of discrete field oxide regions, and intervening active area regions therebetween; forming a first alternating series of floating gates over a first alternating series of active area regions; forming a second alternating series of floating gates over a second alternating series of active area regions, the second series of floating gates disposed in spaced, overlapping and partial covering relation relative to the first alternating series of floating gates; forming a layer of dielectric material over the first and second series of floating gates; and forming a control gate layer of electrically conductive material over the layer of dielectric material. The present invention further relates to a memory chip, and die having a line of floating gate transistors formed from the same method.

Abstract: A MOSFET device and a method of fabricating an MOSFET device on a lightly doped semiconductor substrate are described. First, form buried bitlines in the substrate. Form conductive, complementary bitline structures formed of doped polycrystalline silicon, the structures having lower surfaces formed on the buried bitlines in electrical contact therewith, and the complementary bitline structures having top surfaces and sidewalls. Form a polysilicon oxide of the doped polycrystalline silicon from the complementary bitline structures over the top surfaces thereof. Oxidize to form tunneling oxide polysilicon oxide sidewall layers adjacent to the complementary bitline structures. Simultaneously, form a tunnel oxide layer over the substrate between the complementary bitline structures. Form floating gates over the tunnel oxide layer and between the sidewall layers. Form an interconductor dielectric layer over the device Finally, form an array of wordlines over the interconductor dielectric layer.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.