V-gate Patents (Class 438/271)
  • Patent number: 10211291
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Patent number: 9564527
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Masato Nishimori, Tadahiro Imada
  • Patent number: 9034712
    Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Richard A. Phelps, Jed H. Rankin, Yun Shi
  • Patent number: 9024377
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 5, 2015
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Publication number: 20150108568
    Abstract: A semiconductor device has an epitaxial layer grown over a substrate, each having a first dopant type. A structure disposed within the epitaxial layer has multiple trenches, each of which has a gate and a source electrode disposed within a shield oxide matrix. Multiple mesas each isolate a pair of the trenches from each other. A body region with a second dopant type is disposed above the epitaxial layer and bridges each of the mesas. A region of elevated concentration of the first dopant type is implanted at a high energy level between the epitaxial layer and the body region, which reduces resistance spreading into a channel of the device. A source region having the first dopant type is disposed above the body region.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 23, 2015
    Applicant: Vishay-Siliconix
    Inventors: Kyle TERRILL, Lingpeng GUAN
  • Patent number: 8980713
    Abstract: A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Satoru Mayuzumi, Mark Fischer, Michael Violette
  • Patent number: 8957473
    Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 17, 2015
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 8940607
    Abstract: The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 27, 2015
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8928070
    Abstract: The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: January 6, 2015
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8927347
    Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Toshio Nakajima, Syoji Higashida
  • Patent number: 8900947
    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jin Yul Lee
  • Patent number: 8889532
    Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter A. Burke, Gordon M. Grivna, Balaji Padmanabhan, Prasad Venkatraman
  • Patent number: 8871592
    Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8859369
    Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: October 14, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Patent number: 8853033
    Abstract: A method for fabricating a semiconductor device includes: sequentially forming an n? type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n? type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n? type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide fi
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Hyundai Motor Company
    Inventors: Youngkyun Jung, Kyoung-Kook Hong, Jong Seok Lee, Dae Hwan Chun
  • Patent number: 8835258
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Huan-Ping Chu
  • Patent number: 8815688
    Abstract: A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hoon Lee, Ki Se Kim, Jung Hee Lee, Ki Sik Im, Dong Seok Kim
  • Patent number: 8772111
    Abstract: A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 8, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yoshihiro Ikura
  • Patent number: 8766325
    Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Toshio Nakajima, Syoji Higashida
  • Patent number: 8759202
    Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Gerald Deboy
  • Patent number: 8686500
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Ching-Yao Yang
  • Patent number: 8680613
    Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 25, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 8664071
    Abstract: A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: March 4, 2014
    Inventor: John James Seliskar
  • Patent number: 8659055
    Abstract: Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Hironobu Miyamoto, Tatsuo Nakayama, Yuji Ando
  • Patent number: 8652906
    Abstract: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: February 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Walter Rieger, Markus Zundel
  • Patent number: 8647972
    Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Aritra Dasgupta, Unoh Kwon, Sean M. Polvino
  • Patent number: 8642424
    Abstract: A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sameer H. Jain, Jeffrey B. Johnson, Ying Li, Hasan M. Nayfeh, Ravikumar Ramachandran
  • Patent number: 8643092
    Abstract: A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 4, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8637368
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 28, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Xiaobin Wang
  • Patent number: 8598627
    Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: December 3, 2013
    Assignee: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Patent number: 8597998
    Abstract: Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 3, 2013
    Assignee: Alpha & Omega Semiconductor Limited
    Inventors: Anup Bhalla, Sik K. Lui, Tiesheng Li
  • Patent number: 8592274
    Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 26, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 8575693
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 5, 2013
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu, Chien-Hao Huang
  • Patent number: 8569131
    Abstract: A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8564052
    Abstract: A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8564057
    Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: October 22, 2013
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 8564053
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprise an EPR surrounding outside the multiple trenched floating gates in the termination area.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130264621
    Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroo NISHI, Hiromitsu OSHIMA
  • Patent number: 8536008
    Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: September 17, 2013
    Assignee: Powerchip Technology Corporation
    Inventors: Heiji Kobayashi, Yukihiro Nagai
  • Publication number: 20130234241
    Abstract: A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Inventor: Brian Bowers
  • Patent number: 8519477
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The multiple trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 27, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8487372
    Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 16, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8435844
    Abstract: A gate electrode is formed on a surface of a semiconductor substrate. A resist mask is formed that covers both end faces of the gate electrode in a gate width direction intersecting a gate length direction. Impurity ions are implanted into the semiconductor substrate in an implantation direction having a gate length direction component and a gate width direction component, to form a low-concentration impurity layer overlapping with the gate electrode at both sides of the gate electrode in the surface of the semiconductor substrate. A sidewall is formed that covers a side surface of the gate electrode. Impurity ions are implanted using the gate electrode and the sidewall as a mask, to form a high-concentration impurity layer apart from the gate electrode at both sides of the gate electrode on the surface of the semiconductor substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: May 7, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Mayumi Shibata
  • Patent number: 8421150
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 16, 2013
    Assignee: Richtek Technology Corporation R.O.C.
    Inventors: Tsung-Yi Huang, Huan-Ping Chu
  • Patent number: 8350321
    Abstract: The present invention discloses a transistor having the saddle fin structure. The saddle fin transistor of the present invention has a structure in which a landing plug contact region, particularly, a landing plug contact region on an isolation layer is elevated such that the landing plug contact SAC (Self Aligned Contact) fail can be prevented.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: January 8, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyu tae Kim
  • Patent number: 8349693
    Abstract: A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: January 8, 2013
    Assignee: DENSO CORPORATION
    Inventors: Takumi Shibata, Shouichi Yamauchi
  • Patent number: 8288229
    Abstract: Fabricating a semiconductor device includes forming a hard mask on the substrate having a top substrate surface; forming a gate trench in the substrate, through the hard mask; depositing gate material in the gate trench; removing the hard mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; and disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: October 16, 2012
    Assignee: Alpha & Omega Semiconductor Limited
    Inventors: Anup Bhalla, Sik K. Lui, Tiesheng Li
  • Patent number: 8232161
    Abstract: A trench is formed so as to reach a p?-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8202781
    Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: June 19, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 8120101
    Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon A. Haller, Kris K. Brown, Tuman Earl Allen, III