Vertical Channel Patents (Class 438/268)
  • Patent number: 11183636
    Abstract: Techniques for forming RRAM cells with increased density are provided. In one aspect, a method of forming a RRAM device includes: providing an underlayer disposed on a substrate; patterning trenches in the underlayer; forming bottom electrodes at two different levels of the underlayer that includes first bottom electrodes at bottoms of the trenches and second bottom electrodes along a top surface of the underlayer in between the trenches; depositing an insulating layer on the first/second bottom electrodes; and forming top electrodes on the insulating layer, wherein the top electrodes include word lines, wherein the first and second bottom electrodes include bit lines that are orthogonal to the word lines. A RRAM device is also provided.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Dexin Kong, Takashi Ando
  • Patent number: 11149201
    Abstract: Provided is a silicon nitride layer etching composition, and more specifically, a silicon nitride layer etching composition including two different silicon-based compounds in an etching composition to be capable of selectively etching a silicon nitride layer relative to a silicon oxide layer with a remarkable etch selectivity ratio and providing remarkable effects of suppressing generation of precipitates and reducing the abnormal growth of other layers existing in the vicinity, including the silicon oxide layer when the silicon nitride layer etching composition is used for an etching process and a semiconductor manufacturing process.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 19, 2021
    Assignee: ENF TECHNOLOGY CO., LTD.
    Inventors: Dong Hyun Kim, Hyeon Woo Park, Du Won Lee, Jang Woo Cho, Myung Ho Lee, Myung Geun Song
  • Patent number: 11139174
    Abstract: A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao, Li-Te Hsu
  • Patent number: 11133377
    Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 28, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 11133194
    Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: September 28, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
  • Patent number: 11121258
    Abstract: A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Witold Kula, Gurtej S. Sandhu, John A. Smythe
  • Patent number: 11107802
    Abstract: In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Nakaki
  • Patent number: 11075299
    Abstract: Embodiments of the invention are directed to a method that includes forming a fin over a major surface of a substrate. The fin includes an active fin region having a top fin surface and a fin sidewall. The top fin surface is substantially parallel with respect to the major surface, and the fin sidewall is substantially perpendicular with respect to the major surface. A gate is formed over and around a central portion of the fin, the gate having a bottom gate region and a top gate region. The bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall. The top gate region is substantially above the top fin surface and includes a top gate region sidewall that is at an angle with respect to the major surface.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Miller, Gauri Karve, Marc A. Bergendahl, Fee Li Lie, Kangguo Cheng, Sean Teehan
  • Patent number: 11056497
    Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin B. Dorhout, Damir Fazil, Nancy M. Lomeli
  • Patent number: 11038027
    Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Deepak Chandra Pandey, Haitao Liu, Richard J. Hill, Guangyu Huang, Yunfei Gao, Ramanathan Gandhi, Scott E. Sills
  • Patent number: 11037954
    Abstract: A three dimensional flash memory element with middle source-drain line and manufacturing method thereof. The three dimensional flash memory element includes a string including a channel layer extended in one direction and a plurality of electrode layers vertically layered for the channel layer; an upper wiring layer placed at the top of the string; at least one intermediate wiring layer placed between the plurality of electrode layers in the intermediate area of the string; and a lower wiring layer placed at the bottom of the string. Each of the upper wiring layer, the at least one intermediate wiring layer, and the lower wiring layer is adaptively used as any one of a drain electrode or a source electrode.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun Heub Song
  • Patent number: 10998378
    Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Jean-Jacques Fagot
  • Patent number: 10964714
    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geunwon Lim, SangJun Hong, Seokcheon Baek
  • Patent number: 10964602
    Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10964695
    Abstract: Semiconductor structures are provided. Each of the transistors includes a first source/drain region over a semiconductor fin extending in a first direction, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction perpendicular to the first direction. In a first transistor of the transistors, a first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors, A second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate extending in the second direction. A first contact of the first source/drain region is narrower than a second contact of the second source/drain region along the first direction.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10957793
    Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 23, 2021
    Assignee: IMEC vzw
    Inventors: Vasile Paraschiv, Guglielma Vecchio, Anabela Veloso
  • Patent number: 10957549
    Abstract: A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Guangjun Yang
  • Patent number: 10950704
    Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jun Shin, Si-Wan Kim, Bong-Hyun Choi
  • Patent number: 10941341
    Abstract: An etching composition providing a high selection ratio enabling selective removal of a nitride film and minimization of an etching rate, a preparation method thereof, an etching composition additive prepared through a reaction of phosphoric anhydride and a silane compound represented by Formula 1 below, a method for preparing the same and an etching composition including the same are provided:
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 9, 2021
    Assignees: SK Innovation Co., Ltd., SK-Materials Co., Ltd.
    Inventors: Cheol Woo Kim, Yu Na Shim, Je Ho Lee, Jae Hoon Kwak, Young Bom Kim, Jin Kyung Jo
  • Patent number: 10937869
    Abstract: The subject matter disclosed herein relates to wide band gap semiconductor power devices and, more specifically, to high-energy implantation masks used in forming silicon carbide (SiC) power devices, such as charge balanced (CB) SiC power devices. An intermediate semiconductor device structure includes a SiC substrate layer having a first conductivity type and silicon carbide (SiC) epitaxial (epi) layer having the first conductivity type disposed on the SiC substrate layer. The intermediate device structure also includes a silicon high-energy implantation mask (SiHEIM) disposed directly on a first portion of the SiC epi layer and having a thickness between 5 micrometers (?m) and 20 ?m. The SiHEIM is configured to block implantation of the first portion of the SiC epi layer during a high-energy implantation process having an implantation energy greater than 500 kiloelectron volts (keV).
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 2, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: William Gregg Hawkins, Reza Ghandi, Christopher Bauer, Shaoxin Lu
  • Patent number: 10930670
    Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Wan Sup Shin, Ki Hong Lee, Jae Jung Lee, Young Geun Jang
  • Patent number: 10923498
    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Satoshi Shimizu, Makoto Koto
  • Patent number: 10923591
    Abstract: A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 16, 2021
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10923494
    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, David H. Wells, John D. Hopkins, Kevin Y. Titus
  • Patent number: 10916427
    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10910400
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Woo Park, Kyo Yeon Cho
  • Patent number: 10886403
    Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: January 5, 2021
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Alexander Reznicek, Shogo Mochizuki, Jingyun Zhang, Xin Miao
  • Patent number: 10886462
    Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Ekmini Anuja de Silva, Jennifer Church, Luciana Meli Thompson
  • Patent number: 10872918
    Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes an epitaxial layer and a dielectric layer. The epitaxial layer and the dielectric layer are formed in a deep trench of a semiconductor substrate. The epitaxial layer covers a lower portion of sidewall of the trench, and the dielectric layer covers an upper portion of the sidewall of the trench. In the method for fabricating the optical isolation structure, at first, shallow trenches are formed in the semiconductor substrate. Then, the dielectric layer is formed in the shallow trenches. Thereafter, deep trenches are formed passing through the dielectric layers. Then, the epitaxial layer is formed in the deep trenches.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Han Huang, Tzu-Hsiang Chen, Shih-Pei Chou, Jiech-Fun Lu
  • Patent number: 10867906
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-I Yang, Yu-Chieh Liao, Tien-Lu Lin, Tien-I Bao
  • Patent number: 10854620
    Abstract: According to one embodiment, a semiconductor memory device includes: first interconnect layers; second interconnect layers; a first memory pillar extending through the first interconnect layers; a second memory pillar extending through the second interconnect layers; a first film provided above the first interconnect layers, having a planar shape corresponding to the first interconnect layers and extending in the first direction; and a second film provided above the second interconnect layers, separate from the first film in the second direction, having a planar shape corresponding to the second interconnect layers and extending in the first direction. The first and second films have a compressive stress higher than a silicon oxide film.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takeo Mori, Takashi Terada
  • Patent number: 10834828
    Abstract: A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gerald Bartley, Darryl Becker, Matthew Doyle, Mark Jeanson
  • Patent number: 10825691
    Abstract: Methods, apparatuses, and systems related to stack a semiconductor structure are described. An example method includes stacking a semiconductor structure between electrode materials having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a third silicate material on the second nitride. The method further includes forming a third nitride on the third silicate material. The method further includes using a wet etch process to increase a width between electrode materials. The method further includes using a dry etch process to remove a portion of materials within the semiconductor structure.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Che-Chi Lee
  • Patent number: 10818661
    Abstract: Methods for fabricating FinFETs with enhanced performance are disclosed herein. An exemplary method includes forming a first fin and a second fin having a trench defined therebetween. The first fin and the second fin each include a first semiconductor layer disposed over a second semiconductor layer. An isolation feature is formed in the trench between the first fin and the second fin. A gate structure is formed over the isolation feature, a first region of the first fin, and a first region of the second fin. The gate structure is disposed between second regions of the first fin and between second regions of the second fin. After recessing the first fin and the second fin, a third semiconductor layer is formed over the first fin and the second fin. In some embodiments, the third semiconductor layer extends over the isolation feature and merges the first fin and the second fin.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao Chang, Jeff J. Xu
  • Patent number: 10784278
    Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yong-Sheng Huang, Ming-Chyi Liu
  • Patent number: 10770579
    Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 8, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yasushi Urakami, Yukihiko Watanabe
  • Patent number: 10763337
    Abstract: A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
  • Patent number: 10763105
    Abstract: A method of manufacturing a grooved-gate MOSFET device based on a two-step microwave plasma oxidation, including: etching a grooved gate, and oxidizing silicon carbide on a surface of the grooved gate to silicon dioxide by microwave plasma to form a grooved-gate oxide layer, the step of forming the grooved-gate oxide layer including: placing a silicon carbide substrate subjected to the grooved gate etching in a microwave plasma generating device; introducing a first oxygen-containing gas, heating generated oxygen plasma to a first temperature at a first heating rate, and performing low-temperature plasma oxidation at the first temperature and a first pressure; heating the oxygen plasma to a second temperature at a second heating rate, introducing a second oxygen-containing gas, and performing high-temperature plasma oxidation at the second temperature and a second pressure until a predetermined thickness of silicon dioxide is formed; stopping introduction of the oxygen-containing gas, and completing the react
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 1, 2020
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Xinyu Liu, Yidan Tang, Shengkai Wang, Yun Bai, Chengyue Yang
  • Patent number: 10741557
    Abstract: A method and structure for forming hybrid high mobility channel transistors. The method includes: providing a substrate, epitaxially growing a buffer layer over the substrate and a semiconductor layer over the buffer layer, forming a partial opening over the semiconductor layer, epitaxially growing a second semiconductor layer in the opening, forming a first plurality of fins from the first semiconductor layer and a second plurality of fins from the second semiconductor layer, where the first semiconductor layer and the second semiconductor material comprise different materials, oxidizing a portion of the second plurality of fins, and stripping the oxidized portion of the second plurality of fins, where after striping the oxidized portion of the second plurality of fins, the second plurality of fins have the same width as the first plurality of fins.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10727105
    Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent the breakage of an element and in which the control of impurity amounts is less susceptible to variations in manufacturing processes. A semiconductor substrate has a front surface and includes hole portions extending from the front surface to an inside of the substrate. N-type regions are formed in the semiconductor substrate. At wall surfaces of the hole portions, p-type regions are formed to configure p-n junction with the n-type regions. Each of the p-type regions includes a low-concentration region and a high-concentration region formed at the wall surface of each hole portion. A width of the high-concentration region along the wall surface of the hole portion becomes smaller from the front surface toward a deeper position.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: July 28, 2020
    Assignee: RENSAS ELECTRONICS CORPORATION
    Inventors: Tsuyoshi Kachi, Yoshinori Hoshino, Senichirou Nagase
  • Patent number: 10727245
    Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 28, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Zhiliang Xia, Ping Yan, Guangji Li, Zongliang Huo
  • Patent number: 10720519
    Abstract: A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Hidenori Takahashi
  • Patent number: 10714574
    Abstract: A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region that contacts a shield region in an epitaxial or crystalline layer of the device.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 14, 2020
    Assignee: iPower Semiconductor
    Inventor: Hamza Yilmaz
  • Patent number: 10672887
    Abstract: A vertical transistor includes a first source/drain region and a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin. A gate dielectric is formed on the fin, and a gate conductor is formed on the gate dielectric in a region of the fin. A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Kangguo Cheng, Theodorus E. Standaert, Veeraraghavan S. Basker
  • Patent number: 10658590
    Abstract: Techniques for forming RRAM cells with increased density are provided. In one aspect, a method of forming a RRAM device includes: providing an underlayer disposed on a substrate; patterning trenches in the underlayer; forming bottom electrodes at two different levels of the underlayer that includes first bottom electrodes at bottoms of the trenches and second bottom electrodes along a top surface of the underlayer in between the trenches; depositing an insulating layer on the first/second bottom electrodes; and forming top electrodes on the insulating layer, wherein the top electrodes include word lines, wherein the first and second bottom electrodes include bit lines that are orthogonal to the word lines. A RRAM device is also provided.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Dexin Kong, Takashi Ando
  • Patent number: 10658379
    Abstract: A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a slit vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the slit; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Lan Yao
  • Patent number: 10651302
    Abstract: A semiconductor device including: a semiconductor substrate; a drift region of first conductivity type that is formed in the semiconductor substrate; an accumulation region of first conductivity type that is formed above the drift region and has higher concentration than concentration of the drift region; a base region of second conductivity type that is formed above the accumulation region; and a gate trench portion that is formed extending from an upper surface of the semiconductor substrate to the drift region, passing through the base region and the accumulation region, wherein a maximum value of doping concentration of the accumulation region is greater than a maximum value of doping concentration of the base region will be provided.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa
  • Patent number: 10651181
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Phillipe Matagne, Yoshiaki Kikuchi
  • Patent number: 10637467
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon Park, Bo Seok Oh, Hee Hwan Ji
  • Patent number: 10629702
    Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Sanjay C. Mehta, Muthumanickam Sankarapandian