Abstract: A semiconductor device and a method of forming thereof include a dummy active region positioned adjacent the device active region. The dummy active region is formed to include an oxide layer of a thickness that is less than the oxide layer of the active region such that excess charge accumulated during etching in the active region is conducted through the dummy active region into the substrate. In this manner, the dummy active region operates as a charge sink during formation of the active region to prevent premature deterioration of the gate oxide layer of the active region.

Abstract: The present invention discloses a planarization method of memory unit of a flash memory, wherein a patterned polysilicon layer and a silicon nitride layer are formed in turn on a semiconductor substrate. A silicon dioxide layer is then deposited by the HDPCVD technique. Next, a silicon nitride layer is deposited. Finally, the silicon nitride layer and the silicon dioxide layer thereon are simultaneously removed using hot phosphoric acid. Because the CMP technique is not used in the present invention, the problem of micro scratches will not arise. Therefore, the present invention can assure the requirement of high planarity of memory unit of the flash memory, simplify the process flow, increase the tolerance of the etching mask, and effectively enhance the function of memory unit.

Abstract: A field effect transistor device has a semiconductor substrate having a predetermined impurity concentration of a first conductivity type. Inpurity layers of a second conductivity type are formed spaced apart at the main surface of the semiconductor substrate. The impurity layers make up source/drain regions. A region between the impurity layers defines a channel region. A notch-shaped conductive layer is formed on the channel region. The notch-shaped conductive layer has an upper layer section longer than a lower layer section. The upper and lower layer sections are formed of at least two different materials, one being silicon-germanium layer with varying germanium content. The material of the lower layer section can be etched at a greater rate than the material of the upper layer section during a common etching process.

Abstract: Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: According to one embodiment of the invention, a method of forming an asymmetric I/O transistor includes forming a first oxide layer outwardly from a semiconductor substrate, masking a first portion, less than a whole portion, of an I/O transistor region with a first photoresist layer, removing the first oxide layer from a core transistor region and a second portion of the I/O transistor region, removing the first photoresist layer, forming a second oxide layer outwardly from the substrate, forming gates for the core transistor region and the I/O transistor region, masking the first portion of the I/O transistor region with a second photoresist layer, doping a source region and a drain region of the core transistor region and a source region of the I/O transistor region with a first dopant, doping the source region and the drain region of the core transistor region and the source region of the I/O transistor region with a second dopant, removing the second photoresist layer, masking the core transistor region

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

Abstract: In a method for forming a semiconductor device having a power MOSFET and a diode, after a gate electrode and n+ type source regions for the power MOSFET and an n+ type region of a poly-Si layer for the diode are formed, an oxide film is formed by thermal oxidation. At that time, accelerated oxidation occurs where an n+ type impurity is heavily implanted, so that the oxide film becomes thick on the surfaces of the gate electrode, the source regions, and the n+ type region, as compared to the other region. Then, a p type impurity is self-alignedly implanted through the oxide film serving as a mask to form a p+ type contact region for the MOSFET and a p+ type region of the poly-Si layer for the diode.

Abstract: A process for fabricating composite insulator spacers, comprised of an underlying silicon oxide sidewall layer, and an overlying silicon nitride layer, formed on the sides of a polycide gate structure, has been developed. The process features initially, laterally recessing the exposed sides of a tungsten silicide component, of the polycide gate structure, via use of a selective wet etch solution. A subsequent oxidation procedure, used to thermally grow the silicon oxide sidewall layer, results in a thick silicon oxide component, located on the recessed sides of the tungsten silicide layer, while a thinner silicon oxide component is formed on the sides of the polysilicon component, of the polycide gate structure. Deposition of a silicon nitride layer, followed by an anisotropic RIE procedure, are then used to form the composite insulator spacers, on the sides of the polycide gate structure.

Abstract: A double-bit non-volatile memory structure and a method of forming the structure. The main body of the structure is an array of double-bit memory cells partitioned out by mutually crossing isolation lines and bit lines. Each memory cell includes a pair of stacked gate structures, a doped region in between the stacked gate structures and a pair of common source/drain regions for the pair of stacked gate structures. Each control gate within the pair of stacked gate structures connects electrically with a neighboring word line and each source/drain region connects electrically with a bit line. To form the structure, a plurality of isolation lines is formed over a substrate and then a plurality of linear multi-layered structures perpendicular to the isolation lines are formed over the isolation lines. A pair of neighboring linear multi-layered structures forms a grid unit. Thereafter, source/drain regions and bit lines are formed between various grid units.

Abstract: A static random access memory manufacturing method. A substrate having a gate oxide layer and a first conducting layer is defined to form a buried contact window opening. A second conducting layer is formed upon the substrate with a recess structure at the region of the buried contact opening. A buried contact window is formed in the substrate under the buried contact window opening. A protective layer is formed upon the substrate and fills the recess. A portion of the protective layer is removed, and a patterned photoresist layer is formed upon the substrate. Using the photoresist as a mask, the first and second conducting layer are etched to form a gate electrode and an interconnect. The patterned photoresist layer is removed. The protective layer can be removed or retained. An implantation procedure is performed, thereby forming a source/drain, thereby connecting the source/drain and the contact window.

Abstract: A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.

Abstract: A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of Gn+2Sn are formed on n-channel transistor gate structures and an N+ implant is performed to form N+ implant is performed to form N+ regions in the n-channel substrate region. Resist spacers having a dimension of Gs +2Sp are formed on p-channel transistor gate structures and a P+ implant is performed to form P+ regions in the p-channel substrate region.

Abstract: A process for fabricating a semiconductor device including MOS transistors of low breakdown voltage type and of high breakdown voltage type provided on a semiconductor substrate, the MOS transistor of high breakdown voltage type being operative at a higher voltage than the MOS transistor of low breakdown voltage type and having drift diffusion regions, the process comprises the steps of: forming a LOCOS oxide film on the semiconductor substrate; and performing ion implantation with the use of a single mask having openings respectively defining on the substrate a first region for formation of a first conductivity type MOS transistor of low breakdown voltage type, a second region in which the LOCOS oxide film is formed for isolation of a first conductivity type MOS transistor of high breakdown voltage type, and a third region for formation of a drift diffusion region of a second conductivity type MOS transistor of high breakdown voltage type, so that the first and third regions each have at least two concentrat

Abstract: Process sequences used to simultaneously form a first dielectric gate layer for a first group of MOSFET elements, and a second dielectric gate layer for a second group of MOSFET elements, with the thickness of the first dielectric gate layer different than the thickness of the second gate dielectric layer, has been developed. A first iteration of this invention entails a remote plasma nitridization procedure used to form a thin silicon nitride layer on a bare, first portion of a semiconductor substrate, while simultaneously forming a thin silicon oxynitride layer on the surface of a first silicon dioxide layer, located on second portion of the semiconductor substrate.

Abstract: A section separator region is formed in a semiconductor substrate in which a p-type well region has been formed, to separate the substrate into an I/O section and a core section. An oxide film and a plysilicon film are form at the I/O section, and pre-formation treatment is carried out. Then, an oxide film is formed over the exposed surface by the thermal oxidization. A metal film is formed on the oxide film. The metal film on the I/O section is moved. The polysilicon film and the metal film are patterned to be gate electrodes. Then, ion implantation is carried out to implant impurity into the exposed surface to form source/drain regions corresponding to the gate electrodes respectively.

Abstract: A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.

Abstract: A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask.

Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2-eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.

Abstract: The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.

Abstract: In a non-volatile memory, memory cells have respective floating gates formed of a first polysilicon and respective control gates formed of a second polysilicon. Further, in the non-volatile memory, peripheral circuits include transistors having respective gates formed of the first polysilicon. In addition, a silicide layer is formed directly on the control gates of the memory cells and directly on the gates of the transistors.

Abstract: A DRAM semiconductor device has: a semiconductor substrate with one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well. A DRAM semiconductor device is provided whose refresh characteristics are improved without deteriorating other characteristics.

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

Abstract: An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The body region of the dual-gated MOSFET is a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: Disclosed is a nonvolatile memory device comprising a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second gate insulating layer and a control gate line deposited in one direction perpendicular to the first and second active regions and covering the floating gate; first impurity regions formed in the first and second active regions at one side of the control gate line; second impurity regions formed in the first and second active regions at other side of the control gate line; first contact plugs contacted with the first impurity regions; and a common conductive line formed in one direction on the semiconductor substrate at the other side of the control gate line, for connecting the second impurity regions of the first and second active regions.

Abstract: The surface of a silicon substrate is sputter-etched so that silicon clusters sputtered out form a silicon film on a side wall spacer. Then, a metal film of cobalt, titanium or the like is built up on the entire surface. Thereafter, silicidizing process is carried out to form metal silicide layers on a diffusion layer and the side wall spacer. Then, an inter-layer insulation film 14 is formed and is photo-etched to provide the inter-layer insulation film with a contact hole 15 overlapping the side wall spacer.

Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) comprising a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) comprising a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.

Abstract: Various methods of fabricating circuit devices incorporating a gate stack are disclosed. In one aspect, a method of fabricating a circuit device on a substrate is provided that includes forming a first insulating film on the substrate and etching the first insulating film to define a temporary gate structure. A second insulating film is formed on the substrate adjacent to the temporary gate structure. The temporary gate structure is removed to leave an opening extending to the substrate. A gate stack is formed in the opening. The process of the present invention provides for metal gate definition with sub-lithographic limit critical dimensions.

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.

Abstract: The present invention provides a method to integrate the process of manufacturing an embedded memory and the sequential process of forming a landing via and a strip contact in the embedded memory. The method involves first defining a memory array region and a periphery circuit region on the surface of a silicon substrate of a semiconductor wafer. Next, a plurality of gates and lightly doped drains are separately formed in the memory array region and the periphery circuit region. A silicon nitride layer then covers the surface of each gate in the memory array region, and forms a spacer on either side of each gate in the periphery circuit region. Then, a dielectric layer is formed on the surface of the semiconductor wafer, and a landing via hole and a strip contact hole are separately formed in the dielectric layer in the memory array region and the periphery circuit region, respectively. Finally, each hole is filled with a conductive layer to form in-situ each landing via and strip contact.

Abstract: A MOS transistor fabrication method of the present invention comprises a step of forming a gate insulating film upon a semiconductor substrate; a step of forming a silicon film made from polysilicon or amorphous silicon upon the gate insulating film; a step of applying a heat treatment carried out at 800 to 1000° C. and for a duration of 1 to 10 seconds on the silicon film; a step of pre-doping by implanting impurity ions into the silicon film; a step of patterning a gate electrode by etching the silicon film; a step of forming sidewalls at the side portions of the gate electrode; and a step of doping the gate electrode with an impurity by implanting ions into the gate electrode and the semiconductor substrate as well as forming a source and a drain on the surface of the semiconductor substrate.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An ultra thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2 at a temperature ranging from approximately 650° C. to approximately 900° C. And then, an Al layer is deposited on top of the semiconductor substrate and annealed in the presence of oxygen gas or nitrous oxygen to convert the Al layer into an Al2O3 layer. Thereafter, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.

Abstract: A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by forming a photoresist layer on the substrate such that a portion of the dielectric layer in the peripheral circuit region and in the memory cell region is exposed. The dielectric layer exposed by the photoresist layer is then removed, followed by removing the photoresist layer.

Abstract: A non-volatile semiconductor memory manufacturing method, according to the present invention, is comprised of the process steps that follow. Device isolating layers are formed on predetermined places in a cell region. A layer of floating gate material is deposited next, all over the substrate. Either all the layer of floating electrode material, deposited on the device isolating layers or a part of it, is removed next, by etching, in order to form ditches. To fill the ditches, a first insulation layer is formed next, all over the cell region. A predetermined part of the first insulation layer is removed next, by etching, so the layer of floating electrode material is exposed. Thereafter, the ditches are filled in, on top of the device isolating oxide layers, with insulation layers. A second insulation layer is formed next, all over the cell region. Thereafter, electrode material layers and are deposited on the surface.

Abstract: An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Abstract: A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region.

Abstract: A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

Abstract: A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask.

Abstract: A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. The trenches are formed using a stop layer so that the depth of the trenches may be precisely controlled. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region, a drain region, a first gate electrode, and a second gate electrode.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused using the gate spacer and the gate polysilicon layer as a mask layer to form a source/drain region in the substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer, and the gate polysilicon layer, and then, a dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. The exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer are exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.

Abstract: The present invention provides a method of using organic polymer as a covering layer for a device lightly doped drain (LDD) structure, wherein a photo resist is covered by organic polymer, and ion implantation of different energies and kinds are performed to the same region of different line widths, thereby achieving the effect of LDD. Additionally, the covering layer of organic polymer is removed by means of simple and easy oxygen plasma etch so as not to increase the complexity of fabrication process. The complex fabrication process of a device LDD structure in the prior art is thus greatly improved.

Abstract: A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the substrate. A first impurity is implanted into the bit line regions of the substrate, wherein the first impurity is implanted through the ONO layer, through the openings of the mask. The first impurity is implanted at various angles, such that the first impurity is implanted in the substrate at locations beneath the mask. The upper oxide and nitride layers of the ONO layer are subsequently etched through the mask openings. A second impurity is implanted in the substrate through the openings of the mask. The mask is removed, and the substrate is oxidized, thereby forming bit line oxide regions over the bit line regions, and floating gate structures.

Abstract: This invention relates to a MIS transistor and its manufacturing process. The process comprises the following steps: a) production of a dummy grid on a substrate, made of a material capable of resisting heat treatment, b) formation of self-aligned source and drain regions on the dummy grid, in the substrate, c) lateral coating of the dummy grid with an electrically insulating layer, d) elimination of the dummy grid and formation of a final grid made of a material with low resistivity, in the same position as the dummy grid. Application to the manufacture of hyper-frequency circuits.

Abstract: A dual gate oxides' process for mixed-mode IC is provided. More particularly, the present invention relates to a dual gate oxides' process for mixed-mode IC, which protects and improves the dual gate oxides' quality.