Plural Gate Electrodes (e.g., Dual Gate, Etc.) Patents (Class 438/283)
  • Patent number: 11152221
    Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: October 19, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xuebin Li, Wei Liu, Gaurav Thareja, Shashank Sharma, Patricia M. Liu, Schubert Chu
  • Patent number: 11145748
    Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 11133307
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 11127741
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 11127639
    Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhen Geng, Kitchun Kwong, Taicheng Shieh, Bo-Shiuan Shie, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 11087987
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
  • Patent number: 11081583
    Abstract: A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Keith H. Tabakman, Henry K. Utomo
  • Patent number: 11075198
    Abstract: An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Cheng-ying Huang, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru
  • Patent number: 11069807
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Bo-Feng Young, Chi On Chui, Chih-Yu Chang, Huang-Lin Chao
  • Patent number: 11069812
    Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11063052
    Abstract: A semiconductor device and a fabrication method are provided. The method includes forming a first fin structure and a second fin structure on a substrate. The first fin structure includes a first sidewall surface, facing to the second fin structure, and a second sidewall surface opposite to the first sidewall surface. The method also includes forming an isolation layer to cover a portion of sidewall surfaces of the first fin structure and the second fin structure. The top surface of the isolation layer is lower than the top surfaces of the first fin structure and the second fin structure. The method further includes forming a first sidewall on the first sidewall surface; forming a first doped layer in the first fin structure; and forming a second doped layer in the second fin structure. The first sidewall covers a portion of a sidewall surface of the first doped layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation Shanghai, China, Semiconductor Manufacturing International (Beijing) Corporation Beijing, China
    Inventor: Fei Zhou
  • Patent number: 11049774
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 10998311
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes forming a fin over a substrate. The fin includes an upper fin region and a lower fin region. The lower fin region is physically coupled to the upper fin region and the substrate. A portion of the fin is removed to form a fin tunnel configured to physically separate the upper fin region from the lower fin region. A gate structure is formed and configured to fill the fin tunnel and cover a top surface, a bottom surface, a first sidewall, and a second sidewall of the upper fin region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10985277
    Abstract: A method includes forming a first semiconductor layer over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are etched to form a fin structure that extends from the substrate. The fin structure has a remaining portion of first semiconductor layer and a remaining portion of the second semiconductor layer atop the remaining portion of the first semiconductor layer. A capping layer is formed to wrap around three sides of the fin structure. At least a portion of the capping layer and at least a portion of the remaining portion of the second semiconductor layer in the fin structure are oxidized to form an oxide layer wrapping around three sides of the fin structure.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10974433
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Patent number: 10978450
    Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10971522
    Abstract: The subject disclosure relates to high mobility complementary metal-oxide-semiconductor (CMOS) devices and techniques for forming the CMOS devices with fins formed directly on the insulator. According to an embodiment, a method for forming such a high mobility CMOS device can comprise forming, via a first epitaxial growth of a first material, first pillars within first trenches formed within a dielectric layer, wherein the dielectric layer is formed on a silicon substrate, and wherein the first pillars comprise first portions with defects and second portions without the defects. The method can further comprise forming second trenches within a first region of the dielectric layer, and further forming second pillars within the second trenches via a second epitaxial growth of one or more second materials using the second portions of the first pillars as seeds for the second epitaxial growth.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10872892
    Abstract: A method of manufacturing a semiconductor device includes forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged. The first and second transistor structures are separated by etching the source/drain structures.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Long-Jie Hong, Kang-Min Kuo
  • Patent number: 10867997
    Abstract: A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Jayeol Goo, Sang Gil Kim
  • Patent number: 10861976
    Abstract: The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 8, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Meng Zhao
  • Patent number: 10847380
    Abstract: A semiconductor device is provided. The semiconductor device includes a core structure, a first pattern and a second pattern. The core structure is disposed on a substrate. The first pattern covers a sidewall of a bottom portion of the core structure. The top surface of the first pattern is lower than a top surface of the core structure. The second pattern is disposed on the first pattern and covering a top portion of the core structure. A sidewall of the top portion of the core structure and the top surface of the core structure are covered by the second pattern. The second pattern has an upper portion tapered away from the substrate. A material of the first pattern is different from a material of the second pattern.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 24, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Shu-Ming Li, Tzu-Ming Ou Yang, Ko-Po Tseng
  • Patent number: 10840153
    Abstract: A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10833206
    Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 10833177
    Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a substrate having a fin which has first fin layers and second fin layers; forming a dummy gate structure across the fin; after forming the dummy gate structure, respectively forming a first groove and a second groove in the fin on two sides of the dummy gate structure; removing a portion of the second fin layer adjacent to the first groove to form a first fin recess; removing a portion of the second fin layer adjacent to the second groove to form a second fin recess; forming a first spacer layer in the first fin recess and forming a second spacer layer in the second fin recess; after forming the first spacer layer, forming a doped drain layer in the first groove; and after forming the second spacer layer, forming a doped source layer in the second groove.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: November 10, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10825933
    Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsuan Hsiao, Wei-Sheng Yun, Winnie Victoria Wei-Ning Chen, Tung Ying Lee, Ling-Yen Yeh
  • Patent number: 10811541
    Abstract: A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 20, 2020
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Bum Kim, Hyoung Sub Kim, Seong Heum Choi, Jin Yong Kim, Tae Jin Park, Seung Hun Lee
  • Patent number: 10777554
    Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Patent number: 10770588
    Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chao-Ching Cheng, Chih-Hsin Ko, Hsingjen Wann
  • Patent number: 10756212
    Abstract: Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 25, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Stephen Smith, Qiang Lu
  • Patent number: 10734472
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10727427
    Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Timothy Vasen, Mark van Dal, Gerben Doornbos, Matthias Passlack
  • Patent number: 10692849
    Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 23, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10680063
    Abstract: Stacked SiGe nanotubes and techniques for the fabrication thereof are provided. In one aspect, a method of forming a SiGe nanotube stack includes: forming Si and SiGe layers on a wafer, one on top of another, in an alternating manner; patterning at least one fin in the Si and SiGe layers; depositing an oxide material onto the at least one fin; and annealing the at least one fin under conditions sufficient to diffuse Ge atoms from the SiGe layers along an interface between the oxide material and the Si and SiGe layers to form at least one vertical stack of SiGe nanotubes surrounding Si cores. A SiGe nanotube device and method for formation thereof are also provided.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee
  • Patent number: 10644109
    Abstract: After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy sublayer portions comprised of Si on sidewalls of a sacrificial fin located on a substrate, the sacrificial fin is removed, leaving the semiconductor fins protruding from a top surface of the substrate. The SiGe and Si digital alloy sublayer portions are formed using isotopically enriched Si and Ge source gases to minimize isotopic mass variation in the SiGe and Si digital alloy sublayer portions.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10636790
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method comprises forming active patterns on a substrate that includes first and second logic cell regions adjacent to each other in a first direction, and forming on the substrate a device isolation layer exposing upper portions of the active patterns. The forming the active patterns comprises forming first line mask patterns extending parallel to each other in the first direction and running across the first and second logic cell regions, forming on the first line mask patterns an upper separation mask pattern including a first opening overlapping at least two of the first line mask patterns, forming first hardmask patterns from the at least two first line mask patterns, and etching the substrate to form trenches defining the active patterns.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-chul Oh, Sejin Park
  • Patent number: 10580864
    Abstract: The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 3, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 10566417
    Abstract: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Masaharu Kobayashi, Effendi Leobandung
  • Patent number: 10546770
    Abstract: A method of forming a semiconductor device. The method may include providing a semiconductor device structure. The semiconductor device structure may include a semiconductor fin; and a mask, disposed over the semiconductor fin, the mask defining a plurality of openings, wherein the semiconductor fin is exposed in the plurality of openings. The method may further include directing angled ions into the plurality of openings, wherein a plurality of trenches are formed in the semiconductor fin, wherein a given trench of the plurality of trenches comprises a reentrant profile.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: January 28, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: Min Gyu Sung
  • Patent number: 10522685
    Abstract: The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corp., Semiconductor Manufacturing International (Shanghai) Corp.
    Inventor: Meng Zhao
  • Patent number: 10504786
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert
  • Patent number: 10483392
    Abstract: A radio frequency (RF) integrated circuit (RFIC) switch multi-finger transistor includes a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate. The RFIC also includes a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate. The second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC switch multi-finger transistor.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Ravi Pramod Kumar Vedula
  • Patent number: 10468306
    Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.
    Type: Grant
    Filed: April 1, 2018
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic Gaben
  • Patent number: 10461080
    Abstract: A method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, at first, a semiconductor substrate of a wafer is etched to form at least one fin. Then, an insulation structure is formed around the fin. Thereafter, the fin is recessed. Then, an epitaxial channel structure is epitaxially grown over the recessed fin. Thereafter, a portion of the epitaxial channel structure over a top surface of the insulation structure is removed. Then, a non-contact-type cleaning operation is performed to clean a top surface of the wafer after removing said portion of the epitaxial channel structure. Thereafter, the top surface of the wafer is cleaned using hydrogen fluoride after removing said portion of the epitaxial channel structure. Then, the insulation structure is recessed, such that the epitaxial channel structure protrudes from the recessed insulation structure.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shen-Nan Lee, Kuo-Yin Lin, Pin-Chuan Su, Teng-Chun Tsai
  • Patent number: 10446561
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10446393
    Abstract: A method for forming a silicon-containing epitaxial layer is disclosed. The method may include, heating a substrate to a temperature of less than approximately 950° C. and exposing the substrate to a first silicon source comprising a hydrogenated silicon source, a second silicon source, a dopant source, and a halogen source. The method may also include depositing a silicon-containing epitaxial layer wherein the dopant concentration within the silicon-containing epitaxial layer is greater than 3×1021 atoms per cubic centimeter.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 15, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Nupur Bhargava, John Tolle, Joe Margetis, Matthew Goodman, Robert Vyne
  • Patent number: 10424580
    Abstract: Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Gopinath Bhimarasetti, Tahir Ghani, Seiyon Kim
  • Patent number: 10381479
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10355140
    Abstract: The present disclosure provides a manufacturing method for a transistor with an SONOS structure, including providing a semiconductor substrate, wherein the semiconductor substrate includes a select transistor well and a memory transistor well; depositing an oxide layer on an upper surface of the select transistor well, depositing an ONO memory layer on an upper surface of the memory transistor well, depositing a barrier wall over adjacent portions of the select transistor well and the memory transistor well, depositing polycrystalline silicon covering the oxide layer, the ONO memory layer, and the barrier wall, and etching the polycrystalline silicon, to retain the polycrystalline silicon deposited on both sides of the barrier wall so as to form a select gate and a memory gate, and removing the oxide layer and the ONO layer on a surface of the semiconductor substrate other than the select gate, the barrier wall, and the memory gate.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Xiaoliang Tang
  • Patent number: 10347767
    Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros, Ashish Agrawal
  • Patent number: 10332802
    Abstract: Integrated chips include a first device and a second device. The first device includes a stack of vertically arranged sheets of a first channel material, a source and drain region having a first dopant type, and a first work function metal layer formed from a first work function metal. The second device includes a stack of vertically arranged sheets of a second channel material, a source and drain region having a second dopant type, and a second work function metal layer formed from a second work function metal.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Wenyu Xu