Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.

Abstract: An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a target. The PVD process is followed by annealing, during which ultra-shallow junctions and ultra-thin metal silicide are formed. After removing the mixture film remaining on the semiconductor substrate, an ultra-shallow junction semiconductor field-effect transistor is formed. Because the mixture film comprises metal and semiconductor dopants, ultra-shallow junctions and ultra-thin metal silicide can be formed in a same annealing process. The ultra-shallow junction thus formed can be used in semiconductor field-effect transistors for the 14 nm, 11 nm, or even further technology node.

Abstract: Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.

Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.

Abstract: A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.

Abstract: In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract: The effects of random telegraph noise signal (RTS) or equivalently l/f noise on MOS devices, circuits, and sensors is described. Techniques are disclosed for minimizing this RTS and low frequency noise by minimizing the number of ionized impurity atoms in the wafer, substrate, well, pillar, or fin behind the channel of the MOS transistors. This noise reduction serves to reduce the errors in devices, sensors, and analog integrated circuits and error rates in digital integrated circuits and memories.

Abstract: A method of forming an IC includes forming a first and a second gate portion using a poly mask. The first portion includes a first active poly gate having a line width W1 over an end of a first active area framed by a first active area edge and a first adjacent active field poly feature having a line width 0.8W1 to 1.3W1 in a first field region. The first field poly feature has a horizontal portion and a first extension portion along a gate width direction extending over the first active area edge having a first minimum spacing (S1). The second gate portion includes a second active poly gate over an end of a second active area framed by a second active area edge electrically connected to a second field poly feature in a second field region having a horizontal portion and a second extension portion along a gate width direction extending over the second active area edge having a second minimum spacing (S2). A dummy field poly feature is between the second active poly gate and the second field poly feature.

Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

Abstract: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of a plurality of crystals which may be columnar crystals and/or capillary crystal substantially parallel to the substrate. The resultant structure is then subject to thermal oxidation in a chosen atmosphere containing halogen, thereby removing away any metallic element as contained in the film. This may enable formation of a mono-domain region in which the individual columnar or capillary crystal is in contact with any adjacent crystals and which is capable of being substantially deemed to be a single-crystalline region without presence or inclusion of any crystal grain boundaries therein. This region is for use in forming the active layer of the transistor.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench.

Abstract: A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.

Abstract: A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the gate electrode; first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain; and second electric field relaxation layers one of which is formed between the source and the gate electrode, and another one of which is formed between the drain and the gate electrode.

Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.

Abstract: A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60?), one (60) forming the reference current (RC) side (601) and the other (60?) forming the mirror current side (602) of the CCM (74). The gates (65, 65?) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66?, 66?) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601).

Abstract: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to increase a channel area so as to simplify process steps, thereby improving the yield and productivity for manufacturing a semiconductor device.

Abstract: Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member electrically insulatively coupled to the nanotube member so as to be aligned with the source region and the drain region, wherein the electromechanical deflection of the nanotube member is controllable, in response to an electrical potential applied to the gate and the nanotube member, between an off state and an on state, the on state placing the channel member in electrical connection with the source region and the drain region to form a current path.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.

Abstract: An improved aqueous soluble surfactant which has particular utility for incorporating in etchants for semiconductor devices is provided. The surfactant comprises a combination of a linear perfluorocarboxylic acid, a cyclic amine and an aliphatic alcohol.

Abstract: An improved etching and cleaning composition for semiconductor devices is provided in which the etch solution incorporates a novel surfactant comprising a combination of a linear perfluorocarboxylic acid, a cyclic amine and an aliphatic alcohol.

Abstract: The invention relates to a method of fabricating a structure with field-effect transistors each comprising a source electrode, a drain electrode, a channel extending between the source and drain electrodes and at least one gate electrode associated with the channel for controlling the conductance of the channel, wherein the channel comprises one or more semiconducting single-wall carbon nanotubes.

Abstract: A technique for selecting an optimal quantization direction for a given transport direction in a semiconductor device such as a field effect transistor (FET), a method for preparing a wafer for fabricating such a semiconductor device, and the semiconductor device fabricated by the method. A switching time is calculated for different candidate quantization directions, and for a given current transport direction. The quantization direction that results in the lowest switching time is then determined. In a specific example, Ge nFET performance is enhanced by 12% using the [1 1 0] and [{overscore (4)} 4 21] crystallographic directions for transport and quantization, respectively. Quantization in the [{overscore (1)} 1 0] direction was previously considered optimal.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not have a permitted energy state in the energy interval which is used to control the charge carrier density in the inversion channel between the source electrode and the drain electrode.

Abstract: A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

Abstract: A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract: A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.

Abstract: A CCD and method of fabricating the same, which reads signal charges completely and increases the fill factor of its pixel, to improve the sensitivity. The CCD having photodiodes in matrix form, includes a first interlevel insulating layer and first transfer gate sequentially formed between the photodiodes arranged in the row direction, a block insulating layer formed along the center of the first transfer gate, a second interlevel insulating layer formed on the first transfer gate, second and third transfer gates formed on the first transfer gate, being isolated from each other on the block insulating layer, a third interlevel insulating layer formed on the second and third transfer gates, and a fourth transfer gate formed on the third interlevel insulating layer, being placed on the second and third transfer gates.

Abstract: A fabrication method for a silicon nitride read-only memory is described. A silicon nitride read-only memory and a grounding doped region are formed in the substrate. A contact is formed on the substrate. A metal protection line is also formed, wherein the metal protection line is electrically connected to the word line of the silicon nitride read-only memory. Moreover, the metal protection line is electrically connected the grounding doped region through the contact to conduct charges generated during the manufacturing process to the substrate. The resistance of the metal protection line is higher than that of the word line. A high current is then used to bum out the metal protection line after the formation of the metal interconnect on the substrate to ensure a normal function of the memory device.

Abstract: A method of fabricating a dynamic threshold voltage metal oxide semiconductor (DTMOS) for operation at threshold voltages less than 0.6 volts includes preparing a silicon substrate to form a trench in an active area; forming a silicon layer in the trench; doping the silicon layer in the trench to form a highly doped layer, having a doping ion concentration in a range of between about 5.0·1017 cm−3 and 5.0·1018 cm−3; depositing a silicon layer over the high doped silicon layer; and completing the structure to form a DTMOS transistor.

Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating an impurity and a catalyst metal on the amorphous silicon layer using the gate electrode as a mask; and applying a DC voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.

Abstract: An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.