Total Dielectric Isolation Patents (Class 438/295)
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Patent number: 6884687Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.Type: GrantFiled: November 25, 2002Date of Patent: April 26, 2005Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6867086Abstract: High density plasma chemical vapor deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots are provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. The etch back part of the process involves an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality gap fill operations.Type: GrantFiled: March 13, 2003Date of Patent: March 15, 2005Assignee: Novellus Systems, Inc.Inventors: David Chen, Robert A. Shepherd, Jr., Vishal Gauri, George D. Papasouliotis
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Patent number: 6861311Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.Type: GrantFiled: November 25, 2002Date of Patent: March 1, 2005Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6828198Abstract: A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.Type: GrantFiled: March 19, 2003Date of Patent: December 7, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Der Su, Shien-Yang Wu, Yung-Shun Chen, Tung-Heng Shie, Yuan-Hung Chiu
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Patent number: 6790677Abstract: A method of forming a ferroelectric film includes the steps of forming a layer by a material that takes a metal state in a reducing ambient and an oxide state in an oxidizing ambient, and depositing a ferroelectric film on a surface of the layer by supplying gaseous sources of the ferroelectric film and an oxidizing gas and causing a decomposition of the gaseous sources at the surface of said layer, wherein the step of depositing the ferroelectric film is started with a preparation step in which the state of the surface of said layer is controlled substantially to a critical point in which the layer changes from the metal state to the oxide state and from the oxide state to the metal state.Type: GrantFiled: January 9, 2003Date of Patent: September 14, 2004Assignee: Fujitsu LimitedInventor: Hideki Yamawaki
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Patent number: 6787401Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 22, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6764922Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: GrantFiled: November 7, 2003Date of Patent: July 20, 2004Assignee: International Business Machines CorporationInventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
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Patent number: 6764921Abstract: A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.Type: GrantFiled: July 31, 2003Date of Patent: July 20, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Imade, Hiroyuki Umimoto
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Patent number: 6737328Abstract: In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.Type: GrantFiled: February 2, 2000Date of Patent: May 18, 2004Assignee: Micron Technology, Inc.Inventors: Sujit Sharan, Gurtej S. Sandhu
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Publication number: 20040092094Abstract: The present invention provides a unique methodology for device and process technology that results in significant improvements in the parameters of the active devices of all integrated technologies including: bipolar, CMOS, BiCmos, BCD (Bipolar, Cmos, DMOS), and DMOS. The approach results in fewer process steps than the standard approach in each of these technologies, while providing lower capacitance, higher speed, lower power dissipation, lower Ron, lower ground resistance, lower output resistance, reduced de-biasing at high current, higher breakdown voltage, higher beta and over a broader current range while providing significant reduction in die size. Use of this approach also results in improved Schottky diodes and solar cells.Type: ApplicationFiled: September 24, 2003Publication date: May 13, 2004Inventor: John Durbin Husher
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Patent number: 6709908Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.Type: GrantFiled: February 23, 2001Date of Patent: March 23, 2004Assignee: Seiko Epson CorporationInventors: Yoko Sato, Akihiko Ebina
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Patent number: 6656806Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.Type: GrantFiled: March 11, 2002Date of Patent: December 2, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Min-Su Kim
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Patent number: 6656786Abstract: A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate during a front end manufacturing operation of the capacitor on the substrate. An inter-metal dielectric layer is deposited upon the substrate, followed thereafter by a chemical mechanical polishing operation. Additionally, a lithographic operation is performed upon the substrate. Also, at least one dielectric deposition layer is generally on the substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on the substrate. At least one metal two layer may then be formed on substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof.Type: GrantFiled: November 2, 2001Date of Patent: December 2, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiung Chiang, Hsiao-Hui Tseng, Hsien-Yuan Chang, Tazy-Schiuan Yang
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Patent number: 6596584Abstract: A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask.Type: GrantFiled: October 19, 2000Date of Patent: July 22, 2003Assignee: Texas Instruments IncorporatedInventors: Sarma S. Gunturi, Paul A. Chintapalli
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Patent number: 6586284Abstract: The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications.Type: GrantFiled: July 1, 2002Date of Patent: July 1, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Min-su Kim
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Publication number: 20030119267Abstract: The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell and a method for manufacturing the same. The HSG flash memory cell of the present invention is located on a trench of an isolation region, and a channel region of the HSG flash memory cell composed of a semiconductor film is encompassed by a tunneling oxide layer, a floating gate, and a control gate in sequence. The floating gate and the control gate are also formed on the trench below the channel region. Therefore, the leakage current of the channel can be improved, and the short channel effect cannot be induced by junction depth of a source/drain. Furthermore, the coupling capacitor between the control gate and the floating gate is increased easily by increasing the depth of the trench.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Applicant: WINBOND ELECTRONICS CORPORATIONInventor: Wen-Yueh Jang
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Publication number: 20030092240Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.Type: ApplicationFiled: November 13, 2001Publication date: May 15, 2003Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITEDInventors: Siew Yong Kong, Alex See, Simon Chooi, Gautam Sarkar
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Patent number: 6562694Abstract: A method of manufacturing a semiconductor device including semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of process steps are carried out, commonly referred to as front-end processing, wherein, inter alia, the silicon wafer is heated to temperatures above 700° C. Subsequently, trenches (25) are formed in the top layer, which extend as far as the buried insulating layer and do not intersect pn-junctions. After said trenches have been filled with insulating material (26, 29), the semiconductor device is completed in a second series of process steps, commonly referred to as back-end processing, wherein the temperature of the wafer does not exceed 400° C. The trenches are filled in a deposition process wherein the wafer is heated to a temperature which does not exceed 500° C.Type: GrantFiled: December 21, 2000Date of Patent: May 13, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Ronald Dekker, Henricus Godefridus Rafael Maas, Cornelis Eustatius Timmering, Pascal Henri Leon Bancken
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Publication number: 20030087495Abstract: A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.Type: ApplicationFiled: November 26, 2002Publication date: May 8, 2003Applicant: Micron Technology, Inc.Inventors: Leonard Forbes, Wendell P. Noble
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Patent number: 6551898Abstract: This invention concerns a process of forming a polarizable layer in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. This process comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5-50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25-300 degrees Celsius. After implantation, an annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.Type: GrantFiled: November 1, 2001Date of Patent: April 22, 2003Assignee: The United States of America as represented by the Secretary of the NavyInventors: Harold L. Hughes, Patrick J. McMarr, Reed K. Lawrence
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Publication number: 20030059993Abstract: The manufacturing method of semiconductor devices including a MOSFET according to the present invention has a step of selectively forming element isolation films on the surface of a semiconductor substrate of first conductivity type, a step of forming a well region of the first conductivity type in a selected region between the element isolation films, a step of forming a gate insulation film on the surface of the semiconductor substrate and forming a first conductive film composed of amorphous silicon on top of it, a step of forming a gate electrode in a portion above the well region of the first conductivity type by patterning the first conductive film, a step of forming an oxide film by in-situ steam generation (ISSG) method on the side faces of the gate electrode, and a step of forming a source region and a drain region formed in self-alignment with the gate electrode by implanting a second conductivity type impurity into the well region of the first conductivity type using the gate electrode and the oxidType: ApplicationFiled: June 14, 2002Publication date: March 27, 2003Applicant: NEC CORPORATIONInventor: Katsuhiko Fukasaku
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Publication number: 20030045048Abstract: A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second monolayers comprising tantalum and oxygen and the other of the first and second monolayers comprising oxygen and another element different from tantalum. A dielectric layer can be formed containing the first and second monolayers. The dielectric layer can exhibit a dielectric constant greater than the first monolayer. The another element can include a Group IB to VIIIB element, such as titanium and/or zirconium. The forming of the first and second monolayer can include atomic layer depositing. A dielectric material can include first and second chemisorbed materials, the second material containing oxygen and a Group IB to VIIIB element and the dielectric material exhibiting a dielectric constant greater than the first chemisorbed material. The dielectric material can further exhibit less current leakage than the first material.Type: ApplicationFiled: August 30, 2001Publication date: March 6, 2003Inventor: Eugene P. Marsh
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Publication number: 20020197781Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.Type: ApplicationFiled: June 21, 2001Publication date: December 26, 2002Inventors: Andres Bryant, Meikei Ieong, K. Paul Muller, Edward J. Nowak, David M. Fried, Jed Rankin
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Patent number: 6498057Abstract: Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined burled conduction layer to be connected to a SOI transistor source, and an Intermediate conduction layer between the SOI transistor and the predefined buried conduction layer, A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silcide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An Insulator is disposed between the second hole and the intermediate conduction layer.Type: GrantFiled: March 7, 2002Date of Patent: December 24, 2002Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, John Edward Sheets, II, Gregory John Uhlmann
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Patent number: 6486015Abstract: Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.Type: GrantFiled: April 25, 2000Date of Patent: November 26, 2002Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Nirmal Chaudhary, Richard A. Conti
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Patent number: 6482718Abstract: A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).Type: GrantFiled: September 27, 2001Date of Patent: November 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Takashi Kuroi, Katsuyuki Horita
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Patent number: 6479369Abstract: A method of forming a shallow trench isolation, includes the steps, in sequence, of (a) forming a mask pattern on a silicon substrate, the mask pattern being made of a silicon dioxide layer and a silicon nitride layer, (b) forming a trench in the silicon substrate with the mask pattern being used as a mask, (c) forming a first silicon dioxide film covering an inner surface of the trench such that the trench is not filled with the first silicon dioxide film, (d) heating the first silicon dioxide film, (e) forming a second silicon dioxide film over a product resulted from the step (d) such that the trench is filled with the second silicon dioxide film, (f) heating the second silicon dioxide film, (g) polishing the first and second silicon dioxide films through the use of the silicon nitride layer as a stopper, (h) etching the silicon nitride layer for removal, and (i) etching the first and second silicon dioxide films such that the first and second silicon dioxide films are on a level with a surface of the siliType: GrantFiled: November 6, 2000Date of Patent: November 12, 2002Assignee: NEC CorporationInventor: Kousuke Miyoshi
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Patent number: 6472254Abstract: N+ or P+ diffusions are formed in a lightly doped P type or N type starting wafer. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) diffusions. The trenches extend through the thin device layer to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of the tubs. At least one diffusion of each cell is connected to a diffusion of an adjacent cell to connect each of a predetermined number of the cells. The N+ or (P+) diffusions may be each enclosed by a ring shaped P+ or N+ contact diffusion. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.Type: GrantFiled: December 21, 2000Date of Patent: October 29, 2002Assignee: International Rectifier CorporationInventors: William F. Cantarini, Steven C. Lizotte
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Publication number: 20020155666Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced.Type: ApplicationFiled: March 22, 2002Publication date: October 24, 2002Inventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa, Kazumasa Hasegawa, Eiji Natori
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Publication number: 20020155667Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.Type: ApplicationFiled: March 22, 2002Publication date: October 24, 2002Inventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa, Kazumasa Hasegawa, Eiji Natori
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Patent number: 6465313Abstract: A semiconductor device and a method of forming same are disclosed.Type: GrantFiled: July 5, 2001Date of Patent: October 15, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Ralf van Bentum
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Publication number: 20020146886Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. Control gates are each formed with a substantially vertical face portion by covering a portion of a conductive layer with a protective layer, and performing an anisotropic etch to remove the exposed portion of the conductive layer. An insulation sidewall spacer is formed against the vertical face portion. The control gates have protruding portions that extend over the floating gates.Type: ApplicationFiled: July 26, 2001Publication date: October 10, 2002Inventor: Geeng-Chuan Chern
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Patent number: 6455894Abstract: Provided are a semiconductor device capable of satisfactorily solving a floating-body problem and a hot carrier problem which often arise in an SOI device and of causing a widely distributed partial isolating film to generate a crystal defect for peripheral structures with difficulty and a method of manufacturing the semiconductor device. A dummy region DM1 having no function as an element is formed at almost regular intervals in a partial isolating film 5b provided between MOS transistors TR1. Consequently, the occupation rate of the dummy region DM1 having a lower resistance value than that of a silicon layer 3b provided under the partial isolating film 5b is increased so that the floating-body problem and the hot carrier problem can be solved.Type: GrantFiled: October 3, 2000Date of Patent: September 24, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
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Patent number: 6417030Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.Type: GrantFiled: February 20, 2001Date of Patent: July 9, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Matthew S. Buynoski, Donald L. Wollesen
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Patent number: 6403429Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.Type: GrantFiled: May 3, 2001Date of Patent: June 11, 2002Assignee: Micron Technology, Inc.Inventor: Wendell P. Noble
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Patent number: 6380037Abstract: A method of manufacturing a line type or area type image sensor integrated circuit device with a high resolution is provided. In a semiconductor integrated circuit device using an SOI substrate, a signal processing circuit is formed in an SOI region while a photodiode is formed in a bulk region to have a trench structure in which a diffusion layer is formed on the side walls and the bottom of the trench, and the inside of the trench is coated with an insulting film, or an insulating film and polycrystalline silicon provided with an electric potential. With such a manufacturing method, a semiconductor integrated circuit device mounting a photodiode showing sufficient S/N ratio is provided despite of its small cell size.Type: GrantFiled: April 4, 2000Date of Patent: April 30, 2002Assignee: Seiko Instruments Inc.Inventor: Jun Osanai
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Patent number: 6365468Abstract: A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region.Type: GrantFiled: June 21, 2000Date of Patent: April 2, 2002Assignee: United Microelectronics Corp.Inventors: Wen-Kuan Yeh, Tony Lin, Chih-Yung Lin
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Patent number: 6306691Abstract: In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.Type: GrantFiled: December 22, 1999Date of Patent: October 23, 2001Assignee: NEC CorporationInventor: Risho Koh
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Patent number: 6300204Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.Type: GrantFiled: May 11, 1999Date of Patent: October 9, 2001Inventor: Wendell P. Noble
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Patent number: 6300172Abstract: A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls.Type: GrantFiled: October 1, 1999Date of Patent: October 9, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Ting Cheong Ang, Shyue Pong Quek, Lap Chan, Sang Yee Loong
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Patent number: 6232141Abstract: A semiconductor light-receiving device including (a) a semiconductor substrate, (b) a multi-layered including a first buffer layer having a first electrical conductivity and lying on the semiconductor substrate, a first clad layer having a first electrical conductivity and lying on the first buffer layer, a light-absorbing layer having a first electrical conductivity and lying on the first clad layer, a second clad layer having a second electrical conductivity and lying on the light-absorbing layer, and a second buffer layer having a second electrical conductivity and lying on the second clad layer, (c) a first electrode formed on the second buffer layer, and (d) a second electrode formed on a lower surface of the semiconductor substrate. The multi-layered structure has at least one portion which is inclined to a direction in which a light introduced into the device is directed. For instance, the multi-layered structure has opposite end portions inclined to the direction.Type: GrantFiled: December 7, 1999Date of Patent: May 15, 2001Assignee: NEC CorporationInventor: Atsuhiko Kusakabe
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Patent number: 6228713Abstract: A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.Type: GrantFiled: June 28, 1999Date of Patent: May 8, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yelehanka Ramachandramurthy Pradeep, Vijay Kumar Chhagan, Jie Yu, Mei Sheng Zhou
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Patent number: 6218248Abstract: A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.Type: GrantFiled: April 2, 1999Date of Patent: April 17, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jeong Mo Hwang, Jeong Hwan Son
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Patent number: 6217357Abstract: In a method of manufacturing a two-type power supply voltage compatible CMOS semiconductor, the number of photolithography steps that aim at forming an LDD, a pocket, and a source/drain region is reduced so that time and cost are economized. For this purpose, an LDD structure of a low power supply voltage compatible portion and an LDD structure of a high power supply voltage compatible portion are formed at once and not separately.Type: GrantFiled: August 23, 1999Date of Patent: April 17, 2001Assignee: NEC CorporationInventor: Sadaaki Masuoka
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Patent number: 6146970Abstract: A method for forming a capped shallow trench isolation (CaSTI) structure begin by etching a trench opening (210). The opening (210) is filled with an oxide or like trench fill material (216b) via a deposition and chemical mechanical polish (CMP) step. The plug (216b) is reactive ion etched (RIE) to recess a top of the plug (216b) into the trench opening (210) to form a recessed plug region (216c). A silicon nitride or oxynitride capping layer (218b) is then formed over the recessed plug region (216c) via another deposition and polishing step. The nitride cap layer (218b) protects the underlying region (216c) from erosion due to active area preparation, cleaning, and processing.Type: GrantFiled: May 26, 1998Date of Patent: November 14, 2000Assignee: Motorola Inc.Inventors: Keith E. Witek, Mike Hsiao-Hui Chen, Stephen Shiu-Kong Poon
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Patent number: 6103574Abstract: In a non-volatile semiconductor memory device making electrical writing and erasing possible, source diffusion layers arranged on a substrate and along at least control gate electrodes have, in one part thereof, inclined portions having an angle larger than an ion implantation angle. According to this, device isolation technique is used to lower the resistance of the source diffusion layer.Type: GrantFiled: July 21, 1999Date of Patent: August 15, 2000Assignee: NEC CorporationInventor: Shota Iwasaki
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Patent number: 6093611Abstract: A semiconductor process in which a first nitrogen bearing oxide is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then formed on the nitrogen bearing oxide. The first oxide and the silicon nitride layer are then patterned to expose an upper surface of the substrate over a trench region of the substrate. An isolation trench is then etched into the trench region of the substrate and a nitrogen bearing liner oxide is then formed on sidewalls and a floor of the trench. An isolation dielectric is then formed within the trench and, thereafter, the silicon nitride layer is removed from the wafer. A suitable thickness of the first nitrogen bearing oxide and of the liner oxide is in the range of approximately 30 to 100 angstroms. A consumption of adjacent active regions caused by the thermal oxidation process is preferably less than approximately 50 angstroms.Type: GrantFiled: December 19, 1997Date of Patent: July 25, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Derick Wristers, H. Jim Fulford, Jr.
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Patent number: 6043120Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.Type: GrantFiled: March 3, 1998Date of Patent: March 28, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Kathleen R. Early, Michael K. Templeton, Nicholas H. Tripsas, Maria C. Chan
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Patent number: 6033961Abstract: Two steps of planarizing are performed during isolation trench fabrication resulting in a more uniform planarization of an integrated circuit substrate. A protective layer deposition and a planarizing step are performed prior to a final planarizing step. Applying protective material fills in a portion of recesses in a dielectric layer overlying isolation trench areas. A first global planarization process eliminates narrower recesses and shallows out deeper recesses without causing dishing in the dielectric material. Much of the protective material is removed by the first global planarization process. The remaining protective material is stripped. A final global planarization process then is performed which removes dielectric material outside of the trench areas. A well-defined border of the trenches results.Type: GrantFiled: April 30, 1998Date of Patent: March 7, 2000Assignee: Hewlett-Packard CompanyInventors: Jim-Jun Xu, Homayoon Haddad
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Patent number: 6030873Abstract: A semiconductor device which can prevent formation of a parasitic transistor and degradation in its threshold voltage is obtained. In the semiconductor device, a sidewall insulating film the width of which is increased toward its lower portion is formed on a side wall of a semiconductor layer, and a gate electrode layer is formed such that it extends on the semiconductor layer and the sidewall insulating film.Type: GrantFiled: April 14, 1997Date of Patent: February 29, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue