Including Isolation Structure Patents (Class 438/294)
  • Patent number: 10535734
    Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: January 14, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10510850
    Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10504782
    Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
  • Patent number: 10490460
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Patent number: 10418368
    Abstract: A method for forming a buried local interconnect in a source/drain region is disclosed including, among other things, forming a plurality of VOC structures, forming a first source/drain region between a first pair of the plurality of VOC structures, forming a second source/drain region between a second pair of the plurality of VOC structures, and forming an isolation structure between the first and second source/drain regions. A first trench is formed in the first and second source/drain regions and the isolation structure. A liner layer is formed in the first trench, and a first conductive line is formed in the first trench. A dielectric material is formed above the first conductive line. A first opening is formed in the dielectric material to expose a portion of the first conductive line. A first conductive feature is formed in the first opening contacting the exposed portion of the first conductive line.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven J. Bentley, Bipul C. Paul, Steven R. Soss
  • Patent number: 10388573
    Abstract: A method for fabricating a Fin-FET device includes providing a base structure and a plurality of fin structures protruding from the base structure. Along a direction perpendicular to the surface of the base structure and from the bottom to the top of each fin structure, the width of the fin structure perpendicular to the length direction of the fin structure decreases. The method further includes forming a gate structure on the base structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, and removing a portion of the fin structure on each side of the gate structure to form a trench in the fin structure. Along the length direction of the fin structure, the bottom width of the trench is smaller than the top width of the trench. The method also includes filling each trench with a doped source/drain epitaxial layer.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: August 20, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10366999
    Abstract: Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventor: Pierre Maillard
  • Patent number: 10249535
    Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Daniel Chanemougame, Lars Liebmann, Nigel Cave
  • Patent number: 10199259
    Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Michael Zier
  • Patent number: 10192779
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
  • Patent number: 10128377
    Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 9875944
    Abstract: A semiconductor device includes a substrate structure, multiple fins protruding from the substrate structure, each of the fins having a first portion, a second portion on opposite sides of the first portion, and a third portion at an outer side of the first portion and adjacent to the second portion, a gate structure on the upper surface of the first portion, sidewall spacers on opposite sides of the gate structure and covering the upper surface of the second portion, and source and drain regions outside of the sidewall spacers. The source and drain regions each have an upper surface higher than the second portion upper surface. The first portion protrudes from the second portion. The upper surface of the second portion is lower than the first portion upper surface. The upper surface of the third portion is lower than the second portion upper surface.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: January 23, 2018
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 9865682
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9865596
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: January 9, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang
  • Patent number: 9853074
    Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: December 26, 2017
    Assignee: XINTEC INC.
    Inventors: Ho-Yin Yiu, Chi-Chang Liao, Shih-Yi Lee, Yen-Kang Raw
  • Patent number: 9818842
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9799600
    Abstract: Semiconductor fuses and methods of forming the same include forming a dummy gate on a semiconductor fin. A dielectric layer is formed around the dummy gate. The dummy gate is removed to expose a region of the semiconductor fin. The exposed region is metallized.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9659810
    Abstract: The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joanna Chaw Yane Yin, Chi-Hsi Wu, Kuo-Chiang Ting, Chen Kuang-Hsin
  • Patent number: 9640657
    Abstract: Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Qiuhua Han
  • Patent number: 9620418
    Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liang Li, Wei Lu, Lian Choo Goh, Yung Fu Alfred Chong, Fangyue Liu, Alex See
  • Patent number: 9570561
    Abstract: Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Yi-Ju Chen, Sheng-Fu Yu, I-Shan Huang, Kuan Yu Chen, Li-Yi Chen
  • Patent number: 9500946
    Abstract: A method for patterning a substrate is described. The method includes receiving a substrate having a patterned layer, wherein the patterned layer defines a first mandrel pattern, and wherein a first material layer of a first composition is conformally deposited over the first mandrel pattern. The method further includes partially removing the first material layer using a first gas cluster ion beam (GCIB) etching process to expose a top surface of the first mandrel pattern, open a portion of the first material layer at a bottom region adjacent a feature of the first mandrel pattern, and retain a remaining portion of the first material layer on sidewalls of the first mandrel pattern; and selectively removing the first mandrel pattern using one or more etching processes to leave a second mandrel pattern comprising the remaining portion of the first material layer that remained on the sidewalls of the first mandrel pattern.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: November 22, 2016
    Assignee: TEL Epion Inc.
    Inventors: Soo Doo Chae, Youngdon Chang, Il-seok Song, Noel Russell
  • Patent number: 9437733
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9437596
    Abstract: A semiconductor device includes a substrate, a first well of a first conductivity type formed within the substrate, a second well of a second conductivity type formed underneath the first well within the substrate and a third well of the second conductivity type formed horizontally to the first well within the substrate, and including a first region formed to a first depth from a surface of the substrate, and a second region formed to a second depth greater than the first depth from the surface of the substrate and connected to the second well.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 6, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Junichi Ariyoshi
  • Patent number: 9331203
    Abstract: Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 3, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9312382
    Abstract: Technologies are generally described for reduction of the characteristic on resistance for a transistor device. In some examples, a transistor device may include a source region, a drain region, an n-type epitaxial region between the source and drain regions, a p-type body region, and a deep p-type trench region formed below the body region. The trench region may be configured to charge compensate the n-type epitaxial region. In other examples, the characteristic on resistance may be reduced by replacing the silicon below the body region with lower resistance conductive material. A backside of a wafer that includes the transistor device may be thinned by using a support or carrier on the front side of the wafer to provide mechanical support, and etching trenches in both the substrate silicon and the epitaxial silicon located below the body region of the transistor device. The trenches may be subsequently filled with conductive material.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: April 12, 2016
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Bishnu Prasanna Gogoi
  • Patent number: 9312376
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kook-Tae Kim, Young-Tak Kim, Ho-Sung Son, Seok-Jun Won, Ji-Hye Yi, Chul-Woong Lee
  • Patent number: 9274410
    Abstract: Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: March 1, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Wai Lo, Todd Lukanc, Christie Marrian
  • Patent number: 9269626
    Abstract: An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9263357
    Abstract: According to various embodiments, a carrier may include: a hollow chamber spaced apart from a surface of the carrier; and at least one support structure within the hollow chamber connecting a first region of the carrier disposed over the hollow chamber with a second region of the carrier disposed below the hollow chamber, wherein at least a part of a surface of the at least one support structure is spaced apart from an inner surface of the hollow chamber, and wherein the at least one support structure includes an electrically insulating material.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: February 16, 2016
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventor: Steffen Bieselt
  • Patent number: 9245965
    Abstract: A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Balasubramanian S. Haran, Sanjay Mehta, Shom Ponoth, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert
  • Patent number: 9240325
    Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 19, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Sébastien Barnola, Yves Morand, Heimanu Niebojewski
  • Patent number: 9209202
    Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 8, 2015
    Assignee: Broadcom Corporation
    Inventors: Shom Surendran Ponoth, Changyok Park
  • Patent number: 9159812
    Abstract: A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Chien-Hsun Lin, Sheng-Fu Yu, Yu-Chang Liang, Kuan Yu Chen, Li-Yi Chen
  • Patent number: 9111992
    Abstract: A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 18, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jeoung Mo Koo, Purakh Raj Verma, Guowei Zhang
  • Patent number: 9087741
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Balasubramanian S. Haran
  • Publication number: 20150144878
    Abstract: A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Publication number: 20150137233
    Abstract: A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Applicant: MICROSEMI SOC CORPORATION
    Inventors: Fengliang Xue, Fethi Dhaoui, John McCollum
  • Patent number: 9035380
    Abstract: An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yun Chen, Kong-Beng Thei
  • Patent number: 9034702
    Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 19, 2015
    Assignee: Peking University
    Inventors: Ru Huang, Jiewen Fan, Yujie Ai, Shuai Sun, Runsheng Wang, Jibin Zou, Xin Huang
  • Patent number: 9034712
    Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Richard A. Phelps, Jed H. Rankin, Yun Shi
  • Publication number: 20150129940
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
  • Publication number: 20150129987
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
  • Publication number: 20150129933
    Abstract: When forming field effect transistors with a semiconductor alloy layer, e.g., SiGe, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the active region is not straight, but it rather defines an indentation, so that the active region protrudes into the isolation region in correspondence to the indentation. A gate is then formed on the surface of the device in such a way that a portion of the indentation is covered by the gate. An etching process is then performed, during which the gate acts as a screen. The etching thus gives rise to a cavity defined by a sidewall comprising portions exposing silicon, alternated to portions exposing the dielectric material of the isolation region.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventor: Robert Lutz
  • Publication number: 20150123180
    Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.
    Type: Application
    Filed: November 28, 2014
    Publication date: May 7, 2015
    Inventors: Yoshihiro SATO, Ryohei MIYAGAWA, Tokuhiko TAMAKI, Junji HIRASE, Yoshiyuki OHMORI, Yoshiyuki MATSUNAGA
  • Patent number: 9012979
    Abstract: A semiconductor device and method of manufacturing the same are provided. A device can include an LDMOS region and a high side region on a semiconductor substrate. The device can further include an insulating region separating the LDMOS region from the high side region and the insulating region can include a plurality of second conductive type wells, a plurality of second conductive type buried layer patterns, or both.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 21, 2015
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 9006064
    Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
  • Patent number: 9006066
    Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min-Hwa Chi, Hoong Shing Wong
  • Patent number: 9006070
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Patent number: 8999797
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yong-Soo Joung, Hyung-Kyun Kim, Jae-Soo Kim, Dong-Gun Hwang, Kyoung Yoo