Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.

Abstract: A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction.

Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).

Abstract: A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.

Abstract: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.

Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.

Abstract: The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.

Abstract: A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.

Abstract: The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.

Abstract: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed.

Abstract: A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.

Abstract: A semiconductor device of the present invention is manufactured by the following steps: forming a single-crystal semiconductor layer over a substrate having an insulating surface; irradiating a region of the single-crystal semiconductor layer with laser light; forming a circuit of a pixel portion using a region of the single-crystal semiconductor layer which is not irradiated with the laser light; and forming a driver circuit for driving the circuit of the pixel portion using the region of the single-crystal semiconductor layer which is irradiated with the laser light. Thus, a semiconductor device using a single-crystal semiconductor layer which is suitable for a peripheral driver circuit region and a single-crystal semiconductor layer which is suitable for a pixel region can be provided.

Abstract: An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of each of the grooves. An epi-silicon layer is formed to fill the grooves and cover the barrier layer. Gates are formed on the epi-silicon layer, and junction areas are formed in the silicon layer on both sides of the gates.

Abstract: To achieve electro-optical devices typified by active matrix liquid crystal display devices with higher productivity and yield and lower manufacturing cost by reducing the number of steps of manufacturing a terminal portion and a pixel portion having an inverted staggered thin film transistor, specifically by reducing the number of photomasks used in a photolithography process. In view of this object, a photomask (multitone photomask) formed in such a manner that a light-transmitting substrate is provided with a transmitting portion, a partially-transmitting portion having a function of reducing light intensity, and a light-blocking portion is employed. Moreover, a lift-off method which does not require an etching step in patterning of a source electrode and a drain electrode of the pixel portion and a source wiring that extends to the terminal portion is employed.

Abstract: In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention provides an SOI substrate having a desired shape even when a step is produced on a surface to be bonded. Between steps on the surface to be bonded, dummy patterns 302 are formed at predetermined intervals, and thus the warp of the substrate to be bonded can be suppressed, the adhesion between the bonded substrates can be ensured, and an SOI layer having a desired shape can be obtained.

Abstract: Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device 100 involves irradiating the marking film 21 with an energy beam through the transparent protective film 31 after the protective film 31 is formed, and such irradiation causes a chemical modification of the material of the marking film 21 to create the marks. According to the above-described process for manufacturing the semiconductor device 100, the region for the marking or the upper surface of the marking film 21 is sheathed by the protective film 31, so that a damage to the semiconductor chip 11 due to the generations of dust, exothermic heat, gas, stress or the like during the marking operation can be reduced. This allows achieving the process for manufacturing the semiconductor device 100 that provides a manufacture of better quality of the marks.

Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.

Abstract: A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.

Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.

Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.

Abstract: In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer to thereby leave an oxide film on a terrace portion of the wafer for support layer.

Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

Abstract: A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made of silicon nitride. Before flipping and bonding, a bounding layer, preferably made of amorphous silicon or polysilicon, is formed to bound drain and source areas. After flipping and bonding of the assembly on a second substrate, a second gate is formed in the gate cavity. At least partial silicidation of the bounding layer is then performed before the metal source and drain electrodes are produced.

Abstract: A process of fabricating a thin film semiconductor device is proposed, which is suitable for mass production and enables to lower the production cost. A first substrate is subject to anodization to form a porous layer thereon. Then, a thin film semiconductor layer is formed on the porous layer. Using the thin film semiconductor layer, a semiconductor device is formed, and wiring is formed between the semiconductor devices. After that, the semiconductor devices on the first substrate is bonded to a second substrate. The semiconductor devices are separated from the first substrate. Further, the semiconductor devices are electrically insulated by removing a part of the thin film semiconductor layer from the separated surface of the second substrate.

Abstract: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Abstract: The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects.

Abstract: A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the first sidewall spacers. A second hard mask is formed over the first material layer and the first sidewall spacers. Second sidewall spacers are formed on the second hard mask, and the second hard mask is removed. At least the first sidewall spacers are patterned using the second sidewall spacers as a mask.

Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

Abstract: The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).

Abstract: Shown are embodiments where a process of manufacturing a semiconductor element on a semiconductor wafer is shown. The semiconductor element is obtained by dividing the function-providing semiconductor wafer into functional elements. The function-providing semiconductor wafer is, at its first main surface, mechanically coupled to a handling wafer. The thinning is carried out in the coupled state of the function-providing semiconductor wafer, and the function-providing semiconductor wafer is divided in its state coupled to the handling wafer. During or after connecting the semiconductor element to a lead frame the mechanical coupling between the semiconductor element and the corresponding part of the handling wafer is destroyed. Other embodiments are also shown.

Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Abstract: One or more embodiments relate to a method of making a heterojunction bipolar transistor (HBT) structure. The method includes: forming a partially completed heterojunction bipolar transistor (HBT) structure where the partially completed heterojunction bipolar transistor (HBT) structure includes a silicon layer having an exposed surface and a nitride layer having an exposed surface. The method includes growing a first oxide on the silicon layer and etching the nitride layer using an etchant.

Abstract: Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.

Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.

Abstract: Methods and materials for silicon on insulator wafer production in which the doping concentration in a handle wafer is sufficiently high to inhibit dopant from diffusing from the bond wafer during or after bonding to the handle wafer.

Abstract: A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.

Abstract: A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.

Abstract: The disclosure includes methods of manufacturing a semiconductor device formed on an SOI structure. In one example, a first and second semiconductor layer is formed on a semiconductor substrate including a first region. The first semiconductor layer and the second semiconductor layer are removed from a second region to form a recess for a support. A support precursor layer is formed. A portion of the support precursor layer is removed to form a support coupling the recess and the second semiconductor layer. A part of the first and second semiconductor layer is etched using the support as a mask. The first semiconductor layer is etched and removed to form a cavity under the second semiconductor layer. The second semiconductor layer is thermally oxidized to form a buried insulating layer in the cavity and the support is removed from at least the first region to expose the second semiconductor layer.