Abstract: A method comprising providing a substrate and forming a device on the substrate, wherein forming the device includes printing at least one region of inorganic semiconductor on the substrate.

Abstract: The present invention provides a “collector-less” silcon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BIJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then stripping off the mask and the surface protection layer. A silicon dioxide layer (102) has a first tip surface (102a) corresponding to an area where the mask has not existed and having a relatively long distance from the major surface (100a), and a second top surface (102b) corresponding to an area where the mask has existed and having a relatively short distance from the major surface (100a). As this major surface (100a) is polished by a predetermined quantity, a semiconductor substrate is provided in which only a part of a single-crystal silicon substrate is a SOI substrate.

Abstract: A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value.

Abstract: According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried oxide layer, where the trench exposes a portion of the bulk silicon substrate, and where the trench is situated adjacent to an optical region of said silicon-on-insulator substrate. According to this exemplary embodiment, an epitaxial layer is formed on the exposed portion of the bulk silicon substrate in the trench. The epitaxial layer and the bulk silicon substrate form a bulk silicon electronic region of the silicon-on-insulator substrate.

Abstract: A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a first type of ions in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer. A second type of ions are implanted in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer at an oblique ion implantation angle wherein a lateral spread of second type ions is greater than a lateral spread of first type ions. Semiconductor devices fabricated in accordance to above said method is also provided.

Abstract: According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried oxide layer, where the trench exposes a portion of the bulk silicon substrate, and where the trench is situated adjacent to an optical region of said silicon-on-insulator substrate. According to this exemplary embodiment, an epitaxial layer is formed on the exposed portion of the bulk silicon substrate in the trench. The epitaxial layer and the bulk silicon substrate form a bulk silicon electronic region of the silicon-on-insulator substrate.

Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Abstract: A semiconductor device includes a semiconductor chip having at least an electrode pad and a device formed on a semiconductor layer on its surface, a seal cap having a recess portion facing the device which is adhered to the surface of the semiconductor chip, and a cavity as an airspace formed by the recess portion between the semiconductor chip and the seal cap. The semiconductor chip includes a stepped portion at a portion of the back surface opposite the surface to have an uneven thickness.

Abstract: A method for making a subsurface electrical contact on a micro-electrical-mechanical-systems (MEMS) device. The contact is formed by depositing a layer of polycrystalline silicon onto a surface within a cavity buried under a device silicon layer. The polycrystalline silicon layer is deposited in the cavity through holes etched through the device silicon and reseals the cavity during the polycrystalline silicon deposition step. The polycrystalline silicon layer can then be masked and etched, or etched back to expose the device layer of the micromachined device. Through the layer of polycrystalline silicon, a center hub of the device may be electrically contacted.

Abstract: A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.

Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.

Abstract: Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor on insulator (“SeOI”) structure can be formed using a donor substrate, a support substrate and an insulating layer. The donor substrate may be formed using CZ pulling of semiconductor material at a rate that results in the existence of vacancy clusters. An insulating layer for the SeOI structure can be formed by depositing an oxide layer on the donor or support substrate. An insulating layer can also be formed by thermal oxidizing the support substrate. An SeOI structure can be formed by combining the donor substrate, the support substrate, and the insulating layer there between, and detaching the combination including a thin layer of the donor substrate using a zone of weakness that was formed in the donor substrate.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to the glass substrate. The thin semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. An ultra-thin silicon layer bonded to a glass substrate, selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate, provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: Methods and apparatus provide for: a silicon on insulator structure, comprising: a glass substrate; a layer of semiconductor material; and a deposited barrier layer of between about 60 nm to about 600 nm disposed between the glass substrate and the semiconductor material, where the glass substrate and semiconductor material are bonded together via electrolysis.

Abstract: There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

Abstract: The present invention relates to semiconductor-on-insulator structures having strained semiconductor layers. According to one embodiment of the invention, a semiconductor-on-insulator structure has a first layer including a semiconductor material, attached to a second layer including a glass or glass-ceramic, with the CTEs of the semiconductor and glass or glass-ceramic selected such that the first layer is under tensile strain. The present invention also relates to methods for making strained semiconductor-on-insulator layers.

Abstract: A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas, and top electrode areas; etching to remove the exposed silicon (Si) surfaces; selectively forming metal sidewalls adjacent the hard mask; filling the memory areas with memory resistor material; removing the hard mask, exposing the underlying Si active device areas; forming an overlying layer of oxide; etching the oxide to form contact holes to the active device areas; forming diodes in the contact holes; and, forming bottom electrode lines overlying the diodes.

Abstract: The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

Abstract: A method for manufacturing a SOI wafer includes a step of heat-treating a wafer in a furnace to form an SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order and a step of unloading the SOI wafer from the furnace maintained at a temperature of 250° C. to 800° C. to transfer the SOI wafer to an atmosphere containing hydrogen or water. The steps are performed in that order.

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.

Abstract: A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.

Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.

Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.

Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

Abstract: A thin film transistor (TFT) and a manufacturing method thereof are provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the gate. A doped amorphous silicon layer is formed over a portion of the inter-gate dielectric layer at least covering the gate to serve as channel layer. Next, source/drain regions are formed over the channel layer.

Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.

Abstract: Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Abstract: A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).

Abstract: Atomic layer epitaxy (ALE) is applied to the fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors of the formula RE-(O, N, P)—(Si,Ge) are also disclosed, where RE=at least one selection from group of rare-earth metals, O=oxygen, N=nitrogen, P=phosphorus, Si=silicon and Ge=germanium. The presented ALE growth technique and material system can be applied to silicon electronics, opto-electronic, magneto-electronics and magneto-optics devices.

Abstract: The present invention intends to provide a technique that can improve the capacitance density while securing the withstand voltage of a capacitor element. In order to achieve the above object, the present inventive manufacturing method of a semiconductor device includes forming a metal film on a silicon oxide film, forming a SiN film on the metal film, forming a metal film on the SiN film, etching the upper most metal film with a photoresist film as a mask to form an upper electrode, thereafter forming a silicon oxide film that covers the upper electrode, patterning by etching the silicon oxide film and the SiN film with a photoresist film as a mask to form a capacitor insulating film and sputter-etching the lowermost metal film with the patterned silicon oxide film as a mask to form a lower electrode.

Abstract: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.

Abstract: To provide a method for manufacturing an electro-optical substrate having high reliability with high yield. The method for manufacturing an electro-optical substrate including a composite base plate obtained by joining a support plate to a semiconductor plate having single-crystal silicon precursor layer (semiconductor precursor layer) can include a step of forming a light-shielding layer, having a predetermined pattern, on the support plate, a step of forming an insulating layer on the light-shielding layer having the predetermined pattern, a step of providing semiconductor layers on the insulating layer, a step of oxidizing parts of the semiconductor layers to form oxide layers, and a step of removing the oxide layers. The oxide layers can have a thickness smaller than that of the insulating layer.

Abstract: A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (203), a first semiconductor layer (205), and a first dielectric layer (207) disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first dielectric layer which exposes a portion of the substrate; (c) forming a first doped region (209) in the exposed portion of the substrate; and (d) forming anode (211) and cathode (213) regions in the first implant region.

Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

Abstract: According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric acid and nitric acid. The method is compatible with currently available etch modules for removing metal from the wafer edge, wherein, depending on the hardware specifics, copper, barrier material and dielectric material may be removed in a single etch step, or a first etch step may be performed substantially without any nitric acid so as to avoid the formation of nitric oxides. In this way, the formation of instable layer stacks may be substantially avoided, thereby reducing the risk of material delamination from the substrate edge.

Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

Abstract: The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.

Abstract: A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

Abstract: The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating layer is formed so that a gate electrode surrounds the surface of a channel region. This structure allows the formation of a relatively a thick channel region and decreases the sensitivity of characteristics of the device dependent upon the thickness of the channel region.

Abstract: A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

Abstract: A method for producing a bipolar transistor is described, which comprises providing a layer sequence, which comprises a substrate, a first oxide layer and a SOI layer, generating a collector region in the substrate, generating a second oxide layer on the layer sequence, generating a base region in the first oxide layer, such that the base region is in contact with the SOI layer, generating an emitter region on the base region such that the emitter region is isolated from the SOI layer, and generating a collector contact, a base contact and an emitter contact. The present invention is based on the knowledge that the production of a bipolar transistor can be made significantly less expensive when the above layer sequence is used for its production, and thereby, the base region is generated in the BOX layer while the collector region is formed in the substrate. Thereby, otherwise required production process steps and particularly layer deposition steps, such as for a polysilicon or oxide layer, are saved.

Abstract: Photodiodes and methods of fabricating photodiodes are provided. For example, a method of fabricating a photodiode includes forming a buried layer of a first conductive type on a semiconductor substrate and forming a first intrinsic capping epitaxial layer on the buried layer. A first intrinsic epitaxial layer of the first conductive type is formed on the first intrinsic capping epitaxial layer. A first junction region of the first conductive type is formed in the first intrinsic epitaxial layer. A second intrinsic epitaxial layer of the second conductive type is formed on the first junction region and the first intrinsic epitaxial layer. A second intrinsic capping epitaxial layer is formed on the second intrinsic epitaxial layer. A second junction region of the first conductive type is formed such that the second junction region passes through the second intrinsic capping epitaxial layer and the second intrinsic epitaxial layer. The second junction region contacts the first junction region.

Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.