Substrate Dicing Patents (Class 438/33)
  • Patent number: 10343237
    Abstract: Laser processing of hard dielectric materials may include cutting a part from a hard dielectric material using a continuous wave laser operating in a quasi-continuous wave (QCW) mode to emit consecutive laser light pulses in a wavelength range of about 1060 nm to 1070 nm. Cutting using a QCW laser may be performed with a lower duty cycle (e.g., between about 1% and 15%) and in an inert gas atmosphere such as nitrogen, argon or helium. Laser processing of hard dielectric materials may further include post-cut processing the cut edges of the part cut from the dielectric material, for example, by beveling and/or polishing the edges to reduce edge defects. The post-cut processing may be performed using a laser beam with different laser parameters than the beam used for cutting, for example, by using a shorter wavelength (e.g., 193 nm excimer laser) and/or a shorter pulse width (e.g., picosecond laser).
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 9, 2019
    Assignee: IPG PHOTONICS CORPORATION
    Inventors: Jeffrey P. Sercel, Marco Mendes, Rouzbeh Sarrafi, Joshua Schoenly, Xiangyang Song, Mathew Hannon, Miroslaw Sokol
  • Patent number: 10340413
    Abstract: A semiconductor light emitting element includes a substrate and a semiconductor structure. The substrate has a first main surface, a second main surface and side surfaces. The side surfaces form a first altered area in which voids are positioned in a first imaginary line and a second imaginary line different from the first imaginary line in the thickness direction of the substrate. The semiconductor structure is provided on or above the first main surface of the substrate.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 2, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Hitoshi Minakuchi, Kenichi Matsui
  • Patent number: 10319598
    Abstract: A method and an apparatus for thinning a wafer are provided. The method for thinning a wafer, according to one embodiment of the present invention, comprises the steps of: irradiating a line beam focused at a specific depth of the wafer; scanning the wafer by using the line beam so as to form an interface at the specific depth of the wafer; and cleaving the wafer on which the interface is formed into a pattern wafer and a dummy wafer.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 11, 2019
    Assignee: HANWHA PRECISION MACHINERY CO., LTD.
    Inventor: Sung Wook Kim
  • Patent number: 10276747
    Abstract: A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 30, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Kai Shen Chen, Hsin Hsiung Huang, Wan Jung Lee, Pei Chia Chen, Yung Hsin Tai
  • Patent number: 10258975
    Abstract: Method of forming micro channels in a polymeric nanocomposite film is provided. The method includes combining one or more monomers to form a mixture and adding a plurality of carbon fibers with metal nanoparticles dispersed therein to the mixture prior to or concurrently with formation of a polymer from the monomers. The method also includes adding at least one hydrophobic agent and at least one plasticizer to the polymer to form the polymeric nanocomposite film and forming a plurality of laser-etched micro channels in a surface of the polymeric nanocomposite film.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 16, 2019
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY KANPUR
    Inventors: Nishith Verma, Janakarajan Ramkumar, Prateek Khare
  • Patent number: 10256367
    Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 10224471
    Abstract: Embodiments provide a light emitting device package including a substrate, a light emitting structure disposed under the substrate and including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, first and second electrodes connected to the first and second conductive semiconductor layers, a first pad connected to the first electrodes in first-first through-holes penetrating the second conductive semiconductor layer and the active layer, and a first insulation layer disposed between the first pad and the second conductive semiconductor layer and between the first pad and the active layer to cover the first electrodes in a first-second through-hole, and a second pad connected to the second electrode through a second through-hole penetrating the first insulation layer and electrically spaced apart from the first pad.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 5, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Youl Lee, Kwang Ki Choi
  • Patent number: 10199544
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 5, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 10186648
    Abstract: A display device includes: a display substrate including: a pixel area provided in plurality separated from each other, and a plurality of through holes separated from each other; a light-emitting diode provided in plurality arranged on the display substrate in the pixel areas thereof; and a wiring line provided in plurality on the display substrate, the wiring line including a first wiring line and a second wiring line which are each electrically connected to the light-emitting diode.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Mugyeom Kim
  • Patent number: 10153266
    Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Fischer, Carsten Ahrens, Damian Sojka, Andre Schmenn
  • Patent number: 10096753
    Abstract: A light emitting device has a lens, extended to outside of the mounting substrate on which a semiconductor a light emitting element is mounted, and leakage of light is reduced. A light emitting element, a substrate having the light emitting element mounted on its upper surface, and a lens, having a curved upper surface encloses the light emitting element and the upper surface of the substrate is included. From the bottom surface of the lens, a lower surface of the substrate is exposed. In a top view from a perpendicular direction to the upper surface of the substrate, the bottom surface of the lens includes an outer extending portion where the bottom surface is extended to outside of the substrate, and a inclined portion, which inclines with respect to a direction approximately in parallel to the upper surface of the substrate, at an end portion of the outer extending portion.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: October 9, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Tsuyoshi Okahisa, Yuta Oka, Daisuke Sanga
  • Patent number: 10084108
    Abstract: A method for manufacturing a light emitting element that includes preparing a wafer having a substrate and a semiconductor structure, the substrate including a plurality of protrusions at positions corresponding to lattice points on a regular triangular lattice. The method includes forming a plurality of first modified parts in the substrate by irradiating the substrate with a laser beam along first dividing lines, forming a plurality of second modified parts in the substrate by irradiating the substrate with a laser beam along second dividing lines, and dividing the wafer along the first modified parts and the second modified parts to obtain a plurality of light emitting elements.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 25, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Hiroaki Tamemoto, Chihiro Juasa
  • Patent number: 9972702
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 15, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, National Taiwan University
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • Patent number: 9962790
    Abstract: A support comprises a ceramic supporting surface, on which a circuit board may be placed for cutting to be performed by means of optical radiation generated by a laser. The ceramic supporting surface remains unchanged as said laser radiation hits it.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: May 8, 2018
    Assignee: JOT AUTOMATION OY
    Inventor: Tuomo Mämmilä
  • Patent number: 9882353
    Abstract: A method for fabricating a laser diode device includes providing a gallium and nitrogen containing substrate member having a surface region, forming a patterned dielectric material overlying the surface region to expose a portion of the surface region within a vicinity of an recessed region of the patterned dielectric material and maintaining an upper portion of the patterned dielectric material overlying covered portions of the surface region, and performing a lateral epitaxial growth overlying the exposed portion of the surface region to fill the recessed region and causing a thickness of the lateral epitaxial growth to be formed overlying the upper portion of the patterned dielectric material. The method also includes forming an n-type gallium and nitrogen containing material, forming an active region, and forming a p-type gallium and nitrogen containing material. The method further includes forming a waveguide structure in the p-type gallium and nitrogen containing material.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 30, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Po Shan Hsu, Melvin McLaurin, James W. Raring, Alexander Sztein, Benyamin Buller
  • Patent number: 9871350
    Abstract: A multi-wavelength light emitting device is manufactured by forming first and second epitaxial materials overlying first and second surface regions. The first and second epitaxial materials are patterned to form a plurality of first and second epitaxial dice. At least one of the first plurality of epitaxial dice and at least one of the second plurality of epitaxial dice are transferred from first and second substrates, respectively, to a carrier wafer by selectively etching a release region, separating from the substrate each of the epitaxial dice that are being transferred, and selectively bonding to the carrier wafer each of the epitaxial dice that are being transferred. The transferred first and second epitaxial dice are processed on the carrier wafer to form a plurality of light emitting devices capable of emitting at least a first wavelength and a second wavelength.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 16, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, Eric Goutain, James W. Raring, Paul Rudy, Vlad Novotny
  • Patent number: 9812543
    Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tek Po Rinus Lee, Jinping Liu, Ruilong Xie
  • Patent number: 9774170
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 26, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Patent number: 9755398
    Abstract: In an example, the present invention provides a method for manufacturing a gallium and nitrogen containing laser diode device. The method includes providing a gallium and nitrogen containing substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising of at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The method includes patterning the epitaxial material to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. The method includes transferring each of the plurality of dice to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch corresponding to the design width.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: September 5, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Alexander Sztein, Melvin McLaurin, Po Shan Hsu, James W. Raring
  • Patent number: 9698297
    Abstract: A method produces a light-receiving device by growing a light-receiving layer having an undoped multi-quantum well structure; growing a cap layer on the light-receiving layer while the cap layer is doped with a p-type impurity during its growth; growing a mesa structure; growing a protective film on surfaces of the mesa structure; and annealing to form a p-n junction. The mesa structure is defined by a surrounding trench. Alternatively, a selective growth mask can be formed on the light-receiving layer whereafter the cap layer is grown on the light-receiving layer by use of the mask. In the alternative, the p-n junction is formed by diffusing p-type impurity from a p-type contact layer of the cap layer through a concentration adjusting layer thereof to the light-receiving layer.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 4, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yasuhiro Iguchi, Youichi Nagai
  • Patent number: 9673086
    Abstract: A method of producing a bonded wafer in which wafers each having a cutout portion are used as a bond wafer and a base wafer, and either or both of settings of an ion implanter with which ions are implanted and conditions of the ion implantation are adjusted in the step of implanting the ions such that a cutout portion of either or both of the bond wafer and the base wafer after bonding is located at within a range of 0±30° or 180±30° from a position at which separation of the bond wafer begins in the step of separating the bond wafer. This method can inhibit the occurrence of large fault defect that may be generated on a surface of a thin film right after the separation, when a thin film such as an SOI layer is formed by the ion implantation separation method.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: June 6, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Isao Yokokawa, Masahiro Kato
  • Patent number: 9633901
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first semiconductor element and a second semiconductor element in a semiconductor wafer. The first semiconductor element includes a first electrode formed on a front surface of the semiconductor wafer. The second semiconductor element is adjacent to the first semiconductor element and includes a second electrode formed on the front surface. The method further includes forming a first insulating layer on the front surface located at a first boundary portion between the first electrode and the second electrode; applying a specific potential different from a potential of the second electrode on the first electrode after the formation of the first insulating layer; and cutting the semiconductor wafer at the first boundary portion so as to divide the first semiconductor element from the second semiconductor element.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 25, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akitaka Soeno, Sachiko Aoi, Shinichiro Miyahara
  • Patent number: 9577154
    Abstract: A light emitting chip includes a light emitting unit, a eutectic layer and a surface passivation layer. The eutectic layer has a first surface and a second surface opposite to each other. The light emitting chip connects to the first surface of the eutectic layer. The surface passivation layer covers the second surface of the eutectic layer. A material of the surface passivation layer includes at least a metal of an oxidation potential from ?0.2 volts to ?1.8 volts.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: February 21, 2017
    Assignee: Genesis Photonics Inc.
    Inventors: Yu-Yun Lo, Yi-Fan Li, Chih-Ling Wu, Yi-Ru Huang, Jing-En Huang, Shao-Ying Ting
  • Patent number: 9520697
    Abstract: A method for manufacturing a multi-emitter laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 13, 2016
    Assignee: SORAA LASER DIODE, INC.
    Inventors: Dan Steigerwald, Melvin McLaurin, Eric Goutain, Alexander Sztein, Po Shan Hsu, Paul Rudy, James W. Raring
  • Patent number: 9508899
    Abstract: A light emitting element manufacturing method includes a wafer preparing process of preparing the semiconductor wafer, and a wafer dividing process of dividing the semiconductor wafer. In the wafer dividing process, in a vertical dividing region, a line position shifted by a predetermined distance from a center line of the vertical dividing region in a width direction to one side in the width direction is taken as the cutting start point to divide the semiconductor wafer.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: November 29, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Akinori Yoneda
  • Patent number: 9431589
    Abstract: A packaged LED device having a textured encapsulant that is conformal with a mount surface on which at least one LED chip is disposed. The textured encapsulant, which can be textured using an additive or subtractive process, is applied to the LED either prior to or during packaging. The encapsulant includes at least one textured surface from which light is emitted. The textured surface helps to reduce total internal reflection within the encapsulant, improving the extraction efficiency and the color temperature uniformity of the output profile. Several chips can be mounted beneath a single textured encapsulant. A mold having irregular surfaces can be used to form multiple encapsulants over many LEDs simultaneously.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: August 30, 2016
    Assignee: CREE, INC.
    Inventors: Ban P. Loh, Chenhua You, Bernd Keller, Nathaniel O. Cannon, Mitch Jackson, Ernest W. Combs
  • Patent number: 9385268
    Abstract: A method of manufacturing semiconductor chips includes: forming grooves on a front face side of a substrate; and forming grooves on a back face side of the substrate as defined herein, and in manufacturing conditions in which a variation range of a top section of the cutting member having a tapered tip end shape with no top face in the groove width direction changes from a range included in the groove on the front face side to a range away from the groove on the front face side as wear of the cutting member advances, the use of the cutting member is stopped before the variation range changes from the range included in the groove on the front face side to the range away from the groove on the front face side.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: July 5, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Takeshi Minamiru, Michiaki Murata, Kenji Yamazaki, Tsutomu Otsuka
  • Patent number: 9368939
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: June 14, 2016
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Patent number: 9306141
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Hamasaki, Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 9276174
    Abstract: A semiconductor light emitting device which can control of current density and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device are provided.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: March 1, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Masakazu Takao, Kazuhiko Senda
  • Patent number: 9263397
    Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: February 16, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Matthew Gibson, Prem Na-Namchiew, Ekgachai Kenganantanon, Mathew Bunker
  • Patent number: 9236710
    Abstract: A method of manufacturing a semiconductor laser element including: preparing a wafer; forming first grooves on at least one of an upper surface and a lower surface of the wafer, each of the first grooves being spaced apart from the optical waveguide formed in the wafer and extending in a direction intersecting the optical waveguide in a plan view; forming second grooves on the one of the upper surface and the lower surface of the wafer, each of the second grooves extending in a direction intersecting a straight line extended from each of the first grooves, and each of the second grooves having a smooth surface compared with the first grooves; dividing the wafer along the first grooves to obtain a plurality of laser bars; and dividing the laser bars in a direction intersecting an extending direction of the first grooves to obtain the semiconductor laser elements.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 12, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Shingo Tanisaka, Hiroki Koizumi
  • Patent number: 9214608
    Abstract: A luminescence diode arrangement includes a first luminescence diode chip, a second luminescence diode chip and a luminescence conversion element, wherein the first luminescence diode chip emits blue light, the second luminescence diode chip contains a semiconductor layer sequence that emits greens light, the luminescence conversion element converts part of the blue light emitted by the first luminescence diode chip into red light, and the luminescence diode arrangement emits mixed light containing blue light of the first luminescence diode chip, green light of the second luminescence diode chip and red light of the luminescence conversion element.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: December 15, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Thorsten Kunz, Stephan Kaiser
  • Patent number: 9209351
    Abstract: A method for manufacturing a light emitting element includes: preparing a wafer that has a substrate in which a first main face is provided with a plurality of convex components; and dividing the wafer along first dividing lines and second dividing lines. The convex components are in the form of circular cones or truncated circular cones, each of which having a circular bottom face and a side face that is connected to the bottom face, and disposed regularly so that a plurality of bounded regions are present around the convex components, and a shortest distance between the convex components and the centers of the bounded regions is less than a radius of the bottom faces of the convex components. The first and second dividing lines extend in a direction that intersects straight lines that link the centers of the plurality of bounded regions around a single convex component.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 8, 2015
    Assignee: NICHIA CORPORATION
    Inventor: Hiroaki Tamemoto
  • Patent number: 9185791
    Abstract: The present invention relates to a manufacturing method of a printing circuit board. The manufacturing method mainly includes: forming one or more cylindrical micro-radiators by cutting a high conductive and electrical insulating substrate according to predetermined size; manufacturing one or more mounting holes in copper clad plates and prepregs; embedding the cylindrical micro-radiators into the mounting holes. The present invention combines the micro-radiator with high thermal conductivity and traditional stiffness printing circuit board. The printing circuit board with micro-radiators has the advantages of high thermal conductivity and stable heat transfer, and also has the advantages of routing flexibility and reliable electrical connections.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: November 10, 2015
    Assignee: RAYBEN TECHNOLOGIES (ZHUHAI) LIMITED
    Inventor: Zheng Wang
  • Patent number: 9171760
    Abstract: A method of manufacturing a semiconductor device includes: forming electrodes on a first major surface of a semiconductor substrate having first and second major surfaces facing in opposite directions; and forming a cleavage-inducing pattern on the first major surface of the semiconductor substrate. The cleavage-inducing pattern extends over a target cleavage position located between the electrodes, has a recess extending over the target cleavage position, and is made of a material different from the material of the semiconductor substrate. The method includes forming a scribed groove in the second major surface of the semiconductor substrate and in a position facing the target cleavage position; and cleaving the semiconductor substrate having the scribed groove and the cleavage-inducing pattern by applying pressure, through a cleaving blade, to the first major surface of the semiconductor substrate.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 27, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chikara Watatani, Masato Negishi
  • Patent number: 9142734
    Abstract: An emitter includes a light source and a separately formed conversion material region with conversion particles. The light source is capable of emitting light along a plurality of light paths extending through the conversion material region where at least some of the light can be absorbed by the conversion particles. The light from the light source and the light re-emitted from the conversion particles combine to provide a desired color of light. Each light path extends through a substantially similar amount of conversion particles so that the desired color of light has a substantially uniform color and intensity along each light path.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: September 22, 2015
    Assignee: Cree, Inc.
    Inventors: James Ibbetson, Eric Tarsa
  • Patent number: 9136255
    Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: September 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-Kyoung Seo, Eun-Jin Choi
  • Patent number: 9076923
    Abstract: A method for manufacturing a light-emitting device comprising the steps of: providing a first substrate, a chip area, and a street area; forming a light-emitting structure on the first substrate; forming a conductive structure between the first substrate and the light-emitting structure; removing a part of the light-emitting structure in the street area to expose a sidewall of the light-emitting structure in the chip area; forming a first passivation layer on the light-emitting structure in the chip area; forming a second passivation layer on the conductive structure in the street area, on the sidewalls of the light-emitting structure, and on the sidewalls of the first passivation layer; forming a through-hole in the first passivation layer, and forming an electrode in the through-hole.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 7, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Hsien Li, Chi-Hao Huang, Hsin-Hsiung Huang
  • Publication number: 20150144971
    Abstract: Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.
    Type: Application
    Filed: June 4, 2013
    Publication date: May 28, 2015
    Inventors: Jipu Lei, Stefano Schiaffino, ALexander H. Nickel, Mooi Guan Ng, Grigoriy Basin, Salman Akram
  • Publication number: 20150144968
    Abstract: A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Scott Brad Herner, Linda Romano, Daniel Bryce Thompson, Martin Schubert
  • Patent number: 9040389
    Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
  • Publication number: 20150140711
    Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.
    Type: Application
    Filed: May 8, 2013
    Publication date: May 21, 2015
    Inventors: Jipu Lei, Alexander H. Nickel, Stefano Schiaffino, Grigoriy Basin
  • Publication number: 20150140710
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Application
    Filed: December 3, 2014
    Publication date: May 21, 2015
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Patent number: 9036671
    Abstract: A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade 5g is forced down through a first region ER1 to keep the first region ER1 squeezed between a support member H2 and a movable member H1 together with a part of a protective sheet TF in contact with the first region ER1 while the tension generated in the area of the protective sheet TF in contact with the first region ER1 with the movable member H1 increases until the semi-polar principal surface SF at an end face EG1 of the first region ER1 tilts by a deflection angle THETA from the semi-polar principal surface SF of a second region ER2, and a force is thereby generated in the first region ER1 in a direction opposite to the direction of travel of the blade 5g toward the first region ER1.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 19, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shimpei Takagi
  • Patent number: 9034733
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Publication number: 20150129915
    Abstract: A method for manufacturing a light-emitting diode is provided. First, a substrate having a front or top surface and a rear or bottom surface is provided. An uneven pattern is formed on the rear or bottom surface. A light-emitting semiconductor layer is formed by stacking a first semiconductor layer, an active layer, and a second semiconductor layer on the front or top surface of the substrate having the uneven pattern. The light-emitting semiconductor layer and the substrate are separated into a plurality of light-emitting cells.
    Type: Application
    Filed: April 15, 2013
    Publication date: May 14, 2015
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: ChungHoon Lee, DaeSung Cho, KiBum Nam
  • Patent number: 9029902
    Abstract: A semiconductor device includes a radiation-emitting semiconductor chip, a carrier substrate and a film. The carrier substrate has electrically conductive contact tracks on a top side. The film is arranged on a radiation exit side of the chip, the radiation exit side being remote from the carrier substrate, and on the top side of the carrier substrate and has electrically conductive first conductor tracks. The film has perforations arranged such that the semiconductor chip can be electrically contact-connected to the first contact track of the carrier substrate via the first conductor track of the film.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: May 12, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Magnus Ahlstedt, Johann Ramchen
  • Publication number: 20150118775
    Abstract: A method of manufacturing a nitride semiconductor element includes preparing a wafer having a nitride semiconductor layer which includes p-type dopants, forming an altered portion by condensing laser beam on the wafer, and after the forming an altered portion, forming a p-type nitride semiconductor layer by subjecting the wafer to annealing.
    Type: Application
    Filed: October 29, 2014
    Publication date: April 30, 2015
    Applicant: NICHIA CORPORATION
    Inventors: Junya NARITA, Yohei WAKAI, Kazuto OKAMOTO, Mizuki NISHIOKA
  • Publication number: 20150102304
    Abstract: A method of cutting an organic light-emitting display panel substrate into OLED display panels is disclosed. In one aspect, the method includes forming a plurality of OLEDs over a lower mother substrate, wherein the OLEDs are divided into a plurality of groups. The method also includes forming a plurality of sealant lines over at least one of an upper mother substrate or the lower mother substrate such that each sealant line surrounds a corresponding group of the OLEDs. The method further includes forming a plurality of assistance sealant lines between adjacent sealant lines, attaching the upper mother substrate to the lower mother substrate with the sealant lines and the assistance sealant lines interposed therebetween, and cutting the upper mother substrate and the lower mother substrate along the assistance sealant lines.
    Type: Application
    Filed: July 9, 2014
    Publication date: April 16, 2015
    Inventor: Jae Kyung GO