Substrate Dicing Patents (Class 438/33)
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Patent number: 9034733Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: GrantFiled: January 21, 2014Date of Patent: May 19, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 9036671Abstract: A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade 5g is forced down through a first region ER1 to keep the first region ER1 squeezed between a support member H2 and a movable member H1 together with a part of a protective sheet TF in contact with the first region ER1 while the tension generated in the area of the protective sheet TF in contact with the first region ER1 with the movable member H1 increases until the semi-polar principal surface SF at an end face EG1 of the first region ER1 tilts by a deflection angle THETA from the semi-polar principal surface SF of a second region ER2, and a force is thereby generated in the first region ER1 in a direction opposite to the direction of travel of the blade 5g toward the first region ER1.Type: GrantFiled: August 6, 2012Date of Patent: May 19, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventor: Shimpei Takagi
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Publication number: 20150129915Abstract: A method for manufacturing a light-emitting diode is provided. First, a substrate having a front or top surface and a rear or bottom surface is provided. An uneven pattern is formed on the rear or bottom surface. A light-emitting semiconductor layer is formed by stacking a first semiconductor layer, an active layer, and a second semiconductor layer on the front or top surface of the substrate having the uneven pattern. The light-emitting semiconductor layer and the substrate are separated into a plurality of light-emitting cells.Type: ApplicationFiled: April 15, 2013Publication date: May 14, 2015Applicant: Seoul Viosys Co., Ltd.Inventors: ChungHoon Lee, DaeSung Cho, KiBum Nam
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Patent number: 9029902Abstract: A semiconductor device includes a radiation-emitting semiconductor chip, a carrier substrate and a film. The carrier substrate has electrically conductive contact tracks on a top side. The film is arranged on a radiation exit side of the chip, the radiation exit side being remote from the carrier substrate, and on the top side of the carrier substrate and has electrically conductive first conductor tracks. The film has perforations arranged such that the semiconductor chip can be electrically contact-connected to the first contact track of the carrier substrate via the first conductor track of the film.Type: GrantFiled: September 27, 2011Date of Patent: May 12, 2015Assignee: OSRAM Opto Semiconductors GmbHInventors: Magnus Ahlstedt, Johann Ramchen
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Publication number: 20150118775Abstract: A method of manufacturing a nitride semiconductor element includes preparing a wafer having a nitride semiconductor layer which includes p-type dopants, forming an altered portion by condensing laser beam on the wafer, and after the forming an altered portion, forming a p-type nitride semiconductor layer by subjecting the wafer to annealing.Type: ApplicationFiled: October 29, 2014Publication date: April 30, 2015Applicant: NICHIA CORPORATIONInventors: Junya NARITA, Yohei WAKAI, Kazuto OKAMOTO, Mizuki NISHIOKA
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Publication number: 20150102304Abstract: A method of cutting an organic light-emitting display panel substrate into OLED display panels is disclosed. In one aspect, the method includes forming a plurality of OLEDs over a lower mother substrate, wherein the OLEDs are divided into a plurality of groups. The method also includes forming a plurality of sealant lines over at least one of an upper mother substrate or the lower mother substrate such that each sealant line surrounds a corresponding group of the OLEDs. The method further includes forming a plurality of assistance sealant lines between adjacent sealant lines, attaching the upper mother substrate to the lower mother substrate with the sealant lines and the assistance sealant lines interposed therebetween, and cutting the upper mother substrate and the lower mother substrate along the assistance sealant lines.Type: ApplicationFiled: July 9, 2014Publication date: April 16, 2015Inventor: Jae Kyung GO
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Patent number: 9006865Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.Type: GrantFiled: June 24, 2011Date of Patent: April 14, 2015Assignee: Dowa Electronics Materials Co., Ltd.Inventors: Tetsuya Ikuta, Daisuke Hino, Tomohiko Shibata
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Patent number: 8999816Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.Type: GrantFiled: April 18, 2014Date of Patent: April 7, 2015Assignee: Applied Materials, Inc.Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
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Patent number: 9000434Abstract: A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.Type: GrantFiled: December 10, 2012Date of Patent: April 7, 2015Assignee: Emcore CorporationInventors: Richard Carson, Elaine Taylor, Douglas Collins
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Patent number: 8999737Abstract: Methods of packaging a light emitting diode (LED) include providing a first lead having a first recess in a bottom surface and a second lead having a second recess in a bottom surface, placing a LED die over a top surface of at least one of the first and the second leads, electrically connecting the LED die to the first lead and to the second lead, forming a package around the LED die that includes an opening in its upper surface exposing at least the LED die, and separating the package containing the LED die, the first lead and the second lead from a lead frame such that the package contains a first castellation and a second castellation in a side surface of the package, such that the castellations expose the leads and/or a first platable metal which is electrically connected to the leads.Type: GrantFiled: September 19, 2013Date of Patent: April 7, 2015Assignee: Glo ABInventors: Douglas Harvey, Ronald Kaneshiro
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Publication number: 20150093844Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. A wafer is provided. The wafer has a sapphire substrate and a semiconductor layer formed on the sapphire substrate. The semiconductor layer contains a plurality of un-separated LED dies. A photo-sensitive layer is formed over the semiconductor layer. A photolithography process is performed to pattern the photo-sensitive layer into a plurality of patterned portions. The patterned portions are separated by a plurality of openings that are each substantially aligned with one of the LED dies. A metal material is formed in each of the openings. The wafer is radiated in a localized manner such that only portions of the wafer that are substantially aligned with the openings are radiated. The sapphire substrate is removed along with un-radiated portions of the semiconductor layer, thereby separating the plurality of LED dies into individual LED dies.Type: ApplicationFiled: December 11, 2014Publication date: April 2, 2015Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
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Patent number: 8989530Abstract: An array of optical devices includes singlets diced or separated from a first diced surface and a second diced surface of a semiconductor wafer. Each singlet includes a single optical emitter or a single photosensitive semiconductor device. The singlets are identified as operationally fit before being arranged in corresponding features in a receiving region of a submount. The corresponding features of the submount are arranged to align and precisely control the pitch or separation distance between optical portions of a desired number of singlets. The use of operationally fit singlets dramatically increases production efficiency as it is no longer necessary to identify N contiguous operational optical devices in a semiconductor wafer to produce a precisely aligned array of N operational optical devices.Type: GrantFiled: July 22, 2010Date of Patent: March 24, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Seng-Kum Chan
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Patent number: 8987020Abstract: A method for manufacturing a semiconductor light-emitting device includes forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer. The method includes forming a groove through the first semiconductor layer. The method includes forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove.Type: GrantFiled: September 12, 2012Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akihiro Kojima, Yoshiaki Sugizaki
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Patent number: 8987024Abstract: System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.Type: GrantFiled: June 6, 2013Date of Patent: March 24, 2015Assignee: Bridgelux, IncInventor: Tao Xu
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Publication number: 20150076476Abstract: A method of manufacturing an organic electroluminescent display device includes the steps of: forming a first insulating layer on a substrate; forming a first patterning layer; forming a second patterning layer; forming a trench portion; and forming an electrode layer on the second patterning layer and in the trench portion, wherein in the step of forming the trench portion, an end of the first patterning layer exposed within the trench portion is etched to an outside more than an end of the second patterning layer exposed within the trench portion in a plan view, and in the step of forming the electrode layer, the electrode layer formed within the trench portion is isolated from the electrode layer formed outside of the trench portion.Type: ApplicationFiled: September 18, 2014Publication date: March 19, 2015Inventors: Kazuhiro ODAKA, Toshihiro SATO, Naoki TOKUDA
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Patent number: 8976829Abstract: An edge-emitting semiconductor laser is specified. A semiconductor body includes an active zone suitable for producing electromagnetic radiation. At least two facets on the active zone form a resonator. At least two contact points are spaced apart from one another in a lateral direction by at least one intermediate region and are mounted on an outer face of the semiconductor body.Type: GrantFiled: May 9, 2011Date of Patent: March 10, 2015Assignee: Osram Opto Semiconductors GmbHInventors: Harald Koenig, Uwe Strauss, Wolfgang Reill
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Patent number: 8975096Abstract: A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cMUT) when flip chip bonding is performed, and a separation groove formed in a bottom surface of the accommodation groove, the separation groove having a bottom surface that is spaced apart from thin films of the cMUT that face the bottom surface of the separation groove when the cMUT is seated on portions of the bottom surface of the accommodation groove.Type: GrantFiled: June 25, 2013Date of Patent: March 10, 2015Assignees: Samsung Electronics Co., Ltd., Kyungpook National University Industry-Academic Cooperation FoundationInventors: Young Il Kim, Bae Hyung Kim, Jong Keun Song, Seung Heun Lee, Kyung Il Cho, Yong Rae Roh, Won Seok Lee
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Publication number: 20150064823Abstract: A method for manufacturing a light emitting element that includes preparing a wafer having a substrate and a semiconductor structure, the substrate including a plurality of protrusions at positions corresponding to lattice points on a triangular lattice. The method includes forming a plurality of first modified parts in the substrate by irradiating the substrate with a laser beam along first dividing lines, forming a plurality of second modified parts in the substrate by irradiating the substrate with a laser beam along second dividing lines, and dividing the wafer along the first modified parts and the second modified parts to obtain a plurality of light emitting elements.Type: ApplicationFiled: August 22, 2014Publication date: March 5, 2015Inventors: Hiroaki TAMEMOTO, Chihiro JUASA
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Publication number: 20150064824Abstract: An optical device including a substrate formed of a light transmitting material and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Each side surface of the substrate has a corrugated sectional shape such that a plurality of concave portions and convex portions are alternately formed.Type: ApplicationFiled: August 28, 2014Publication date: March 5, 2015Inventor: Kota Fukaya
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Publication number: 20150060888Abstract: A method for fabricating an epitaxial structure includes providing a wafer comprising one or more epitaxial layers. The wafer is divided into dice where the area between the dice are called streets. Each street has a slot formed on either side of the street. The slots penetrate through the epitaxial layer but not the substrate leaving a portion of the epitaxial layer intact between the slots creating a “W” shaped cross section. A protective layer is then formed on the wafer. A laser may be used to singulate the wafer in to individual dice. The laser divides each street between the slots. The barrier walls of the epitaxial layers protect the individual dice from debris created by laser separation.Type: ApplicationFiled: April 5, 2013Publication date: March 5, 2015Inventors: Songnan Wu, Boris Kharas
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Patent number: 8969175Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.Type: GrantFiled: August 23, 2013Date of Patent: March 3, 2015Assignee: OSRAM Opto Semiconductors GmbHInventors: Andreas Ploessl, Heribert Zull
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Publication number: 20150054017Abstract: An LED chip package having a topographical glass coating on top surface for enhancing heat dissipation is disclosed. A circular wall is optionally built to surround the LED chip for reflecting light beams from the LED chips; the glass coating further extends to cove the inner wall surface of the circular wall. The larger area the glass coating covers, the more heat the package dissipates in a time unit. The LED chip package according to the present invention exhibits higher thermal dissipation and helps to last longer the life of the LED chip package than a traditional one.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Applicant: Prolight Opto Technology CorporationInventors: Chen-Lun HSING CHEN, Chien-Cheng KUO, Jung-Hao HUNG, Cheng-Chung LEE, Ding-Yao LIN, Meng-Chi LI, Ping-Chun TSAI
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Publication number: 20150056730Abstract: The present invention relates to a semiconductor device, a manufacturing method thereof. More specifically, this invention is related to a chemical etching method in semiconductor device separation process without using dicing or scribing. According to an example of the invention, a method for manufacturing a semiconductor device, the method comprising: forming a light emitting semiconductor device layer that emits light by current injection; and forming at least one metal layer with etch barrier plated thereon on the semiconductor device layer, wherein the at least one metal layer provides mechanical support to the semiconductor device, wherein the etch barrier is plated on the at least one metal layer in a direction that the etch barrier can prevent side wall under-cut when the street lines are separated by wet chemical etching.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Inventors: Kyu Sung Hwang, Se Jong Oh, Myung Cheol Yoo, Moo Keun Park, Sang Don Lee
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Patent number: 8962363Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.Type: GrantFiled: June 6, 2014Date of Patent: February 24, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
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Vertically structured group III nitride semiconductor LED chip and method for manufacturing the same
Patent number: 8962362Abstract: A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon (“n” is a positive integer) having rounded corners.Type: GrantFiled: November 5, 2009Date of Patent: February 24, 2015Assignees: Wavesquare Inc., Dowa Electronics Materials Co., Ltd.Inventors: Meoung Whan Cho, Seog Woo Lee, Pil Guk Jang, Ryuichi Toba, Tatsunori Toyota, Yoshitaka Kadowaki -
Publication number: 20150050765Abstract: A photolithographic method which produces a structure in a radiation-emitting semiconductor component by providing a semiconductor wafer having a semiconductor layer sequence, applying a first photoresist layer to the semiconductor wafer, providing a mask, and arranging the mask relative to the coated semiconductor wafer, exposing the first photoresist layer and imaging the mask in the first photoresist layer, arranging the mask or a different mask relative to the semiconductor wafer at another position different from a first position and again exposing the first photoresist layer and imaging the mask in the first photoresist layer or applying a second photoresist layer to the first photoresist layer, arranging the mask or a different mask relative to the semiconductor wafer at a second position, and exposing the second photoresist layer and imaging the mask in the second photoresist layer, forming a patterned photoresist layer and patterning the semiconductor wafer.Type: ApplicationFiled: August 15, 2014Publication date: February 19, 2015Inventors: Bernd Böhm, Sebastian Hoibl
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Patent number: 8956901Abstract: An integral LED component is mounted into a hollow carrier. The carrier has two conductive electrodes with opposite polarities. The LED component comprises a substrate, N number of LED epitaxial structures where N is a number greater than one, a third electrode and a fourth electrode. The N number of LED epitaxial structures are formed on the upper surface of the substrate, the at least one of the N number of LED epitaxial structures comprises a first and a second electrode. The third and fourth electrodes are formed on the upper surface and located outside the N number of LED epitaxial structures, the respective electrodes are electrically connected to form a circuit. The two conductive electrodes of the hollow carrier are used for electrically connecting the third and fourth electrodes of the substrate, and the lower surface of the substrate is exposed to the hollow carrier.Type: GrantFiled: April 29, 2014Date of Patent: February 17, 2015Inventor: Jen-Shyan Chen
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Patent number: 8956887Abstract: The invention is directed to the provision of a method for manufacturing a semiconductor light-emitting element that eliminates the need for preparing a plurality of different fluorescent sheets. The method for manufacturing the semiconductor light-emitting element containing an LED die includes the steps of arranging the LED die on a fluorescent sheet containing a fluorescent substance and adjusting the amount by which the LED die is depressed into the fluorescent sheet so that the semiconductor light-emitting element has a desired color emission.Type: GrantFiled: June 28, 2012Date of Patent: February 17, 2015Assignees: Citizen Holdings Co., Ltd., Citizen Electrinocs Co., Ltd.Inventor: Kazuaki Sorimachi
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Publication number: 20150044799Abstract: In an optical device wafer processing method, a light emitting layer on the front side of a wafer is removed by applying a pulsed laser beam to the wafer along division lines from the back side of a substrate with the focal point of the beam set near the light emitting layer, thereby partially removing the light emitting layer along the division lines. A shield tunnel is formed by applying the beam to the wafer along the division lines from the back of the substrate with the focal point of the beam set near the front of the substrate. This forms a plurality of shield tunnels arranged along each division line, each shield tunnel extending from the front side of the substrate to the back side thereof. Each shield tunnel has a fine hole and an amorphous region formed around the fine hole for shielding the fine hole.Type: ApplicationFiled: August 6, 2014Publication date: February 12, 2015Inventors: Noboru Takeda, Hiroshi Morikazu
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Publication number: 20150044798Abstract: A method for producing an optoelectronic component is provided. A transfer layer, containing InxGa1-xN with 0<x<1, is grown onto a growth substrate. Subsequently, ions are implanted into the transfer layer to form a separation zone, a carrier substrate is applied, and the transfer layer is separated by way of heat treatment. A further transfer layer, containing InyGa1-yN with 0<y?1 and y>x, is grown onto the previously grown transfer layer, ions are implanted into the further transfer layer to form a separation zone, a further carrier substrate is applied, and the further transfer layer is separated by way of heat treatment. Subsequently, a semiconductor layer sequence, containing an active layer, is grown onto the surface of the further transfer layer facing away from the further carrier substrate.Type: ApplicationFiled: September 12, 2012Publication date: February 12, 2015Applicant: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Ann-Kathrin Haerle, Jakob Johannes Haerle, Johanna Magdalena Haerle
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Patent number: 8951819Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a split-beam laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.Type: GrantFiled: July 11, 2011Date of Patent: February 10, 2015Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, Aparna Iyer
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Patent number: 8946745Abstract: The present invention is related to a supporting substrate for manufacturing vertically-structured semiconductor light emitting device and a vertically-structured semiconductor light emitting device using the same, which minimize damage and breaking of a multi-layered light-emitting structure thin film separated from a sapphire substrate during the manufacturing process, thereby improving the whole performance of the semiconductor light emitting device.Type: GrantFiled: July 15, 2009Date of Patent: February 3, 2015Assignee: LG Innotek Co., Ltd.Inventor: Tae Yeon Seong
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Patent number: 8946726Abstract: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.Type: GrantFiled: March 20, 2013Date of Patent: February 3, 2015Assignee: Cree, Inc.Inventors: Christopher Harris, Andrei Konstantinov, Jan-Olov Svederg
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Patent number: 8946056Abstract: In a splitting method for an optical device wafer, the wafer having optical devices formed individually in regions partitioned by a plurality of crossing scheduled splitting lines provided on a front surface and having a reflective film formed on a reverse surface, a focal point of a laser beam is positioned to the inside of the optical device wafer and the laser beam is irradiated along the scheduled splitting lines from the reverse surface side of the wafer to form modification layers in the inside of the wafer. An external force is applied to the wafer to split the wafer along the scheduled splitting lines and form a plurality of optical device chips. The laser beam has a wavelength that produces transmittance through the reflective film equal to or higher than 80%.Type: GrantFiled: May 7, 2012Date of Patent: February 3, 2015Assignee: Disco CorporationInventors: Hiroumi Ueno, Hitoshi Hoshino
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Patent number: 8945960Abstract: An optical device wafer has a plurality of optical devices formed on a front side and a plurality of crossing division lines for partitioning the optical devices. Each optical device has electrodes formed on the front side. A processing method includes: forming a groove on the front side of the wafer along each division line, the groove having a depth reaching a finished thickness; of forming a nonconductive reflective film on the front side of the wafer to thereby form the reflective film on at least the side surfaces of the groove; removing the reflective film formed on the electrodes to thereby expose the electrodes; and grinding a back side of the wafer to thereby reduce the thickness to the finished thickness until the groove is exposed to the back side of the wafer to divide the wafer into individual optical device chips.Type: GrantFiled: June 4, 2013Date of Patent: February 3, 2015Assignee: Disco CorporationInventor: Kazuma Sekiya
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Patent number: 8945963Abstract: An optical device processing method including: a groove forming step of forming a plurality of grooves on a front side of a sapphire substrate; a film forming step of forming an epitaxial film on the front side of the sapphire substrate after performing the groove forming step, thereby forming a plurality of optical devices and a plurality of crossing division lines for partitioning the optical devices; and a dividing step of dividing the sapphire substrate with the epitaxial film along the division lines after performing the film forming step, thereby obtaining a plurality of individual optical device chips.Type: GrantFiled: June 4, 2013Date of Patent: February 3, 2015Assignee: Disco CorporationInventor: Kazuma Sekiya
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Patent number: 8940621Abstract: Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate.Type: GrantFiled: June 25, 2012Date of Patent: January 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Uk Han, Jeong-Kyu Ha, Youngshin Kwon, Seung Hwan Kim, KwanJai Lee
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Patent number: 8936952Abstract: An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer.Type: GrantFiled: June 8, 2011Date of Patent: January 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akihiro Chida
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Patent number: 8936953Abstract: Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. In one embodiment, a cavity is formed on a substrate to contain an LED and phosphor layer. The substrate has a channel separating the substrate into a first portion containing the cavity and a second portion. A filler of encapsulant material or other electrically insulating material is molded in the channel. The first portion can serve as a cathode for the LED and the second portion can serve as the anode.Type: GrantFiled: December 3, 2013Date of Patent: January 20, 2015Assignee: Micron Technology, Inc.Inventor: Jonathon G. Greenwood
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Patent number: 8936957Abstract: The present disclosure discloses a method of manufacturing a light-emitting device comprising the steps of providing a light-emitting wafer having a semiconductor stacked structure and an alignment mark, sensing the alignment mark, and separating the light-emitting wafer into a plurality of light-emitting diodes and removing the alignment mark accordingly.Type: GrantFiled: December 24, 2013Date of Patent: January 20, 2015Assignee: Epistar CorporationInventor: Tsung-Hsien Yang
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Patent number: 8932890Abstract: The present invention relates to a vertical-structure semiconductor light emitting device and a production method thereof, more specifically, to a vertical-structure semiconductor light emitting device having a high-performance heat sink support comprising a thick metal film or metal foil. The vertical-structure semiconductor light emitting element produced in accordance with the present invention constitutes a highly reliable light emitting element with absolutely no thermal or mechanical damage since it has the high performance heatsink support and so suffers not fine micro-cracking and can be freely subjected to heat treatment and to post-processing including of a side-surface passivation thin film.Type: GrantFiled: November 23, 2010Date of Patent: January 13, 2015Assignee: LG Innotek Co., Ltd.Inventor: Tae Yeon Seong
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Patent number: 8932888Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.Type: GrantFiled: September 6, 2011Date of Patent: January 13, 2015Assignee: OSRAM Opto Semiconductors GmbHInventor: Ralph Wagner
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Patent number: 8918971Abstract: A method of manufacturing packages having contents sealed therein, including: a step of forming cavities in a plurality of package forming areas on a first wafer; a step of bonding the first wafer and a second wafer while arranging the contents in the cavities; and a step of irradiating a bonded wafer member with a laser and separating the packages into pieces, characterized in that dummy cavities are formed on an outside of the package forming area in an outermost periphery of the first wafer in the cavity forming step.Type: GrantFiled: July 7, 2011Date of Patent: December 30, 2014Assignee: SII Crystal Technology Inc.Inventor: Junya Fukuda
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Patent number: 8916888Abstract: The present invention discloses an integral LED component which integrates LED epitaxial structures electrodes and interconnect with a package substrate together and an integral manufacturing process thereof. The integral LED component can be made with multiple epitaxial structures or with just a single epitaxial structure. The integral LED component can be mounted into a hollow carrier. And by having support by the hollow carrier, the package substrate can be mounted and contacted with a heat conductive or a dissipation device. The integral LED component is fabricated by wafer level process and cut from the wafer as an independent component. By different manufacturing process, the integral LED component can be made as Vertical LED structure or Lateral LED structure.Type: GrantFiled: April 26, 2013Date of Patent: December 23, 2014Assignee: Neobulb Technologies, Inc.Inventor: Jen-Shyan Chen
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Patent number: 8916403Abstract: A method for producing a plurality of optoelectronic semiconductor chips includes providing a carrier wafer having a first surface and a second surface opposite the first surface, wherein a plurality of individual component layer sequences spaced apart from one another in a lateral direction are applied on the first surface, the component layer sequences being separated from one another by separation trenches; introducing at least one crystal imperfection in at least one region of the carrier wafer which at least partly overlaps a separation trench in a vertical direction; singulating the carrier wafer along the at least one crystal imperfection into individual semiconductor chips.Type: GrantFiled: February 3, 2011Date of Patent: December 23, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Ewald K. M. Günther, Mathias Kämpf, Jens Dennemarck, Nikolaus Gmeinwieser
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Patent number: 8916402Abstract: The present invention provides a compound semiconductor light emitting device including: an Si—Al substrate; protection layers formed on top and bottom surfaces of the Si—Al substrate; and a p-type semiconductor layer, an active layer, and an n-type semiconductor layer which are sequentially stacked on the protection layer formed on the top surface of the Si—Al substrate, and a method for manufacturing the same.Type: GrantFiled: April 30, 2012Date of Patent: December 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myong Soo Cho, Ki Yeol Park, Pun Jae Choi
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Patent number: 8912033Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a substrate having opposite first and second sides. A semiconductor layer is formed on the first side of the substrate. The method includes forming a photoresist layer over the semiconductor layer. The method includes patterning the photoresist layer into a plurality of photoresist components. The photoresist components are separated by openings. The method includes filling the openings with a plurality of thermally conductive components. The method includes separating the semiconductor layer into a plurality of dies using a radiation process that is performed to the substrate from the second side. Each of the first regions of the substrate is aligned with one of the conductive components.Type: GrantFiled: October 8, 2010Date of Patent: December 16, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
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Patent number: 8912024Abstract: Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching.Type: GrantFiled: November 18, 2011Date of Patent: December 16, 2014Assignee: Invensas CorporationInventors: Ilyas Mohammed, Masud Beroz, Liang Wang
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Patent number: 8912565Abstract: A light emitting device is provided, including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer, and a plurality of electrodes. The first semiconductor layer has a step-down region such that one of the plurality of electrodes is placed on the first semiconductor layer. The light emitting device includes a substrate including a first portion having a flat top surface, a second portion having a flat bottom surface and disposed under the first portion, and a side portion disposed between the first portion and the second portion. An area of the flat top surface of the first portion is larger than an area of the flat bottom surface of the second portion.Type: GrantFiled: January 28, 2014Date of Patent: December 16, 2014Assignee: LG Innotek, Co., Ltd.Inventor: Sang Youl Lee
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Patent number: 8912049Abstract: Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal portion bonded to the first electrode of each LED for providing an energization current to each LED. The submount wafer also has a second metal portion running along and proximate to the first metal portion but not electrically connected to the first metal portion. The second metal portion may be interdigitated with the first metal portion. The second metal portion is connected to a bias voltage. When the wafer is immersed in an electrically conductive solution for electrochemical (EC) etching of the exposed first semiconductor layer, the solution electrically connects the second metal portion to the first metal portion for biasing the first semiconductor layer during the EC etching.Type: GrantFiled: October 10, 2011Date of Patent: December 16, 2014Assignee: Koninklijke Philips N.V.Inventor: Yajun Wei