Making Emissive Array Patents (Class 438/34)
  • Patent number: 10424607
    Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 24, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Patent number: 10411065
    Abstract: A light-emitting device includes a substrate and a first light-emitting unit. The first light-emitting unit is disposed on the substrate, and includes a first semiconductor layer, a first light-emitting layer, and a second semiconductor layer. The first semiconductor layer is disposed on the substrate. The first light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is disposed on the first light-emitting layer. The first semiconductor layer has a first sidewall and a second sidewall. A first angle is between the substrate and the first sidewall. A second angle is between the substrate and the second sidewall. The first angle is smaller than the second angle.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 10, 2019
    Assignee: GENESIS PHOTONICS INC.
    Inventors: Tsung-Syun Huang, Chih-Chung Kuo, Jing-En Huang, Shao-Ying Ting
  • Patent number: 10403756
    Abstract: Embodiments of the present invention relate to a thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device. The TFT includes an active layer, an amorphous silicon (a-Si) connecting layer and a source-drain electrode layer. The active layer includes a channel region, a source region and a drain region; forming materials of the channel region include polycrystalline silicon (poly-Si); the a-Si connecting layer is disposed on a side of the active layer and includes a first connecting part and a second connecting part which are spaced from each other; the source-drain electrode layer includes a source electrode and a drain electrode which are spaced to each other; the source electrode is electrically connected with the source region through the first connecting part; and the drain electrode is electrically connected with the drain electrode through the second connecting part.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 3, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jinchao Bai, Huibin Guo, Young Tae Hong
  • Patent number: 10388873
    Abstract: An evaporation mask is disclosed. The evaporation mask includes a mask frame, a set of first mask strips arranged on the mask frame along a first direction, and a set of second mask strips arranged on the set of first mask strips along a second direction different from the first direction. Each of the second mask strips has sections overlapping the first mask strips. The sections are embedded in respective ones of the first mask strips. Also disclosed is a method of patterning a substrate using the evaporation mask, as well as an organic light-emitting diode display substrate manufactured using the method.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: August 20, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shenchun Chang
  • Patent number: 10367142
    Abstract: A layered structure suitable as a support for an organic light emitting device (OLED), includes a light-transmissive glass substrate, a diffusive internal extraction layer (IEL) with an outer layer made of a glass containing at least 30 weight % of Bi2O3, formed on one side of the light-transmissive glass substrate, and an acid-resistant barrier layer formed on the IEL. The acid-resistant barrier layer has a bilayer structure made of an ALD-deposited metal oxide layer, the metal oxide being selected from the group consisting of aluminum oxide (Al2O3), titanium oxide (TiO2), zirconium oxide (ZrO2) and hafnium oxide (HfO2), in contact with the IEL, and a sputter-deposited SiOxNy layer in contact with the ALD-deposited metal oxide layer.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 30, 2019
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Young Seong Lee, Simon Le Moal, Jinwoo Han
  • Patent number: 10361312
    Abstract: A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Ho Jung, Chaun Gi Choi, Hye Young Park, Eun Young Lee, Joo Hee Jeon, Eun Jeong Cho, Bo Geon Jeon, Yung Bin Chung
  • Patent number: 10186680
    Abstract: An organic light emitting display device includes a pixel electrode, an auxiliary electrode, a pixel defining layer, a spacer, a light emitting layer, and an opposite electrode. The pixel electrode and auxiliary electrode on a same layer and are separated and electrically isolated from each other. The pixel defining layer is on the pixel and auxiliary electrodes and exposes at least portions of the pixel and auxiliary electrodes. The spacer corresponds to portions of the auxiliary electrode and pixel defining layer and exposes at least a portion of the auxiliary electrode. The light emitting layer is on the pixel electrode. The opposite electrode is on the light emitting layer and the spacer and is in contact with the auxiliary electrode.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Wonse Lee
  • Patent number: 10128424
    Abstract: The invention relates in at least one embodiment to the production of optoelectronic semiconductor components and comprises the steps: A) providing an intermediate carrier (2) having a plurality of fixing points (23), B) providing optoelectronic semiconductor chips (3) each having a chip upper side (30) and a mounting side (32) located opposite thereto, wherein electric contact points (34) of the semiconductor chips (3) are each located on the mounting sides (32), C) attaching connecting means (4), D) fixing the contact points (34) to the fixing points (23) by means of the connecting means (4), E) producing a potting layer (5), such that the semiconductor chips (3) and the contact points (34) and the connecting means (4) are directly surrounded all round by the potting layer (5), F) detaching the semiconductor chips (3), such that the connecting means (4) are removed from the semiconductor chips (3) and recesses (44) are each provided at the contact points (34) as a negative form in relation to the connecting
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 13, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Siegfried Herrmann
  • Patent number: 10118318
    Abstract: The invention discloses a temperature regulation mask and an alignment layer pre-curing device, and is related to the field of manufacturing a liquid crystal display panel. Said temperature regulation mask is suitable for the alignment layer pre-curing device for pre-curing an alignment layer, and includes a base and a pattern arranged on the base. A pattern region of said temperature regulation mask has a different thermal conductivity from a thermal conductivity of a non-pattern region of said temperature regulation mask. A position of the one having a lower thermal conductivity among the pattern region and the non-pattern region of said temperature regulation mask corresponds to a position of said alignment layer corresponding to a metallic wiring region. The present invention can obtain an alignment layer with even thickness and improve a display quality.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: November 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Hongming Zhan, Lifeng Lin
  • Patent number: 10083991
    Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Koji Kusunoki
  • Patent number: 10072206
    Abstract: Processes for preparing color stable red-emitting phosphors include contacting a complex fluoride phosphor of formula I with a first fluorine-containing oxidizing agent in gaseous form at a first temperature ranging from 200° C. to 700° C. to form a first product phosphor, contacting the first product phosphor in particulate form with a solution of a compound of formula II in aqueous hydrofluoric acid to form a treated phosphor, and contacting the treated phosphor with a second fluorine-containing oxidizing agent in gaseous form at a second temperature <225° C., AxMFy:MN4+??I AxMFy??II wherein A is independently at each occurrence Li, Na, K, Rb, Cs or a combination thereof, M is independently at each occurrence Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof, x is absolute value of the charge of the MFy ion; and y is 5, 6 or 7.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 11, 2018
    Assignee: General Electric Company
    Inventors: James Edward Murphy, Fangming Du, Anant Achyut Setlur
  • Patent number: 10068953
    Abstract: By controlling the luminance of light emitting element not by means of a voltage to be impressed to the TFT but by means of controlling a current that flows to the TFT in a signal line drive circuit, the current that flows to the light emitting element is held to a desired value without depending on the characteristics of the TFT. Further, a voltage of inverted bias is impressed to the light emitting element every predetermined period. Since a multiplier effect is given by the two configurations described above, it is possible to prevent the luminance from deteriorating due to a deterioration of the organic luminescent layer, and further, it is possible to maintain the current that flows to the light emitting element to a desired value without depending on the characteristics of the TFT.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mai Akiba, Jun Koyama
  • Patent number: 10062791
    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 28, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Patent number: 9989703
    Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Jean Fompeyrine, Jens Hofrichter, Bert Jan Offrein, Mirja Richter
  • Patent number: 9985239
    Abstract: The invention describes an OLED device (1) comprising an organic layer (3) which emits light (L1) in operation and which is positioned between an essentially transparent anode layer (5) and an essentially opaque cathode layer (7). The cathode layer (7) is deliberately structured along a main extension plane (EP) of the OLED device to comprise at least one cathode region (11, 11a, 11b) in which the cathode layer (7) is 10 present and a plurality of cathode-free regions (13, 13a, 13b) and/or at least one cathode-free region (13, 13a, 13b) of a larger extension, through which cathode-free regions and/or region (13, 13a, 13b) visible light (L2) can pass in the direction of a cross extension (CE) of the OLED device. The invention also describes a production method of such OLED device (1).
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 29, 2018
    Assignee: Koninklike Philips N.V.
    Inventors: Manfred Stephan Ruske, Holger Schwab, Herbert Lifka
  • Patent number: 9966556
    Abstract: The present specification relates to an organic light emitting device.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 8, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Yeon Keun Lee
  • Patent number: 9905813
    Abstract: An organic layer depositing apparatus includes a deposition unit which includes one or more deposition assemblies spaced a predetermined distance apart from a substrate to deposit a deposition material on the substrate, wherein the one or more deposition assemblies include: a deposition source; a deposition source nozzle unit; a first pattern sheet which includes a first patterning unit and a first overlap unit; and a second pattern sheet which includes a second patterning unit and a second overlap unit, wherein the first and second pattern sheets are arranged such that the first and second overlap units overlap each other.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaesoo Ha, Minsoo Kim, Mugyeom Kim, Muhyun Kim, Dongkyu Lee, Byungkook Lee, Suhwan Lee, Yonggu Lee, Jaeyoung Cho, Valeriy Prushinskiy
  • Patent number: 9899225
    Abstract: An embodiment of present disclosure provides a method for manufacturing an array substrate, an array substrate manufactured by the method, and a mask. The method for manufacturing the array substrate includes: providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate; forming a first mask pattern on a base substrate by means of the light non-transmission region of the mask; and forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 20, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO. LTD.
    Inventors: Zhichao Zhang, Tsung-Chieh Kuo, Zheng Liu, Xiaoxiang Zhang, Xi Chen, Mingxuan Liu
  • Patent number: 9876099
    Abstract: To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Toshimitsu Obonai, Junichi Koezuka, Suzunosuke Hiraishi
  • Patent number: 9868898
    Abstract: Processes for preparing color stable Mn4+ doped phosphors include contacting a phosphor of formula I with a fluorine-containing oxidizing agent in gaseous form at temperature ?225° C. to form the color stable Mn4+ doped phosphor A x ? MF y ? : ? Mn 4 + I wherein A is independently at each occurrence Li, Na, K, Rb, Cs, or a combination thereof; M is independently at each occurrence Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the MFy ion; and y is 5, 6 or 7. In another aspect, the processes include contacting a phosphor of formula I at an elevated temperature with an oxidizing agent comprising a C1-C4 fluorocarbon, to form the color stable Mn4+ doped phosphor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 16, 2018
    Assignee: General Electric Company
    Inventors: James Edward Murphy, Fangming Du, Anant Achyut Setlur
  • Patent number: 9831374
    Abstract: Techniques and mechanisms for providing efficient direction of light to a photodetector with a tapered waveguide structure. In an embodiment, a taper structure of a semiconductor device comprises a substantially single crystalline silicon. A buried oxide underlies and adjoins the monocrystalline silicon of the taper structure, and a polycrystalline Si is disposed under the buried oxide. During operation of the semiconductor device light is redirected in the taper structure and received via a first side of a Germanium photodetector. In another embodiment, one or more mirror structures positioned on a far side of the Germanium photodetector may provide for a portion of the light to be reflected back to the Germanium photodetector.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 28, 2017
    Assignee: INTEL CORPORATION
    Inventors: Benjamin Vincent, Avi Feshali
  • Patent number: 9793413
    Abstract: The present disclosure provides a method for producing a thin film transistor. The method includes the steps of: forming a protective layer on an active layer of the thin film transistor and patterning the protective layer along with the active layer when the active layer is deposited; depositing a source and drain electrode layer and patterning it by a dry etching to form a source electrode and a drain electrode; and etching or passivating the protective layer located in a back channel region of the source electrode and the drain electrode. In addition, the present disclosure also discloses a thin film transistor produced by the above method, and an array substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: October 17, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Li Zhang, Meili Wang, Fengjuan Liu
  • Patent number: 9741958
    Abstract: An organic light emitting diode display panel is provided. The organic light emitting diode display panel comprises a glass substrate, a conductive layer, an anode, a hole inject layer, a hole transport layer, an organic light-emitting layer, an electron inject layer and a cathode. The present invention further provides an organic light emitting diode display device. The organic light emitting diode display panel and the organic light emitting diode display device can effectively reduce a horizontal resistance of the organic light emitting diode display panel through setting the conductive layer, thereby improving the luminous uniformity of the organic light emitting diode display panel.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: August 22, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Chao Xu
  • Patent number: 9724725
    Abstract: A deposition apparatus for manufacturing a display device is disclosed. In one aspect, the apparatus includes a substrate fixing portion configured to fix a deposition substrate to a lower portion thereof and a first mask transfer portion placed on one side of the substrate fixing portion and configured to move the deposition mask upwardly such that the deposition mask is formed spaced apart from the deposition substrate by a predetermined distance. The apparatus also includes a substrate transfer portion configured to move the deposition substrate such that the deposition substrate passes over the deposition mask. The apparatus further includes a mask spacing portion positioned on the substrate fixing portion and configured to maintain a substantially uniform distance between the deposition substrate and the deposition mask when the deposition substrate is moved and a deposition source configured to deposit a deposition material on the deposition substrate through the deposition mask.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jeong Won Han
  • Patent number: 9673230
    Abstract: A pixel array includes a plurality of scan lines, a plurality of data lines, a first active device, a second active device, a first pixel electrode and a second pixel electrode. The first active device and the second active device are electrically connected to the corresponding scan line and data line respectively. The first pixel electrode is electrically connected to the first active device through a contact hole. The second pixel electrode is electrically connected to the second active device through the contact hole.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: June 6, 2017
    Assignee: Au Optronics Corporation
    Inventors: He-Yi Cheng, Hsin-Chun Huang, Ching-Sheng Cheng
  • Patent number: 9627436
    Abstract: A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 18, 2017
    Assignee: BRIDGELUX, INC.
    Inventors: Mike Kwon, Gerry Keller, Scott West, Tao Tong, Babak Imangholi
  • Patent number: 9601373
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shan Wang, Jian-Hong Lin, Shun-Yi Lee
  • Patent number: 9572969
    Abstract: A device for delivery of material or stimulus to targets within a body to produce a desired response, the targets being at least one of cells of interest, cell organelles of interest and cell nuclei of interest. The device includes a number of projections for penetrating a body surface, with the number of projections being selected to produce a desired response, and the number being at least 500. A spacing between projections is also at least partially determined based on an arrangement of the targets within the body.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: February 21, 2017
    Assignee: The University of Queensland
    Inventor: Mark Anthony Fernance Kendall
  • Patent number: 9577170
    Abstract: A light-emitting device is disclosed. The light-emitting device comprises a supportive substrate; a first light-emitting element and a second light-emitting element on the supportive substrate, wherein the first light-emitting element comprises a transparent layer on the supportive substrate, a first light-emitting stacked layer on the transparent layer, and a plurality of contact parts between the transparent layer and the first light-emitting stacked layer; and the second light-emitting element comprises an electrode and a second light-emitting stacked layer between the electrode and the supportive substrate; and a metal line on the supportive substrate and electrically connecting the electrode and one of the contact parts.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 21, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-I Chen, Chia-Liang Hsu, Tzu-Chieh Hsu, Han-Min Wu, Ye-Ming Hsu, Chien-Fu Huang, Chao-Hsing Chen, Chiu-Lin Yao, Hsin-Mao Liu, Chien-Kai Chung
  • Patent number: 9548247
    Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: January 17, 2017
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Andreas Voerckel
  • Patent number: 9530896
    Abstract: Provided are a reliable high performance thin film transistor and a reliable high performance display device. The display device has: a gate electrode which is formed on a substrate; a gate insulating film which is formed to cover the substrate and the gate electrode; an oxide semiconductor layer which is formed on the gate electrode through the gate insulating film; a channel protective layer which is in contact with the oxide semiconductor layer and formed on the oxide semiconductor layer; and source/drain electrodes which are electrically connected to the oxide semiconductor layer and formed to cover the oxide semiconductor layer. A metal oxide layer is formed on an upper part of the channel protective layer. The source/drain electrodes are formed to be divided apart on the channel protective layer and the metal oxide layer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: December 27, 2016
    Assignee: Japan Display Inc.
    Inventors: Norihiro Uemura, Isao Suzumura, Hidekazu Miyake, Yohei Yamaguchi
  • Patent number: 9520325
    Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: December 13, 2016
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Andreas Voerckel
  • Patent number: 9496524
    Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured using the method. The organic layer deposition apparatus includes a conveyer unit including first and second conveyer units, loading and unloading units, and a deposition unit. A transfer unit moves between the first and second conveyer units, and the substrate attached to the transfer unit is spaced from a plurality of organic layer deposition assemblies of the deposition unit while being transferred by the first conveyer unit. The organic layer deposition assemblies include common layer deposition assemblies and pattern layer deposition assemblies.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: November 15, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su-Hwan Lee, Un-Cheol Sung, Chae-Woong Kim, Young-Mook Choi
  • Patent number: 9391051
    Abstract: A display device using a semiconductor light emitting device and a method of fabricating the semiconductor light emitting device are disclosed. The display device includes a substrate, a plurality of first electrodes disposed on the substrate, an anisotropic conductive film disposed on the substrate provided with the first electrodes, a plurality of semiconductor light emitting devices disposed on the anisotropic conductive film layer, electrically connected to the first electrodes, and constituting individual pixels, and a plurality of second electrodes disposed between the semiconductor light emitting devices and electrically connected to the semiconductor light emitting devices. Thus, alignment of the semiconductor light emitting device array may be simplified by use of an anisotropic conductive film Due to excellent brightness, the semiconductor light emitting devices, which are small in size, may form individual sub-pixels.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: July 12, 2016
    Assignee: LG ELECTRONICS INC.
    Inventor: Byungjoon Rhee
  • Patent number: 9312279
    Abstract: A thin film transistor (TFT) array substrate includes a substrate, a gate electrode, a gate line, a first data line, and a second data line on the substrate, a gate insulating layer that covers the gate electrode and the gate line and includes a first opening that exposes a portion of the first data line and a second opening that exposes a portion of the second data line, an active layer disposed on the gate insulating layer so that at least one portion of the active layer overlaps the gate electrode, a drain electrode and a source electrode that extend from opposite sides of the active layer, a pixel electrode that extends from the drain electrode, and a connection wiring that extends from the source electrode, and connects the first data line to the second data line through the first and second openings of the gate insulating layer.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung-Geun Cha, Yoon-Ho Khang, Hyun-Jae Na, Sang-Ho Park
  • Patent number: 9287531
    Abstract: A method of manufacturing an organic light-emitting display device is provided. A plurality of anodes and an auxiliary electrode are formed on a substrate. The auxiliary electrode is separated from the plurality of the anodes. An organic layer is formed on the plurality of the anodes and the auxiliary electrode. An opening is formed in the organic layer by applying a voltage to the auxiliary electrode. The opening exposes the auxiliary electrode. A cathode is formed on the organic layer and the exposed auxiliary electrode. The cathode is electrically connected to the exposed auxiliary electrode.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Kwan Hee Lee
  • Patent number: 9245948
    Abstract: An optoelectric device including microwires or nanowires on a support, each microwire or nanowire including at least one portion mainly containing a III-V compound in contact with the support, wherein the III-V compound is based on a first group-V element and on a second group-III element, wherein a surface of the support includes first areas of a first material promoting the growth of the III-V compound according to the polarity of the first element distributed in a second area of a second material promoting the growth of the compound according to the polarity of the second element, the microwires or nanowires being located on the first areas.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: January 26, 2016
    Assignees: ALEDIA, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emilie Pougeoise, Amelie Dussaigne
  • Patent number: 9240572
    Abstract: A vapor deposition device includes a vapor deposition source (60) having a plurality of vapor deposition source openings (61) that discharge vapor deposition particles (91), a limiting unit (80) having a plurality of limiting openings (82), and a vapor deposition mask (70) in which a plurality of mask openings (71) are formed only in a plurality of vapor deposition regions (72) where the vapor deposition particles that have passed through a plurality of limiting openings reach. The plurality of vapor deposition regions are arranged along a second direction that is orthogonal to the normal line direction of the substrate (10) and the movement direction of the substrate, with non-vapor deposition regions (73) where the vapor deposition particles do not reach being sandwiched therebetween.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 19, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinichi Kawato, Satoshi Inoue, Tohru Sonoda, Satoshi Hashimoto
  • Patent number: 9231152
    Abstract: The present invention provides a light emitting diode, which comprises a first LED die, a second LED die, and a dummy LED die, wherein the second LED die is disposed between the first LED die and the dummy LED die, and each die comprises a first semi-conductive layer, a second semi-conductive layer, and a multiple quantum well layer disposed between the first and the second semi-conductive layers. The first semi-conductive layer of the first LED die is coupled to the second semi-conductive layer of the second LED die, and the first semi-conductive layer of the second LED die is coupled to the first and second semi-conductive layers of the dummy LED die.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: January 5, 2016
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Trung-Tri Doan, Chao-Chen Cheng, Yi-Feng Shih
  • Patent number: 9190589
    Abstract: The present invention provides a light emitting diode, which comprises a first LED die and a second LED die, each die comprising a first semi-conductive layer, a second semi-conductive layer, and a multiple quantum well layer disposed between the first and the second semi-conductive layers, wherein the first semi-conductive layer of the first LED die is coupled to the second semi-conductive layer of the second LED die so as to form a serially connected structure whereby the consuming current and heat generation of the light emitting diode are lowered so that the size of heat dissipating device for the light emitting diode can be reduced and illumination of the light emitting diode can be enhanced.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 17, 2015
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Trung-Tri Doan, Chao-Chen Cheng, Yi-Feng Shih
  • Patent number: 9178046
    Abstract: Embodiment of the present invention disclose an array substrate and a manufacturing method thereof, and the manufacturing method of an array substrate comprises the following steps: Step S1: a gate electrode metal layer, an insulating layer and an active layer are deposited successively on a substrate, and gate electrodes, gate lines and an active layer pattern are formed through a first mask process; Step S2: a protective layer is deposited on the substrate after completion of the step S1, and via-holes are formed in the protective layer through a second mask process; and Step S3: a pixel electrode layer and a source/drain electrode metal layer are deposited sequentially on the substrate after completion of the step S2, and source/drain electrodes, pixel electrodes and data lines are formed through a third mask process.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 3, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ce Ning
  • Patent number: 9172064
    Abstract: A deposition mask for forming an organic layer pattern of an organic light emitting diode (OLED) display includes a base member having a first surface facing a substrate of the OLED display, and a second surface facing a side opposite to the first surface, and including a plurality of openings passing through the first surface and the second surface for forming the organic layer pattern. The opening has a pair of first side walls and a pair of second side walls. Each side wall of the openings has an inclination surface inclined with respect to a thickness direction of the base member, and when measuring an inclination angle of the inclination surface with reference to the first surface of the base member, the inclination angle of the first side wall and the inclination angle of the second side wall are different from each other.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: October 27, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Min Lee, Choong-Ho Lee
  • Patent number: 9166106
    Abstract: A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: October 20, 2015
    Assignee: GLO AB
    Inventors: Carl Patrik Theodor Svensson, Nathan Gardner
  • Patent number: 9166111
    Abstract: In a light-emitting element 1, a light-emitting layer 4, a second conductivity type semiconductor layer 5, a transparent electrode layer 6, a reflecting electrode layer 7 and an insulating layer 8 are stacked in this order on a first conductivity type semiconductor layer 3, while a first electrode layer 10 and a second electrode layer 12 are stacked on the insulating layer 8 in an isolated state.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: October 20, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Nobuaki Matsui, Hirotaka Obuchi
  • Patent number: 9147700
    Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: September 29, 2015
    Assignee: AU Optronics Corp.
    Inventors: Yi-Chen Chung, Chia-Yu Chen, Hui-Ling Ku, Yu-Hung Chen, Chi-Wei Chou, Fan-Wei Chang, Hsueh-Hsing Lu, Hung-Che Ting
  • Patent number: 9136137
    Abstract: An etchant composition including 0.5 wt % to 20 wt % of a persulfate, 0.01 wt % to 1 wt % of a fluorine compound, 1 wt % to 10 wt % of an inorganic acid, 0.01 wt % to 2 wt % of an azole-based compound, 0.1 wt % to 5 wt % of a chlorine compound, 0.05 wt % to 3 wt % of a copper salt, 0.01 wt % to 5 wt % of an antioxidant or a salt thereof, based on a total weight of the etchant composition, and water in an amount sufficient for the total weight of the etchant composition to be equal to 100 wt % is disclosed. The etchant composition is suitable for use in forming a metal wiring by etching a metal layer including copper or in fabricating a thin film transistor substrate for a display apparatus.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 15, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: In-Bae Kim, Jong-Hyun Choung, Youngmin Moon, Hongsick Park, Gyu-po Kim, Won-guk Seo, Hyun-cheol Shin, Ki-beom Lee, Sam-young Cho, Seung-yeon Han
  • Patent number: 9117959
    Abstract: A light emitting diode structure is provided. The light emitting diode structure includes a substrate, a light emitting multi-layer structure, a first current blocking layer, a first current spreading layer, a second current blocking layer and a second current spreading layer. The light emitting multi-layer structure is formed on the substrate by way of stacking. The first current blocking layer is formed on part of the light emitting multi-layer structure. The first current spreading layer covers the first current blocking layer and the light emitting multi-layer structure. The second current blocking layer is formed on part of the first current spreading layer. An orthogonal projection of the second current blocking layer is disposed in an orthogonal projection of the first current blocking layer. The second current spreading layer covers the second current blocking layer and the first current spreading layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 25, 2015
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Bo-Yu Chen, Po-Hung Tsou, Tzu-Hung Chou
  • Patent number: 9111813
    Abstract: An etchant includes: 5 to 20 wt % of persulfate, 1 to 10 wt % of at least one compound of an inorganic acid, an inorganic acid salt, or a mixture thereof, 0.3 to 5 wt % of a cyclic amine compound, 1 to 10 wt % of at least one compound of an organic acid, an organic acid salt, or a mixture thereof, 0.1 to 5 wt % of p-toluenesulfonic acid, and water, based on the total weight of the etchant. A copper-titanium etchant further includes 0.01 to 2 wt % of a fluoride-containing compound. A method of forming a display device using the etchant, and a display device, are also disclosed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hong-Sick Park, Wang-Woo Lee, Sang-Tae Kim, Joon-Woo Lee, Young-Chul Park, Young-Jun Jin, Kyong-Min Kang, Young-Jin Yoon, Suck-Jun Lee, O-Byoung Kwon, In-Ho Yu, Sang-Hoon Jang, Min-Ki Lim, Dong-Ki Kim
  • Patent number: 9070779
    Abstract: A metal oxide thin film transistor includes a metal oxide semiconductor channel with the metal oxide semiconductor having a conduction band with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band with a second energy level equal to, or less than 0.5 eV above the first energy level.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: June 30, 2015
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Fatt Foong, Juergen Musolf, Gang Yu
  • Patent number: RE46985
    Abstract: A display device using a semiconductor light emitting device and a method of fabricating the semiconductor light emitting device are disclosed. The display device includes a substrate, a plurality of first electrodes disposed on the substrate, an anisotropic conductive film disposed on the substrate provided with the first electrodes, a plurality of semiconductor light emitting devices disposed on the anisotropic conductive film layer, electrically connected to the first electrodes, and constituting individual pixels, and a plurality of second electrodes disposed between the semiconductor light emitting devices and electrically connected to the semiconductor light emitting devices. Thus, alignment of the semiconductor light emitting device array may be simplified by use of an anisotropic conductive film Due to excellent brightness, the semiconductor light emitting devices, which are small in size, may form individual sub-pixels.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 7, 2018
    Assignee: LG ELECTRONICS INC.
    Inventor: Byungjoon Rhee