Abstract: A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n? polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.

Abstract: When a silicon-germanium mixed crystal layer is grown on a substrate by introducing a silicon source gas, a germanium source gas, a boron source gas, and a carbon source gas into a reaction chamber, the flow rate of the carbon source gas is set at 5 sccm or higher and the supply concentration of the carbon source gas is set as low as approximately 1.0% under the condition that the silicon-germanium mixed crystal layer is doped with carbon with a concentration of approximately 0.5%; resulting in, carbon with a concentration required to inhibit the diffusion of boron is doped into the layer and the concentration of carbon becomes equal to or higher than the concentration of boron in a region at any given depth.

Abstract: A method of manufacturing vertical NPN and PNP transistors on a substrate includes forming a first oxide film, a P-polycrystal silicon film, and a second oxide film successively on N-silicon epitaxial film on the substrate. An opening is made in the first oxide film to expose the N-silicon epitaxial film and a bottom of the P-polycrystal silicon film anisotropically etching the second oxide film and the P-polycrystal silicon film, and then isotropically etching the exposed first oxide film. A part of the opening is plugged by growing a selective epitaxial layer including a P-monocrystal layer from the surface of the N-silicon epitaxial film, and growing a polycrystal layer from the bottom of the P-polycrystal silicon film. Then, within a PNP transistor section, position and impurity concentration of a P-N junction are adjusted by self-aligned implanting or diffusing of P-impurities into the N-silicon epitaxial layer through the opening.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: A base of a low breakdown voltage npn bipolar transistor has p+ diffusion layers. A field insulating layer is formed on the p+ diffusion layer located between the p+ diffusion layer and an emitter, while the p+ diffusion layer encloses the surface of the emitter and has a window part immediately under the emitter. Thus, a semiconductor device and a method of fabricating the same capable of suppressing dispersion of a current amplification factor hFE in a wafer plane of the low breakdown voltage transistor and fabricating the low breakdown voltage transistor and a high breakdown voltage transistor through simple steps are obtained.

Abstract: A low-power bipolar transistor is formed to have a silicon germanium base region, an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The silicon germanium base region increases the speed of the transistor, while the small extrinsic emitter region reduces the maximum current that can flow through the transistor, and the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.

Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: Silicon carbide semiconductor power devices having epitaxially grown guard rings edge termination structure are provided. Forming the claimed guard rings from an epitaxially grown SiC layer avoids the traditional problems associated with implantation of guard rings, and permits the use of self aligning manufacturing techniques for making the silicon carbide semiconductor power devices.

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract: A method of manufacturing a semiconductor component includes providing a substrate (110) having a first doping concentration and growing an epitaxial layer (120, 520) over the substrate. The epitaxial layer has a second doping concentration lower than the first doping concentration, and the epitaxial layer has at least two effective, as-grown thicknesses. The resulting composite substrate is suitable for an integrated circuit having both high and low voltage portions.

Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.

Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.

Abstract: A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.

Abstract: Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.

Abstract: A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of free charge carriers the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area. The method starts with a semiconductor body having adjacent a first major surface (10b) a first semiconductor region (2) of one conductivity type. A mask (3, 4, 5) is provided on the first major surface, having at least one mask area masking a part (2a) of the first region. At least a part of the unmasked first region (2) is then removed to provide at least one opening (7) in the first region.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film having one portion below a surface of the semiconductor substrate and the other portion on the semiconductor substrate in a second region to the same thickness as the insulating film, which improves an operation speed even at a low voltage.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.

Abstract: A semiconductor device fabrication method includes the steps of forming a first insulation layer and a first semiconductor layer sequentially on a semiconductor substrate having a buried diffusion region therein. A second insulation layer is formed on the first semiconductor layer. The first insulation layer, the first semiconductor layer, and the second insulation layer are then patterned to create openings that expose the buried diffusion region. A third insulation layer is formed on respective side walls of the openings on the exposed portions of the first semiconductor layer, first insulation layer and second insulation layer that form the openings. A first epitaxial layer is formed on the semiconductor substrate exposed through the openings. A second epitaxial layer is then formed on the first epitaxial layer to be connected to the first semiconductor layer, thereby forming an active base region and a second conductive type collector region in the second epitaxial layer of the first and second openings.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

Abstract: Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).

Abstract: There is provided a bipolar transistor integrated circuit device having excellent characteristics by a simple process. A region where an impurity is not introduced is disposed in a part of a buried layer region for separating a collector region from a substrate, so that a bipolar transistor having low collector resistance can be formed. This can be applied also to a BiCMOS where insulated field effect transistors exist on the same substrate. These processes can be realized without adding a number of steps to a conventional process.

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Abstract: A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conductivity-altering dopant, and then isolation dopant of a conductivity type opposite to that of the substrate is introduced into the trench-circumscribed silicon region. The introduced isolation dopant is then thermally driven into the substrate, with lateral diffusion of isolation dopant physically constrained by the existing first narrow trench. Epitaxial silicon is then formed over the substrate, with polysilicon formed in regions overlying the filled narrow trench. A second, wider trench encompassing the first trench is etched to consume epitaxial silicon, polysilicon, and the sacrificial material. The second trench is then filled with dielectric material.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a collector contact region are formed in surface portions of the lightly doped n-type single crystal silicon layer, and the single crystal silicon layer is not affected by the heat during the growth of the thick field oxide layer, and has a flat zone constant in dopant concentration regardless of the thickness thereof.

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.

Abstract: A semiconductor device has a P type semiconductor substrate 1, a vertical type bipolar transistor having an N type base region 4, a lateral type bipolar transistor having an N type base region 4 formed on the semiconductor substrate 1, an N type collector region 7a, and an N type emitter region 8, and a P type insulating diffusion region 7b for isolating between vertical and lateral type bipolar transistors, at least one of collector and emitter regions of the lateral bipolar transistor having substantially same depth of the insulating diffusion region 7b.

Abstract: Since the PN junction of a photodiode is formed of a silicon substrate having a low impurity concentration and an epitaxial layer, the width of the depletion layer in the PN junction is formed wider, the parasitic capacitance by the junction capacitance is lowered, and the diffusion length of the silicon substrate is formed longer. Besides, a buried layer containing a high impurity concentration is formed by a high energy ion implantation method in such a depth that the buried layer cannot be depleted by a reverse voltage applied to the PN junction, which is served as a region to lead out the anode, which accordingly results in a low parasitic resistance at the anode. Thereby, the invention provides a semiconductor device including a photodetector and a method of manufacturing the same that achieves a high photoelectric conversion sensitivity and an excellent frequency characteristic at the same time.

Abstract: The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose.

Abstract: A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

Abstract: A new method of forming a buried contact junction in a process involving shallow trench isolation is described. A first silicon oxide layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. An opening is etched in the first silicon nitride and pad oxide layers where they are not covered by a mask. The substrate underlying the opening is etched into to form a shallow trench. An oxide material is deposited over the surface of the first silicon nitride layer and within the shallow trench and planarized to the surface of the first silicon nitride layer wherein the oxide material forms a STI region. The first silicon nitride layer is removed whereby the STI protrudes above the pad oxide layer. The pad oxide layer is removed whereby the corners of the STI above the substrate are also removed. A second silicon nitride layer is deposited overlying a sacrificial oxide layer and etched away to leave silicon nitride spacers filling in and rounding the corners of the STI.

Abstract: In a method for manufacturing a bipolar transistor, a semiconductor layer having a collector region of a first conductivity type is formed, and an epitaxial semiconductor layer of a second conductivity type is grown on the semiconductor layer. Then, impurities are thermally diffused from the epitaxial semiconductor layer into the semiconductor layer. Thus, a base region is formed by the epitaxial semiconductor layer and a part of the semiconductor layer.

Abstract: A method for fabricating a bipolar transistor improves the fast characteristics of the transistor at low operating voltages. An oxide film is formed on a semiconductor substrate, in which a buried layer is formed, and a floating poly base is formed on the oxide film. An insulating film is then formed on the entire surface of the semiconductor substrate including the floating poly base. The insulating film and the floating poly base are etched to define a base region and a collector region, and a first epitaxial layer is formed in the base and collector regions, with the first epitaxial layer having a smaller thickness than the oxide film. A second epitaxial layer is formed on the first epitaxial layer, and impurities are implanted into the second epitaxial layer in the base and collector regions. A second polysilicon layer is then formed on the second epitaxial layer in the base region, and electrodes are formed on the semiconductor surface.

Abstract: In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract: This invention provides a thin metallic sheet structure having excellent sound damping characteristics which can lower the sound pressure level of a sound inherent to a thin metallic sheet structure when this structure is patted, and can quickly damp the sound by a simple structure. In a flat sheet-like or box-like structure comprising a thin metallic external sheet and beams for reinforcing the external sheet, a thin metallic sheet structure having excellent sound damping characteristics according to the present invention employs the construction wherein the reinforcing beams 2 are brought into contact with one of the surfaces of the thin metallic external sheet 1 through a sound damping sheet 3, and the coupling state between the sound damping sheet 3 and the thin metallic external plate 1 or the reinforcing beams 2 is a non-coupling state or a discrete coupling state on at least one of the surfaces of the sound damping sheet 3.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).