Ordered Or Disordered Patents (Class 438/36)
  • Patent number: 11096615
    Abstract: An electrical patch and associated system for acquisition of physiological data is described. The patch has a design that enables a variety of configurations depending upon the requirements physiological measurements to be made. Patches with single input channels to patches with multiple input channels, processing capabilities and radio communication can all use the same physical configuration. The design includes a battery management system to enable long term data acquisition and an optimization process that includes mirroring of algorithms on the patch and devices local to the user with algorithms running on a centrally located server. The server can then optimize data acquisition and analysis algorithms. The components of the system and methods of use are included.
    Type: Grant
    Filed: May 15, 2016
    Date of Patent: August 24, 2021
    Inventors: Eric Baumann, Habib Homayoun, Lev Korzinov, David Churchville
  • Patent number: 10666017
    Abstract: An optoelectronic device employs a surface-trapped TM-polarized optical mode existing at a boundary between a distributed Bragg reflector (DBR) and a homogeneous medium, dielectric or air. The device contains a resonant optical cavity surrounded by two DBRs, and an additional DBR section on top supporting the surface-trapped mode. Selective chemical transformation, like selective oxidation, etching or alloy composition intermixing form a central core and a periphery having different vertical profiles of the refractive index. Therefore, the longitudinal VCSEL mode in the core is non-orthogonal to the surface-trapped mode in the periphery, and the two modes can be transformed into each other. Such transformation allows fabrication of a number of optoelectronic devices and systems like a single transverse mode VCSEL, an integrated optical circuit operating as an optical amplifier, an integrated optical circuit combining a VCSEL and a resonant cavity photodetector, etc.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 26, 2020
    Assignee: Vertically Integrated (VI) Systems GmbH
    Inventors: Nikolay Ledentsov, Vitaly Shchukin
  • Patent number: 10403649
    Abstract: A display device includes a common active pattern, a first gate electrode, and a second gate electrode. The common active pattern includes an NMOS area, a PMOS area, and a silicide area in a same layer as the NMOS area and the PMOS area. The silicide area electrically connects the NMOS area to the PMOS area. The NMOS area includes a first channel area and an n-doped area contacting the first channel area. The PMOS area includes a second channel area and a p-doped area contacting the second channel area. The first gate electrode overlaps the first channel area, and the second gate electrode overlaps the second channel area.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woonghee Jeong, Taehoon Yang, Kyoungwon Lee, Jongchan Lee, Yongsu Lee
  • Patent number: 10224463
    Abstract: An object of the present invention is to provide a film formation technique having high productivity by realizing a foundation layer having excellent crystallinity with a small film thickness of about 2 ?m. An embodiment of the present invention relates to a film forming method which includes the step of forming a buffer layer by sputtering on a sapphire substrate held by a substrate holder. The buffer layer includes an epitaxial film having a wurtzite structure prepared by adding at least one substance selected from the group consisting of C, Si, Ge, Mg, Zn, Mn, and Cr to AlxGa1?xN (where 0?x?1).
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: March 5, 2019
    Assignee: CANON ANELVA CORPORATION
    Inventor: Yoshiaki Daigo
  • Patent number: 9461119
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 4, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: T. Warren Weeks, Jr., Edwin Lanier Piner, Thomas Gehrke, Kevin J. Linthicum
  • Patent number: 9437686
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: T. Warren Weeks, Jr., Edwin Lanier Piner, Thomas Gehrke, Kevin J. Linthicum
  • Patent number: 9437687
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: T. Warren Weeks, Jr., Edwin L. Piner, Thomas Gehrke, Kevin J. Linthicum
  • Patent number: 8937394
    Abstract: An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: January 20, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Ting Chen, Li-Wen Lai, Kun-Wei Lin, Teng-Yen Wang
  • Patent number: 8932888
    Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 13, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8906725
    Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 9, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Stephen Moffatt
  • Patent number: 8883529
    Abstract: A semiconductor light emitting device having high reliability and excellent light distribution characteristics can be provided with an n-electrode arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack is mounted on a substrate. A plurality of convexes are arranged on a first convex region and a second convex region on the light extraction surface. The second convex region adjoins the interface between the n-electrode and the semiconductor stack, between the first convex region and the n-electrode. The base end of the first convex arranged in the first convex region is positioned closer to a light emitting layer than the interface between the n-electrode and the semiconductor stack, and the base end of the second convex arranged in the second convex region is positioned closer to the interface between the n-electrode and the semiconductor stack than the base end of the first convex.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 11, 2014
    Assignee: Nichia Corporation
    Inventors: Yohei Wakai, Hiroaki Matsumura, Kenji Oka
  • Patent number: 8866146
    Abstract: A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: October 21, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Angelo Mascarenhas, Myles A. Steiner, Lekhnath Bhusal, Yong Zhang
  • Patent number: 8827759
    Abstract: To make a light emitting device, a light emitting element is placed in a recess of a package, powders having a fluorescent material and coated with inorganic particles are provided, the fluorescent powders, fillers and a resin are mixed, the light emitting element placed in the recess of the package is sealed with the resin, and a centrifugal force is applied to the sealed package so that the fluorescent powders and the fillers sediment are pushed toward a bottom of the recess.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 9, 2014
    Assignee: Nichia Corporation
    Inventor: Masaki Kobashi
  • Patent number: 8828764
    Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 9, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8816321
    Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tadashi Takeoka, Yoshihiko Tani, Kazuya Araki, Yoshihiro Ueta
  • Publication number: 20140175440
    Abstract: Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Ilyas Mohammed, Liang Wang
  • Patent number: 8716752
    Abstract: A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 6, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove
  • Patent number: 8704248
    Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 22, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8691605
    Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 8, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Stephen Moffatt
  • Patent number: 8691404
    Abstract: A method of constructing a solid-state energy-density micro radioisotope power source device. In such embodiments, the method comprises depositing the pre-voltaic semiconductor composition, comprising a semiconductor material and a radioisotope material, into a micro chamber formed within a power source device body. The method additionally includes heating the body to a temperature at which the pre-voltaic semiconductor composition will liquefy within the micro chamber to provide a liquid state composite mixture. Furthermore, the method includes cooling the body and liquid state composite mixture such that liquid state composite mixture solidifies to provide a solid-state composite voltaic semiconductor, thereby providing a solid-state high energy-density micro radioisotope power source device.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: April 8, 2014
    Assignee: The Curators of the University of Missouri
    Inventors: Jae Wan Kwon, Tongtawee Wacharasindhu, John David Robertson
  • Patent number: 8686455
    Abstract: A composite substrate for the formation of a light-emitting device, ensuring that a high-quality nitride-based light-emitting diode can be easily formed on its top surface and the obtained substrate-attached light-emitting diode functions as a light-emitting device capable of emitting light for an arbitrary color such as white, is provided.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 1, 2014
    Assignees: Ube Industries, Ltd., Riken
    Inventors: Yasuyuki Ichizono, Hideki Hirayama
  • Patent number: 8679879
    Abstract: Disclosed are a method for fabricating a quantum dot. The method includes the steps of (a) preparing a compound semiconductor layer including a quantum well structure formed by sequentially stacking a first barrier layer, a well layer and a second barrier layer; (b) forming a dielectric thin film pattern including a first dielectric thin film having a thermal expansion coefficient higher than a thermal expansion coefficient of the second barrier layer and a second dielectric thin film having a thermal expansion coefficient lower than the thermal expansion coefficient of the second barrier layer on the second barrier layer; and (c) heat-treating the compound semiconductor layer formed thereon with the dielectric thin film pattern to cause an intermixing between elements of the well layer and elements of the barrier layers at a region of the compound semiconductor layer under the second dielectric thin film.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 25, 2014
    Assignee: Gwangju Institute of Science and Technology
    Inventor: Hong Seok Lee
  • Publication number: 20140030834
    Abstract: A film-forming method of organic light-emitting diode and a film-forming apparatus are disclosed. The method is to gasify organic materials to gaseous organic molecules and make the gaseous organic molecules to move to a surface of a substrate, and generate an electric field on the surface of the substrate so as to orient the gaseous organic molecules in the same direction. As the gaseous organic molecules contact the surface of the substrate, and the gaseous organic molecules condense to solid organic molecules to form a molecular film, and the solid organic molecules in the molecular film are oriented in the same direction.
    Type: Application
    Filed: August 31, 2012
    Publication date: January 30, 2014
    Applicant: SHENZHEN CHINA STAR OPTELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaohu Zhao
  • Publication number: 20140017839
    Abstract: An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, the optoelectronic device includes a first optoelectronic material that is inhomogeneously strained. A first charge carrier collector and a second charge carrier collector are each in electrical communication with the first optoelectronic material and are adapted to collect charge carriers from the first optoelectronic material. In another embodiment, a method of photocatalyzing a reaction includes using a strained optoelectronic material.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 16, 2014
    Applicant: Peking University
    Inventors: Ju Li, Xiaofeng Qian, Ji Feng
  • Patent number: 8558257
    Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: October 15, 2013
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8507928
    Abstract: An organic EL device includes a first organic EL element and a second organic EL element on an underlying layer that includes a first drive circuit unit for driving the first organic EL element and a second drive circuit unit for driving the second organic EL element. The organic EL device includes a partition on the underlying layer defining a first region including a first light-emitting layer of the first organic EL element and a second region including a second light-emitting layer of the second organic EL element. The partition defines the first film-forming region such that the first film-forming region includes the first drive circuit unit and the second film-forming region such that the second film-forming region does not include at least part of the second drive circuit unit. The first light-emitting layer is formed by a different method from that used for the second light-emitting layer.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: August 13, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Masahiro Uchida
  • Publication number: 20130200353
    Abstract: The device for charge carrier modulation is a current-controlled component, which has semiconductor layers arranged on top of each other. The organic semiconductor layers arranged on top of each other are an electron transport layer, which is arranged between a first and a second hole transport layer, and/or a hole transport layer, which is arranged between a first and a second electron transport layer. The respective central layer is the modulation layer having a contact for a modulation voltage. By applying a modulation voltage, a modulation current flow is generated over the modulation layer. The modulation current flow influences the component current flow which flows from the first into the second hole or electron transport layer via the respective modulation layer.
    Type: Application
    Filed: September 20, 2011
    Publication date: August 8, 2013
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Günter Schmid, Dan Taroata
  • Publication number: 20130187123
    Abstract: A field-emission device is disclosed. The device comprises a solid state structure formed of a crystalline material and an amorphous material, wherein an outer surface of the solid state structure is substantially devoid of the amorphous material, and wherein a p-type conductivity of the crystalline material is higher at or near the outer surface than far from the outer surface.
    Type: Application
    Filed: January 17, 2013
    Publication date: July 25, 2013
    Applicant: Technion Research & Development Foundation Ltd.
    Inventor: Technion Research & Development Foundation Ltd.
  • Patent number: 8492765
    Abstract: Provided is a display device that includes: a gate line disposed on a substrate, the gate line including a protruding gate electrode; a data line extending across the gate line, the data line having first and second segments spaced apart from each other; a semiconductor pattern overlapping with the gate electrode; a drain electrode that contacts a drain region of the semiconductor pattern and connects the first and second segments; a source electrode that contacts a source region of the semiconductor pattern; and a storage electrode overlapping with the data line.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seok-Je Seong, Jisuk Lim
  • Patent number: 8492185
    Abstract: A method for fabricating large-area nonpolar or semipolar GaN wafers with high quality, low stacking fault density, and relatively low dislocation density is described. The wafers are useful as seed crystals for subsequent bulk growth or as substrates for LEDs and laser diodes.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 23, 2013
    Assignee: Soraa, Inc.
    Inventors: Mark P. D'Evelyn, James Speck, William Houck, Mathew Schmidt, Arpan Chakraborty
  • Publication number: 20130037779
    Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 14, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tadashi Takeoka, Yoshihiko Tani, Kazuya Araki, Yoshihiro Ueta
  • Patent number: 8367434
    Abstract: Method for fabricating a substrate comprising a nanostructured surface for an organic light emitting diode OLED, in which a layer of an organic resin or of a mineral material having a first nanostructuration is prepared by nano-imprint; the organic resin or mineral material is heated to a temperature equal to or higher than its glass transition temperature Tg or its melting point, and the organic resin or the mineral material is maintained at this temperature for a time tR called annealing time, whereby the organic resin or the mineral material flows and the first nanostructuration of the layer of organic resin or of mineral material is modified to produce a second nanostructuration; the organic resin or the mineral material is cooled.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: February 5, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Alexandre Mary, Luc Andre, Stefan Landis
  • Patent number: 8334152
    Abstract: Semiconductor material is formed on a host substrate of a material exhibiting optical transparency with an intervening radiation lift off layer. A transfer device, intermediate substrate or target substrate is brought into adhesive contact with the semiconductor material and the radiation lift off layer is irradiated to weaken it, allowing the semiconductor material to be transferred off the host substrate. Electronic devices may be formed in the semiconductor layer while it is attached to the host substrate or the intermediate substrate.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 18, 2012
    Assignee: Cooledge Lighting, Inc.
    Inventor: Ingo Speier
  • Patent number: 8313965
    Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: November 20, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Stephen Moffatt
  • Patent number: 8304269
    Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device 11a includes a group III nitride semiconductor supporting base 13, a GaN based semiconductor region 15, an active layer active layer 17, and a GaN semiconductor region 19. The primary surface 13a of the group III nitride semiconductor supporting base 13 is not any polar plane, and forms a finite angle with a reference plane Sc that is orthogonal to a reference axis Cx extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region 15 is grown on the semipolar primary surface 13a. A GaN based semiconductor layer 21 of the GaN based semiconductor region 15 is, for example, an n-type GaN based semiconductor, and the n-type GaN based semiconductor is doped with silicon.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: November 6, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Yusuke Yoshizumi, Yohei Enya, Katsushi Akita, Masaki Ueno, Takamichi Sumitomo, Takao Nakamura
  • Patent number: 8218919
    Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: July 10, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventor: Karen Tyger
  • Publication number: 20120032187
    Abstract: A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.
    Type: Application
    Filed: April 15, 2010
    Publication date: February 9, 2012
    Applicant: Alliance for Sustainable Energy, LLC
    Inventors: Angelo Mascarenhas, Myles A. Steiner, Lekhnath Bhusal, Yong Zhang
  • Patent number: 8105921
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: January 31, 2012
    Assignee: International Rectifier Corporation
    Inventors: T. Warren Weeks, Jr., Edwin Lanier Piner, Thomas Gehrke, Kevin J. Linthicum
  • Patent number: 8090229
    Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: January 3, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventor: Karen Tyger
  • Publication number: 20110227038
    Abstract: A semiconductor light emitting device comprising a semiconductor layer of (AlyGa1-y)xIn1-xP (0<x?1, 0?y?1) that consists of a first semiconductor layer of a first electrical conduction type, an active layer of a multiple quantum well structure containing a barrier layer and a distortion-containing well layer, a second semiconductor layer of a second electrical conduction type, and a third semiconductor layer of the second electrical conduction type, constructed in this order in the form of a generally flat laminate; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the third semiconductor layer; wherein part of the active layer facing the second semiconductor layer side is inclined from the surface of the active layer toward its normal, and the third semiconductor layer has a composition of Ga1-zInzP (0?z?0.35).
    Type: Application
    Filed: March 15, 2011
    Publication date: September 22, 2011
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventor: Wataru TAMURA
  • Publication number: 20110223701
    Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device 11a includes a group III nitride semiconductor supporting base 13, a GaN based semiconductor region 15, an active layer active layer 17, and a GaN semiconductor region 19. The primary surface 13a of the group III nitride semiconductor supporting base 13 is not any polar plane, and forms a finite angle with a reference plane Sc that is orthogonal to a reference axis Cx extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region 15 is grown on the semipolar primary surface 13a. A GaN based semiconductor layer 21 of the GaN based semiconductor region 15 is, for example, an n-type GaN based semiconductor, and the n-type GaN based semiconductor is doped with silicon.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 15, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Yusuke YOSHIZUMI, Yohei ENYA, Katsushi AKITA, Masaki UENO, Takamichi SUMITOMO, Takao NAKAMURA
  • Patent number: 7994520
    Abstract: Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: August 9, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Kyong Jun Kim
  • Publication number: 20110133204
    Abstract: A light emitting diode includes a thermal conductive substrate, an p-type GaN layer, an active layer and an n-type GaN layer sequentially stacked above the substrate and an electrode pad deposited on the n-type GaN layer. A surface of n-type GaN layer away from the active layer has a first diffusing section and a second diffusing section. The first diffusing section is adjacent to the electrode pad and the second diffusing section is located at the other side of the first diffusing section opposite to the electrode pad, wherein the doping concentration of the first diffusing section is less than that of the second diffusing section. The n-type GaN layer has an electrical resistance larger than that of the first diffusing section which in turn is larger than that of the second diffusing section.
    Type: Application
    Filed: September 17, 2010
    Publication date: June 9, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIH-CHEN LAI
  • Patent number: 7955875
    Abstract: Methods of forming a light emitting device include selectively forming a wavelength conversion structure on a light emitting element using stereolithography. Selectively forming the wavelength conversion structure may include covering the light emitting element with a photo-curable liquid polymer containing a luminescent material, and exposing the liquid polymer to light for a time sufficient to at least partially cure the liquid polymer. Multiple layers of polymer can be selectively built up to form a wavelength conversion structure having a custom shape on the light emitting element.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: June 7, 2011
    Assignee: Cree, Inc.
    Inventor: Craig Hardin
  • Publication number: 20110051771
    Abstract: An optoelectronic component contains an epitaxial layer sequence (6) based on a nitride compound semiconductor having an active layer (4) and, wherein the epitaxial growth substrate (1) comprises Al1-xGaxN, where 0<x<0.95. In the case of a method for producing an optoelectronic component an epitaxial growth substrate (1) of Al1-x(InyGa1-y)xN or In1-xGaxN, where 0<x<0.99 and 0?y?1 is provided and an epitaxial layer sequence (6) which is based on a nitride compound semiconductor and contains an active layer (4) is grown thereon.
    Type: Application
    Filed: January 28, 2009
    Publication date: March 3, 2011
    Applicant: OSRAM Opto Semiconductors GmbH
    Inventors: Adrian Stefan Avramescu, Christoph Eichler, Uwe Strauss, Volke Härle
  • Patent number: 7888145
    Abstract: A selective oxidation layer is formed by alternately growing an AlAs layer and an XAs layer containing a group III element X with a thickness ratio in a range between 97:3 and 99:1 on a plurality of semiconductor layers including an active layer. The selective oxidation layer is selectively oxidized to manufacture a vertical-cavity surface-emitting laser.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: February 15, 2011
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Keishi Takaki, Norihiro Iwai, Hitoshi Shimizu, Takeo Kageyama
  • Patent number: 7884466
    Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: February 8, 2011
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masamichi Ishihara, Fumihiko Ooka, Yoshihiko Ino
  • Patent number: 7880189
    Abstract: A light-emitting semiconductor component comprising a substrate which has a first interface between a first and a second silicon layer, whose lattice structures which are considered as ideal are rotated relative to each other through a twist angle about a first axis perpendicular to the substrate surface and are tilted through a tilt angle about a second axis parallel to the substrate surface, in such a way that a dislocation network is present in the region of the interface, wherein the twist angle and the tilt angle are so selected that an electroluminescence spectrum of the semiconductor component has an absolute maximum of the emitted light intensity at either 1.3 micrometers light wavelength or 1.55 micrometers light wavelength.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: February 1, 2011
    Assignee: IHP GmbH-Innovations for High Performance Microelectronics/ Leibniz-Institut für innovative Mikroelektronik
    Inventors: Martin Kittler, Manfred Reiche, Tzanimir Arguirov, Winfried Seifert
  • Publication number: 20110017976
    Abstract: A light emitting device with a template comprising a substrate and a nested superlattice. The superlattice has Al1-x-yInyGaxN wherein 0?x?? and 0?y?1 with x increasing with distance from said substrate. An ultraviolet light-emitting structure on the template has a first layer with a first conductivity comprising Al1-x-yInyGaxN wherein ??x; a light emitting quantum well region above the first layer comprising Al1-x-yInyGaxN wherein ??x?b; and a second layer over the light emitting quantum well with a second conductivity comprising Al1-x-yInyGaxN wherein b?x. The light emitting device also has a first electrical contact in electrical connection with the first layer, a second electrical contact in electrical connection with the second layer; and the device emits ultraviolet light.
    Type: Application
    Filed: March 27, 2009
    Publication date: January 27, 2011
    Applicant: NITEK, INC
    Inventors: Asif Khan, Qhalid Fareed
  • Patent number: 7842529
    Abstract: In a method for manufacturing a III-V nitride compound semiconductor light emitting element, light emitting element regions (21) are formed in a low dislocation region on the III-V nitride compound semiconductor substrate wherein high density dislocation sections (22) and low dislocation regions are alternately arranged repeatedly, so that stripe-shaped light emitting regions are in parallel to the direction wherein the high density dislocation sections (22) extend, and then the substrate is broken, after making two scribe lines (23) to have the high density dislocation section (22) in between, on a plane (25) on the opposite side to a plane (24) whereupon the element regions (21) are formed. Thus, chips are separated and the high density dislocation sections (22) can be removed. The pitch of the two scribe lines is preferably 100 ?m or more.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: November 30, 2010
    Assignees: Tottori Sanyo Electric Co., Ltd., Sanyo Electric Co., Ltd.
    Inventor: Katsunori Kontani