Voltage Variable Capacitance Device Manufacture (e.g., Varactor, Etc.) Patents (Class 438/379)
  • Patent number: 11015262
    Abstract: An apparatus and method for molecular beam epitaxy are described herein. The apparatus comprises an enclosure defining a vacuum chamber. A substrate holder is mounted within the vacuum chamber. At least one molecular beam source is in fluid communication with the vacuum chamber. A cooling shroud having at least one surface is mounted within the vacuum chamber spaced from the substrate holder. A cryocooler having at least a portion extending into the vacuum chamber is operatively coupled to the cooling shroud for extracting heat therefrom, and cooling the at least one surface of the cooling shroud to cryogenic temperatures.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 25, 2021
    Assignee: ANYON SYSTEMS INC.
    Inventors: Alireza Najafi-Yazdi, William Georges
  • Patent number: 9660038
    Abstract: A lateral semiconductor device and/or design including a space-charge generating layer and an electrode or a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 23, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Mikhail Gaevski, Michael Shur
  • Patent number: 9570630
    Abstract: The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: February 14, 2017
    Assignee: MEDIATEK INC.
    Inventor: Puo-Yu Chiang
  • Patent number: 9461183
    Abstract: A diode comprising a reduced surface field effect trench structure, the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate, the joining region comprising an electrical contact and a layer of p-doped semiconductor material.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: October 4, 2016
    Assignee: NXP B.V.
    Inventors: Tim Boettcher, Jan Fischer
  • Patent number: 9431510
    Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Chengjie Zuo, Chi Shun Lo, Jonghae Kim, Mario F. Velez
  • Patent number: 9269832
    Abstract: Disclosed is an integrated circuit (100), comprising a semiconductor substrate (110) carrying a plurality of circuit elements; and a pressure sensor including a cavity (140) on said semiconductor substrate, said cavity comprising a pair of electrodes (120, 122) laterally separated from each other; and a flexible membrane (130) over and spatially separated from said electrodes such that said membrane interferes with a fringe field between said electrodes, said membrane comprising at least one aperture (132). A method of manufacturing such an IC is also disclosed.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 23, 2016
    Assignee: AMS INTERNATIONAL AG
    Inventors: Axel Nackaerts, Willem Frederik Adrianus Besling, Klaus Reimann
  • Patent number: 9224828
    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 29, 2015
    Assignee: Avogy, Inc.
    Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
  • Patent number: 9184240
    Abstract: There is provided a method of producing a semiconductor wafer, including: forming a compound semiconductor layer on a base wafer by epitaxial growth; cleansing a surface of the compound semiconductor layer by means of a cleansing agent containing a selenium compound; and forming an insulating layer on the surface of the compound semiconductor layer. Examples of the selenium compound include a selenium oxide. Examples of the selenium oxide include H2SeO3. The cleansing agent may further contain one or more substances selected from the group consisting of water, ammonium, and ethanol. When the surface of the compound semiconductor layer is made of InxGa1-xAs (0?x?1), the insulating layer is preferably made of Al2O3, and Al2O3 is preferably formed by ALD.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: November 10, 2015
    Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masahiko Hata, Osamu Ichikawa, Yuji Urabe, Noriyuki Miyata, Tatsuro Maeda, Tetsuji Yasuda
  • Publication number: 20150118819
    Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
    Type: Application
    Filed: November 26, 2014
    Publication date: April 30, 2015
    Inventors: Changhan Hobie YUN, Chengjie ZUO, Chi Shun LO, Jonghae KIM, Mario Francisco VELEZ
  • Patent number: 8981529
    Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: March 17, 2015
    Assignees: STMicroelectronics SA, International Business Machines Corporation
    Inventors: Yvan Morandini, Romain Debrouke
  • Publication number: 20140367831
    Abstract: A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO
  • Publication number: 20140332928
    Abstract: A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable capacitor with MOS compatible structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the capacitance value between the other two terminals of the device, by increasing or decreasing its DC voltage with respect to one of the main terminals of the device. Furthermore, the present invention decouples the AC signal and the DC control voltage preventing distortion of the RF signal. The present invention describes a controllable capacitor whose capacitance value is not necessarily linear with its control voltage, but although possibly abrupt in its characteristic, is utilized to manufacture a semiconductor variable capacitor with digital control to improve its noise and linearity performance while maintaining high quality factor.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 13, 2014
    Inventors: Fabio Alessio Marino, Paolo Menegoli
  • Publication number: 20140327016
    Abstract: A varactor comprising two Schottky diodes, each diode comprising a substrate and a plurality of layers formed on the substrate including at least one GaN layer and at least one semi-insulating material layer formed of a material with an energy gap greater than 3.5 and free carrier mobility less than 300 cm2/V-s; the Schottky diodes having cathodes adapted to be connected to an AC voltage input and being configured so that as the AC voltage applied to the cathodes increases the capacitance decreases nonlinearly, the nonlinear transition from high capacitance to low capacitance being adjustable by utilizing the intrinsic carrier concentration of the semi-insulating layer to obtain an optimal nonlinear transition for the predetermined AC voltage applied to the cathodes. A method of making a varactor comprising computer modeling to produce capacitance-voltage curves, modifying at least one semi-insulating region, and modeling power input/output efficiency for a predetermined input signal.
    Type: Application
    Filed: July 23, 2014
    Publication date: November 6, 2014
    Inventors: PANKAJ B. SHAH, H. ALFRED HUNG
  • Publication number: 20140308793
    Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 16, 2014
    Inventors: Josef Dietl, Raimund Peichl, Gabriele Bettineschi
  • Patent number: 8796809
    Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: August 5, 2014
    Assignee: Cree, Inc.
    Inventor: Christopher Harris
  • Patent number: 8748934
    Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: June 10, 2014
    Assignee: Tsinghua University
    Inventors: Liyang Pan, Fang Yuan
  • Patent number: 8735257
    Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Patent number: 8728933
    Abstract: A method of kerf formation and treatment for solar cells and semiconductor films and a system therefor are described. A semiconductor film is backed by a first metal layer and topped by a second metal layer. A reference feature is defined on the film. An ultraviolet laser beam is aligned to the reference feature. A kerf is cut along the reference feature, using the ultraviolet laser beam. The beam cuts through the second metal layer, through the film and through the first metal layer. Cutting leaves debris deposited on walls of the kerf. The debris is cleaned off of the walls, using an acid-based solvent. In the case of solar cells, respective first terminals of the solar cells are electrically isolated by the cleaned kerf, and respective negative terminals of the solar cells are electrically isolated by the cleaned kerf.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 20, 2014
    Assignee: Alta Devices, Inc.
    Inventors: Michael Andres, Laila Mattos, Daniel G. Patterson, Gang He
  • Publication number: 20140124893
    Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Josef Dietl, Raimund Peichl, Gabriele Bettineschi
  • Patent number: 8716126
    Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Peter Baars, Frank Feustel
  • Patent number: 8691707
    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: April 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Yiming Li
  • Patent number: 8685827
    Abstract: A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion on the substrate, the resistor portion including a third gate oxide layer and a third polysilicon layer on the third gate oxide layer, covering the resistor portion with a photoresist, removing respective first portions of the first and second polysilicon layers from the first and second gate stack portions, removing the photoresist from the resistor portion, and after removing the photoresist from the resistor portion, removing respective remaining portions of the first and second polysilicon layers from the first and second gate stack portions.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ju Youn Kim, Jedon Kim
  • Patent number: 8669605
    Abstract: A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: March 11, 2014
    Inventor: Yoshiaki Shimizu
  • Patent number: 8633562
    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: January 21, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Yiming Li
  • Patent number: 8609479
    Abstract: In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chewn-Pu Jou, Chin Wei Kuo, Sally Liu
  • Patent number: 8598683
    Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Edward J. Nowak
  • Publication number: 20130292683
    Abstract: An electronic device comprising a substrate; a pair of stacks of polar semiconductor materials which create a charge by spontaneous and/or piezoelectric polarization; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is in a direction opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced. A method of substantially eliminating the bias required to offset polarization charges in an electronic device having a heterobarrier comprising providing a substrate; growing at least one pair of stacks of semiconductor materials; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced to substantially eliminate the need for a voltage bias.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Applicant: U.S. Government as represented by the Secretary of the Army
    Inventor: PANKAJ B. SHAH
  • Patent number: 8530319
    Abstract: An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ephrem G. Gebreselasie, Joseph M. Lukaitis, Robert R. Robison, William R. Tonti, Ping-Chuan Wang
  • Publication number: 20130200494
    Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.
    Type: Application
    Filed: February 5, 2012
    Publication date: August 8, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Zhiying CHEN, Jianping ZHAO, Lee CHEN, Merritt FUNK, Radha SUNDARARAJAN
  • Patent number: 8502348
    Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yue-Shiun Lee, Cheng-Hsiung Chen, Meng-Fan Wang
  • Publication number: 20130181784
    Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 18, 2013
    Applicants: International Business Machines Corporation, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., International Business Machines Corporation
  • Patent number: 8486798
    Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.
    Type: Grant
    Filed: February 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Zhiying Chen, Jianping Zhao, Lee Chen, Merritt Funk, Radha Sundararajan
  • Publication number: 20130140678
    Abstract: The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die.
    Type: Application
    Filed: January 25, 2013
    Publication date: June 6, 2013
    Applicant: RF MICRO DEVICES, INC.
    Inventor: RF Micro Devices, Inc.
  • Patent number: 8450827
    Abstract: Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Patent number: 8450832
    Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manju Sarkar, Purakh Raj Verma
  • Publication number: 20130113081
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ZHIHONG CHEN, SHU-JEN HAN, SIYURANGA O. KOSWATTA, ALBERTO VALDES GARCIA
  • Publication number: 20130100090
    Abstract: This disclosure provides systems, methods and apparatus for electromechanical systems variable capacitance devices. In one aspect, an electromechanical systems variable capacitance device includes a substrate with a first metal layer including a first bias electrode overlying the substrate. A member suspended above the first metal layer includes a dielectric beam and a second metal layer including a first radio frequency electrode and a ground electrode. The member and the first metal layer define a first air gap. A third metal layer over the member includes a second bias electrode, and the third metal layer and the member define a second air gap. The member includes a plane of symmetry substantially parallel a plane containing the first bias electrode.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Daniel FELNHOFER, Wenyue ZHANG, Je-Hsuing LAN
  • Patent number: 8399352
    Abstract: When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 19, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Peter Baars, Frank Feustel
  • Publication number: 20130049646
    Abstract: An energy conversion device, and methods of manufacturing and operating the same. The energy conversion device includes: a monolithic single-crystal silicon layer that includes a plurality of doping regions; a vibrator that is disposed in the single-crystal silicon layer and is connected to a doping region of the plurality of doping regions; a first diode that is a PN junction diode and allows an input signal applied to the vibrator to pass therethrough; and a second diode that is a PN junction diode and allows a signal output from the vibrator to pass therethrough.
    Type: Application
    Filed: June 19, 2012
    Publication date: February 28, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Che-heung KIM, Jong-oh KWON
  • Patent number: 8334179
    Abstract: A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 18, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 8324064
    Abstract: Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 4, 2012
    Assignee: Freescale Semiconductors, Inc.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Publication number: 20120262229
    Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas M. Daley, Mete Erturk, Edward J. Gordon
  • Patent number: 8288839
    Abstract: A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: October 16, 2012
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 8273616
    Abstract: Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chewn-Pu Jou, Chin-Wei Kuo, Sally Liu
  • Patent number: 8232624
    Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Joseph E. Nowak
  • Publication number: 20120146188
    Abstract: A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 14, 2012
    Inventors: Fan Chen, Xiongbin Chen
  • Patent number: 8163612
    Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Erik M Dahlstrom, Alvin J Joseph, Robert M Rassel, David C Sheridan
  • Publication number: 20120081188
    Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Li Liu, Chiewcharn Narathong
  • Patent number: 8148800
    Abstract: A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink. The residual carrier sink is located at or adjacent to the semiconductor nanowire near the semiconductor junction and employs one or both of enhanced recombination and direct extraction of the residual carriers. The method includes providing a semiconductor nanowire, forming a semiconductor junction within the semiconductor nanowire, forming a residual carrier sink, and removing residual carriers from the semiconductor junction region using the residual carrier sink.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 3, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Theodore I. Kamins
  • Patent number: 8129814
    Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Prakash Pendharkar, Eugen Pompiliu Mindricelu