Abstract: A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface, source and drain layers formed in the first major surface, a gate insulating film formed on the first major surface, a gate layer formed on the gate insulating film, a source electrode formed on the first major surface and electrically connected to the source layer, a drain electrode formed on the first major surface, electrically connected to the drain layer, and having a second isolation portion, a gate electrode formed on the first major surface, electrically connected to the gate layer, and having a first isolation portion, a first capacitance adjusting electrode formed on the gate insulating film and having a first capacitance adjusted by the first isolation portion, and a second capacitance adjusting electrode formed on the gate insulating film and having a second capacitance adjusted by the second isolation portion.

Abstract: A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.

Abstract: A semiconductor component is provided having a layer sequence for conversion of acoustic to thermal signals and electrical voltage changes to one another, as well as a process for its production. The layer sequence has a lower electrode, an upper electrode and a layer which is arranged between them and is piezoelectrical or pyroelectrical. An auxiliary layer is arranged between the lower electrode and the layer and is used for homogeneously oriented growth of the layer during the production process. The auxiliary layer preferably consists essentially of amorphous silicon, amorphous silicon oxide or amorphous silicon nitride.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n? region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n? region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n? region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n? region 132 is lower than that in each of the anode 133 and the cathode 131.

Abstract: A charge control circuit for controlling a micro-electromechanical device having a variable capacitance is disclosed. In one embodiment, a charge storage device is configured to store a charge amount. A switch circuit is configured to control the variable capacitance of the micro-electromechanical device by sharing the charge amount between the charge storage device and the micro-electromechanical device to equalize the charge storage device and the micro-electromechanical device to a same voltage.

Abstract: In one embodiment, a varactor includes a first node and a second node. The varactor includes: at least one first varactor element including a source, a drain, and a p-type doped gate; at least one second varactor element including a source, a drain, and an n-type doped gate; and at least one third varactor element including a source, a drain, and an intermediately doped gate, the intermediately doped gate having doping characteristics intermediate to doping characteristics of the p-type and n-type gates. The varactor includes one or more wells in a substrate region underlying the first, second, and third varactor elements. The first, second, and third varactor elements are coupled in parallel between the first and second nodes.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solide state chemical sensors. Detection of the following chemical species was established: hydrogen, deuterium, carbon monoxide, molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: This invention relates to an apparatus and method of using a high frequency, high power, fluid dielectric variable capacitor for an impedance matching network. The apparatus consists of a bow-tie rotary vane, a set of two fixed vanes, and a set of rotating vanes adapted to rotate interdigitally between the fixed vanes. A dielectric fluid is circulated between the fixed vanes and the rotating vanes for cooling the device. This arrangement facilitates production of a device having a higher capacitance and a smaller size, thus making it suitable for use in a matching network.

Abstract: A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (10; 10, 41); forming a buried n+-doped region (31) in the substrate; forming in the substrate an n-doped region (41) above the buried n+-doped region (31); forming field isolation (81) around the n-doped region (41); multiple ion implanting the n-doped region (41); forming a p+-doped region (151) on the n-doped region (41); forming an n+-doped contact region to the buried n+-doped region (31), the contact region being separated from the n-doped region (41); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (41); the formation of the p+-doped region (151); and the heat treatment are performed to obtain a hyper-abrupt p+/n-junction within the n-doped region (41).

Abstract: The present invention is directed to an electrolytic capacitor having a novel floating anode between the cathode and the powered anode of the capacitor, resulting in a single capacitor having a working voltage double that of the formation voltage of the powered anode. The floating anode acts as cathode to the powered anode and as an anode to the cathode, such that the capacitor according to the present invention supports half the working voltage between the cathode and the floating anode and half the working voltage between the floating anode and the powered anode. The arrangement of the cathode, floating anode and powered anode according to the present invention results in a single capacitor with half the capacitance and twice the voltage of a single anode device.

Abstract: A simple metal dielectric semiconductor (MDS) variable capacitor which may be a MOS capacitor uses the drain and source of a floating gate metal dielectric semiconductor field effect transistor connected to the bulk of the semiconductor substrate as one plate of the capacitor and the gate of the transistor as the other plate. The capacitance is voltage dependent and is strongly nonlinear in the depletion region. The accumulation and strong inversion regions are also nonlinear, but to a much smaller degree. The nonlinearity can be significantly reduced by connecting two of the capacitors in series. This series connection also makes possible a capacitor structure with an isolated floating gate connecting the two series capacitors. The charge on the floating gate can be controlled by tunneling and injection to vary the capacitor bias voltage and thus, its capacitance. Alternatively, the capacitors may operate in the accumulation region.

Abstract: The present invention discloses a method for manufacturing an MOS varactor which can be utilized as a high frequency device with an increased capacitance of the varactor part while maintaining the characteristics of a transistor by forming a gate oxide film of the MOS varactor by a high dielectric material as compared to a gate oxide film of the transistor.

Abstract: An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+ diffusion regions are connected to a ground potential wiring. Further, an n+ diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+ diffusion regions absorb positive holes serving as minority carriers from a channel region.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: A semiconductor diode with hydrogen detection capability includes a semiconductor substrate, a doped semiconductor active layer formed on the substrate and made from a compound having the formula XYZ, in which X is a Group III element, Y is another Group III element different from X, and Z is a Group V element, a semiconductor contact-enhancing layer formed on the active layer and made from a compound having the formula MN, in which M is a Group III element, and N is a Group V element, an ohmic contact layer formed on the semiconductor contact-enhancing layer, and a Schottky barrier contact layer formed on the active layer. The Schottky barrier contact layer is made from a metal that is capable of dissociating a hydrogen molecule into hydrogen atoms.

Abstract: Micro-electro-mechanical system (MEMS) variable capacitor apparatuses, system and related methods are provided.

Abstract: A Semiconductor component, such as an IGBT, a thyristor, a GTO or a diode, and especially a Schottky diode is provided that is capable of blocking for producing a termination portion of a semiconductor component. An insulator profile of an insulator portion includes a curved surface, which is free of steps and is produced by gray-tone lithography in the termination portion of an anode. The device also includes a substrate that is covered with an insulating layer having a thickness of between 0.5 &mgr;m and 15 &mgr;m, an insulator layer having a thickness is covered with a photosensitive layer (photoresist layer) where the photoresist layer is exposed through a mask, which changes in its gray-tone value in accordance with the course of curvature of the surface of at least one insulator profile, and is subsequently structured to form at least one resist remainder.

Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract: A parallel-plate, voltage-variable capacitor is designed to have an increased current conducting perimeter relative to its area. In one approach, the perimeter is increased by changing the shape of the plates. In another approach, the varactor is implemented by a number of disjoint plates, which are coupled in parallel.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive component integration directly on the motherboard (200) or chip (230) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors (214), resistors (212) and capacitors (216) can be integrated on the device (140) over the porous silicon region (130). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.

Abstract: An array of nanometric dimensions consisting of two or more arms, positioned side by side, wherein the arms are of such nanometric dimensions that the beams can be moved or deformed towards or away from one another by means of a low voltage applied between the beams, whereby to produce a desired optical, electronic or mechanical effect. At nanometer scale dimensions structures previously treated as rigid become flexible, and this flexibility can be engineered since it is a direct consequence of material and dimensions. Since the electrostatic force between the two arms is inversely proportional to the square of the distance, a very considerable force will be developed with a low voltage of the order of 1-5 volts, which is sufficient to deflect the elements towards or away from one another.

Abstract: In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P+ gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the PLL.

Abstract: A parallel capacitor structure that can be fabricated using advanced processing techniques that employ, for example, copper interconnects and low k dielectrics is described. The parallel capacitor structure includes a first copper dual Damascene interconnection line, a first interconnection, a middle capacitor electrode, a dielectric layer, a second interconnection, an upper capacitor electrode, and a second interlayer dielectric layer. The existing first copper dual Damascene interconnection line is embedded in a first interlayer dielectric layer, and is utilized as a lower capacitor electrode. The middle capacitor electrode is on the first copper dual Damascene interconnection line. The dielectric layer is interposed between the first copper dual Damascene interconnection line and the middle capacitor electrode. The second interconnection can be directly connected to the middle capacitor electrode.

Abstract: The present invention concerns an integrated variable capacitance device comprising at least one membrane (12) forming at least one mobile armature and having at least one principal face facing at least one fixed armature. In accordance with the invention, the membrane has at least one rigidity rib (32) lying in a perpendicular direction to said principal face.

Abstract: A method of fabricating a hyperabrupt junction varactor diode structure comprises the steps of forming a non-uniformly doped n-type, hyperabrupt cathode region in a layer of semiconductor material and depositing, by ultra high vacuum chemical vapor deposition (UHVCVD), a p-type anode region onto a surface of the hyperabrupt cathode region. The deposition process is performed at relatively low temperature (i.e., below 600° C.). The anode region and the hyperabrupt cathode are joined at a junction between them such that an impurity concentration level of the hyperabrupt region increases in a direction toward the junction. During the forming step, n-type impurity ions are implanted at an implantation energy level substantially less than 300 keV, preferably between from about 10 to about 70 keV, with the implanted ions being thermally activated at a relatively low temperature (between from about 700 to about 800° C.).

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract: An integrated adjustable capacitor device and method for making such a device are provided. The adjustable capacitor includes an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The adjustable capacitor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

Abstract: A first MISFET is formed in a first active region on the surface of a semiconductor substrate. The drain region of the first MISFET has a lightly doped drain structure with a low concentration region and a high concentration region. The side wall spacer conformingly covers the side wall of the gate electrode and the surface of the low concentration region in the drain region. A second MISFET is formed in a second active region. The side wall spacer of the second MISFET covers the side wall of the gate electrode and do not extend further to the surfaces of the source and drain regions. An interlayer insulating film covers the said first MISFET and second MISFET and is made of material having an etching resistance different from that of the side wall spacers of the first MISFET and second MISFET.

Abstract: An integrated adjustable capacitor device and method for making such a device are provided. The adjustable capacitor includes an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The adjustable capacitor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.

Abstract: A semiconductor device, such as a pin diode, includes a first drift layer, a second drift layer, an anode layer on the first drift layer, and a buffer layer formed between the first and second drift layers. The shortest distance from the pn-junction between the anode layer and the buffer layer, and the thickness of the buffer layer are set at the respective values at which a high breakdown voltage is obtained, while reducing the tradeoff relation between the soft recovery and the fast and low-loss reverse recovery.

Abstract: A vertical MIM capacitor (140) including a first conductive line (124) and second conductive line (136) sandwiched around a vertical portion of a capacitor dielectric (134). Additional conductive lines (136) may be positioned vertically proximate first conductive lines (124) separated by another vertical portion of capacitor dielectric (134) to form a double-sided capacitor (142), increasing the capacitance. A plurality of vertical MIMcaps (140, 142) may be coupled together in parallel to increase the capacitance.

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A method of producing a Schottky varicap (25) including: (a) providing an epitaxial layer (12) on a semiconductor substrate (1); (b) providing an insulating layer including an oxide layer and a nitride layer on a predetermined area of the surface of the epitaxial layer (12); (c) depositing a polysilicon layer (6); (d) applying a first high temperature step to diffuse a guard ring (10) around the first predetermined area; (e) removing a predetermined portion of the polysilicon layer (6) to expose the first silicon nitride film (5); (f) implanting atoms through at least the first oxide film (4) to provide a predetermined varicap doping profile; (g) applying a second high temperature step to anneal and activate the varicap doping profile; (h) removing the first oxide film (4) to provide an exposed area; (i) providing a Schottky electrode (17) on the exposed area.

Abstract: The invention relates to a variable capacitor and method of making it. The variable capacitor comprises a fixed charge plate disposed in a substrate, a movable charge plate disposed above the fixed charge plate, and a stiffener affixed to the movable charge plate. The movable charge plate may be patterned to form a movable actuator plate where the fixed charge plate is elevated above a fixed actuator plate.

Abstract: A semiconductor diode structure comprising a Schottky junction, where a metal contact and a silicon carbide semiconducting layer of a first conducting type form said junction and where the edge of the junction exhibits a Junction Termination Extension (JTE) laterally surrounding the junction, said JTE having a charge profile with a stepwise or uniformly decreasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the centre part of the JTE towards the outermost edge of the termination. The object of the junction termination extension is to control the electric field at the periphery of the diode.

Abstract: A MOS-type capacitor includes a semiconductor substrate of a first conductive type serving as a first electrode, a conductor layer formed on the semiconductor substrate via a capacitive insulation film and serving as a second electrode, and an impurity region of a second conductive type formed in the vicinity of the surface of the semiconductor substrate at a location in proximity to a region facing the conductor layer. The MOS-type capacitor is used as a variable capacitor in a VCO (voltage-controlled oscillator) having a widened frequency range.

Abstract: A method of producing a Schottky varicap (25) including:

Abstract: A variable capacitance semiconductor device (10) such as a varactor diode, is formed to have a plurality of openings (13), such as a plurality of trenches, that cause the depletion regions (16) to overlap. This overlap results in a rapid change of capacitance for a given change of voltage, and allows efficient operation over a small voltage range.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.