Abstract: A process of manufacturing parallel-plate microstructures by integrating the microstructures in a chip using a CMOS process is provided. A MEMS variable capacitor, a tunable band-pass filter, tunable matching networks, and capacitive RF-MEME switches all having vertically movable components and are integrated into a chip.

Abstract: An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that the first conductive layer is electrically connected to the N-type semiconductor and the P-type semiconductor; a dielectric layer laminated on an upper surface of the first conductive layer; and a second conductive layer laminated on an upper surface of the dielectric layer so that the second conductive layer forms a capacitor together with the first conductive layer and the dielectric layer. Accordingly, when the integrated circuit structure is used in a rectification circuit, the size of an entire circuit can be reduced.

Abstract: A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.

Abstract: A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.

Abstract: A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

Abstract: A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

Abstract: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.

Abstract: A method for micro-machining a varactor that is part of a membrane suspended MEMS tunable filter. In one non-limiting embodiment, the method includes providing a main substrate; depositing a membrane on the main substrate; depositing and patterning a plurality of sacrificial photoresist layers at predetermined times during the fabrication of the varactor; depositing metal layers that define a fabricated varactor structure enclosed within photoresist; coupling a carrier substrate to the fabricated structure opposite to the main substrate using a release layer; etching a central portion of the main substrate to expose the membrane; removing the carrier substrate by dissolving the release layer in a material that attacks the release layer but does not dissolve the photoresist; and removing the photoresist layers to provide a released varactor.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: An improved solution for performing switching, routing, power limiting, and/or the like in a circuit, such as a radio frequency (RF) circuit, is provided. A semiconductor device that includes at least two electrodes, each of which forms a capacitor, such as a voltage-controlled variable capacitor, with a semiconductor channel of the device is used to perform the desired functionality in the RF circuit. The device includes electrodes that can provide high power RF functionality without the use of ohmic contacts or requiring annealing.

Abstract: A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage.

Abstract: A diode structure fabrication method. In a P? substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N? layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.

Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.

Abstract: Disclosed is a varactor and/or variable capacitor. The varactor/variable capacitor includes a plurality of first conductive-type wells vertically formed on a substrate, a plurality of second conductive-type ion implantation areas formed in the first conductive-type wells, at least one second conductive-type plug electrically connected to the second conductive-type ion implantation areas, an isolation layer formed at sides of an uppermost second conductive-type ion implantation area, and a first conductive-type ion implantation area in an uppermost first conductive-type well electrically disconnected from the uppermost second conductive-type ion implantation area by the isolation area.

Abstract: The semiconductor variable capacitor includes a capacitor including an n-well 16 formed in a first region of a semiconductor substrate 10, an insulating film 18 formed over the semiconductor substrate 10 and a gate electrode 20n formed above the n-well 16 with the insulating film 18 interposed therebetween; and a p-well 14 of a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate 10. The gate electrode 20n has an end which is extended to the second region and formed above the p-well 14 with the insulating film 18 interposed therebetween.

Abstract: Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

Abstract: A two-terminal capacitive circuit element 100 includes a MOS transistor including a source 126 and drain 127 separated by a body region 131, and a gate 105 separated from the body 129 by a gate insulator layer 110, and a bypass capacitor 125. The gate node (port2; 115) is AC grounded through the bypass capacitor 125 and the source 126 and drain 127 are tied together (port-1; 120). By toggling the transistor on and off using an appropriate gate to body voltage, the capacitance of the capacitive circuit element 100 between port-1 and port-2 significantly changes.

Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.

Abstract: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.

Abstract: MOS varactor having an entire accumulation and depletion regime of its CV characteristic curve in one bias regime (negative or positive). The MOS varactor may comprise a gate electrode, a well region of semiconductor material having a first conductivity type (e.g., p-type), contact regions to the well region that comprise heavily doped semiconductor material of the first conductivity type (e.g., p+-type), and a Schottky junction formed between the gate and contact regions. The Schottky junction may be formed by spacing the contact regions away from the gate electrode and siliciding the substrate surface. The gate electrode may be formed from semiconductor material of a second conductivity type (e.g., n-type) opposite to the first conductivity type, thus changing the flat band voltage of the MOS varactor and shifting accumulation and depletion regime of the CV characteristic curve in one bias regime, such as the negative bias regime.

Abstract: A voltage controlled oscillator (VCO), suitable for use in a frequency shift keying (FSK) system. The VCO device comprises a switching varactor unit, having a first terminal and a second terminal, wherein the switching varactor unit produces a capacitance, according to a frequency-selection voltage. A VCO core has a first output terminal, a second output terminal complementary to the first output terminal, and an input terminal. Wherein, the switching varactor unit is coupled in parallel with the VCO core at the first output terminal and the second output terminal to produce a capacitance effect with respect to the capacitance, so as to adjust a frequency constant ?{square root over (LC)} of the VCO core.

Abstract: A junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the first ion diffusion region serving as an anode of the junction varactor; and a second ion diffusion region with a second conductivity type located in the ion well at the other side of the gate finger, the second ion diffusion region serving as a cathode of the junction varactor. In operation, the gate of the junction varactor is biased to a gate voltage VG that is not equal to 0 volt.

Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.

Abstract: A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.

Abstract: A metal oxide semiconductor varactor may be formed with HALO implants regions having an opposite polarity from the polarity of the well of the varactor. The HALO implant regions can be angled away from the source and drain. The HALO implant regions can stop the depletion from continuing as the bias voltage applied to the gate continues to increase. Stopping that depletion can create a constant capacitance when the varactor is in a depletion bias.

Abstract: An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that the first conductive layer is electrically connected to the N-type semiconductor and the P-type semiconductor; a dielectric layer laminated on an upper surface of the first conductive layer; and a second conductive layer laminated on an upper surface of the dielectric layer so that the second conductive layer forms a capacitor together with the first conductive layer and the dielectric layer. Accordingly, when the integrated circuit structure is used in a rectification circuit, the size of an entire circuit can be reduced.

Abstract: A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

Abstract: Apparatus and method of providing a CMOS varactor device having improved linearity. At least two differential varactor elements are connected in parallel. Each of the differential elements includes first, second and third doped regions in a well. A first gate controls the first and second regions and a second gate controls the second and third regions. A resistor is formed such that power applied to the bulk region of the two differential elements will differ by the voltage drop across the resistor.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: A method of making a variable capacitor by forming a grove portion in an insulating substrate, two upper portions of the substrate located on either side of the groove portion forming two lateral edges, a conductive layer covering the inside of the groove portion, a flexible conductive membrane, placed above the groove portion by bearing on the edges, a dielectric layer covering the conductive layer or the membrane to insulate the conductive layer and the membrane, and terminals of application of a voltage between the conductive layer and the membrane, and such that the depth of the groove portion continuously increases from one of the edges to the bottom of the groove portion, and that the conductive layer covers the inside of the groove portion at least to reach one of the two edges, that it may cover.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to electrically isolate the N type semiconductor layer. The metal layer which is located above the N type semiconductor layer and which forms a wire or a bonding pad is isolated from the N type semiconductor layer in which a diffusion layer or the like has been formed by an insulating film. An N type buried diffusion layer having an impurity concentration higher than that of the N type semiconductor layer is provided between the P type semiconductor substrate and the N type semiconductor layer. In addition, a P type semiconductor layer is formed by means of diffusion between the insulating film and the N type semiconductor layer plus the element isolation layer.

Abstract: A varactor has a plurality of alternating P? wells and N+ regions formed in a silicon layer. Each of the P? wells forms a first N+/P? junction with the N+ region on one of its side and a second N+/P? junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P? wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.

Abstract: A micro-electro mechanical system (MEMS) variable capacitor (varactor) generally includes a substrate (102), a first capacitive plate (112) formed on the substrate, a flexible structure (150) coupled to the substrate, a second capacitive plate (116) and a first electrode (122) formed on the flexible structure; a package seal (104) coupled to the substrate and having a second electrode (106) formed thereon, wherein the distance between the first capacitive plate and the second capacitive plate (and hence, the capacitance of the structure) is responsive to a bias voltage applied to the electrodes.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (10; 10, 41); forming a buried n+-doped region (31) in the substrate; forming in the substrate an n-doped region (41) above the buried n+-doped region (31); forming field isolation (81) around the n-doped region (41); multiple ion implanting the n-doped region (41); forming a p+-doped region (151) on the n-doped region (41); forming an n+-doped contact region to the buried n+-doped region (31), the contact region being separated from the n-doped region (41); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (41); the formation of the p+-doped region (151); and the heat treatment are performed to obtain a hyper-abrupt p+/n-junction within the n-doped region (41).

Abstract: A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and tuning range. A second, deeper base implant is used to improve the quality factor of the device by reducing the base resistance. The varactor includes a third terminal (collector), which isolates the emitter-base junction from the substrate, providing flexibility in circuit applications. A method for fabricating a high performance varactor having the above-described structure is also provided.

Abstract: A method of forming a variable contact structure, and the structure so formed, comprising forming a via within the device, wherein a diameter of the via is variably determined depending upon the number of wires to be contacted.

Abstract: A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.

Abstract: A semiconductor structure for high frequency operation has a substrate with a doped well formed therein and a buffer layer made of a substrate material covers the well. The buffer layer is made of an undoped material and is disposed on a top side of the well for inhibiting an outdiffusion of a dopant from the well. At least a portion of the substrate is not covered by the buffer layer.