Deposited Thin Film Resistor Patents (Class 438/384)
  • Patent number: 9679844
    Abstract: In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 13, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Yaojian Leng, Justin Hiroki Sato
  • Patent number: 9368565
    Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 14, 2016
    Assignee: SHANGHAI IC R & D CENTER CO., LTD.
    Inventors: Qingyun Zuo, Xiaoxu Kang, Shaohai Zeng
  • Patent number: 9328416
    Abstract: Methods for depositing film on substrates are described. In various cases, a high thermal conductivity gas such as helium is used to deposit a conditioning layer on surfaces of the reaction chamber before it is used to process substrates. The helium may be used to help atomize/vaporize a liquid reactant in a heated injection module before the reactant is delivered to the reaction chamber. In some embodiments, a purge gas including helium is used during a post-deposition purge during deposition on substrates. The disclosed embodiments allow for mixed recipe processing without having to clean the reaction chamber between recipes, and without forming a high number of particles/defects on the substrates. This allows for an improved throughput of high quality film, even where mixed recipes are used in a single reaction chamber.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 3, 2016
    Assignee: Lam Research Corporation
    Inventors: Arul N. Dhas, Akhil Singhal, Ming Li, Kareem Boumatar
  • Patent number: 9312483
    Abstract: A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: April 12, 2016
    Assignee: CROSSBAR, INC.
    Inventor: Steven Patrick Maxwell
  • Patent number: 9263457
    Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Viraj Y. Sardesai, Robert C. Wong
  • Patent number: 9236426
    Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: January 12, 2016
    Assignee: SK Hynix Inc.
    Inventor: Dong Kee Lee
  • Patent number: 9130052
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode over a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate, a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, and etch stop layers including metal silicide and formed over the pipe connection gate electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Patent number: 9130053
    Abstract: This technology relates to a nonvolatile memory device and a method of fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a bottom buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular to the substrate, and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers, wherein the pipe connection gate electrode includes a metal silicide layer formed within the groove. The electric resistance of the pipe connection gate electrode may be greatly reduced without an increase in a substantial height by forming the metal silicide layer buried in the substrate under the pipe connection gate electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Jin-Hae Choi, Joo-Hee Han, Sung-Jin Whang, Byung-Ho Lee
  • Patent number: 9087791
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The device includes first and second line pattern units configured to extend substantially parallel to one another in a first direction and alternately disposed such that end portions of the first and second line pattern units are arranged in a diagonal direction, third and fourth pattern units configured to respectively extend from the end portions of the first and second line pattern units in a second direction crossing the first direction, first contact pad units respectively formed in the third line pattern units disposed a first distance from the end portions of the first line pattern units, and fourth contact pad units respectively formed in the fourth line pattern units disposed a second distance from the end portions of the second line pattern units. Here, the second distance is different from the first distance.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: July 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Duk Sun Han
  • Patent number: 9070579
    Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 30, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Kota V. R. M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Publication number: 20150132902
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 14, 2015
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 9029180
    Abstract: A method of producing a temperature sensing device is provided. The method includes forming at least one silicon layer and at least one electrode or contact to define a thermistor structure. At least the silicon layer is formed by printing, and at least one of the silicon layer and the electrode or contact is supported by a substrate during printing thereof. Preferably, the electrodes or contacts are formed by printing, using an ink comprising silicon particles having a size in the range 10 nanometers to 100 micrometers, and a liquid vehicle composed of a binder and a suitable solvent. In some embodiments the substrate is an object the temperature of which is to be measured. Instead, the substrate may be a template, may be sacrificial, or may be a flexible or rigid material. Various device geometries are disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 12, 2015
    Assignee: PST Sensors (Proprietary) Limited
    Inventors: David Thomas Britton, Margit Harting
  • Publication number: 20150108607
    Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Yu CHEN, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
  • Patent number: 9006026
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 14, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Zhendong Hong, Vidyut Gopal, Imran Hashim, Randall J. Higuchi, Tim Minvielle, Hieu Pham, Takeshi Yamaguchi
  • Publication number: 20150069574
    Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Tai TSENG, Ming-Chyi LIU, Chung-Yen CHOU, Chia-Shiung TSAI
  • Patent number: 8940612
    Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Kamel Benaissa
  • Patent number: 8921946
    Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Publication number: 20140357047
    Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.
    Type: Application
    Filed: August 13, 2014
    Publication date: December 4, 2014
    Inventors: Jun KAWAHARA, Naoya INOUE, Naoya FURUTAKE, Yoshihiro HAYASHI
  • Patent number: 8883655
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 11, 2014
    Assignees: Intermoecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik
  • Patent number: 8878152
    Abstract: A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: November 4, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Dipankar Pramanik
  • Patent number: 8871603
    Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: October 28, 2014
    Assignees: Texas Instruments Deutschland GmbH, Texas Instruments Incorporated
    Inventors: Christoph Andreas Othmar Dirnecker, Leif Christian Olsen
  • Patent number: 8859386
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
  • Patent number: 8853044
    Abstract: A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 8846443
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 30, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Zhendong Hong, Hieu Pham, Randall Higuchi, Vidyut Gopal, Imran Hashim, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140264753
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Application
    Filed: July 5, 2013
    Publication date: September 18, 2014
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
  • Publication number: 20140273395
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Do-Hyung KIM, Eun-Tae KIM, Sung-Lae CHO
  • Publication number: 20140239449
    Abstract: An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Christoph Dirnecker, Karsten Spinger, Franz Stingl
  • Patent number: 8796104
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first insulation layer on or over a semiconductor substrate, metal patterns on or over the first insulation layer, a thin film resistor pattern disposed on or over the metal patterns, and an anti-reflection layer between the thin film resistor pattern and the metal patterns.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Chang Eun Lee
  • Patent number: 8772121
    Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Man Hwang, Jun-Soo Bae, Sung-Un Kwon, Kwang-Ho Park
  • Patent number: 8765568
    Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph M. Lukaitis, Deborah M. Massey, Timothy D. Sullivan, Ping-Chuan Wang, Kimball M. Watson
  • Patent number: 8759189
    Abstract: A reprocessing method of a semiconductor device, the reprocessing method includes adjusting a resistance value of a first resistor by first trimming the first resistor, wherein the first resistor is electrically connected between a first pad and a second pad, forming a second resistor on the first trimmed first resistor, and adjusting a resistance value of the second resistor by second trimming the second resistor.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-San Jung
  • Patent number: 8748988
    Abstract: A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yuichiro Kitajima
  • Patent number: 8709882
    Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: April 29, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Publication number: 20140113429
    Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Jin KANG, Youngnam HWANG
  • Patent number: 8703548
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 22, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye
  • Publication number: 20140103489
    Abstract: An electronic device comprising a semiconductor structure having an integrated circuit back end capacitor and an integrated circuit back end thin film resistor and a method of manufacturing the same is provided. The semiconductor structure comprises a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. Furthermore, there is a second dielectric layer which is disposed on the bottom plate of the capacitor and on top of the thin film resistor body. A top plate of the capacitor is disposed on the second dielectric layer in a region of the second dielectric layer which is defined by the lateral dimensions of the bottom plate of the capacitor. The bottom plate and the resistor body are laterally spaced apart layers which are both disposed on the first dielectric layer and which are composed of a same thin film material.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Christoph DIRNECKER, Berthold STAUFER
  • Patent number: 8685827
    Abstract: A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion on the substrate, the resistor portion including a third gate oxide layer and a third polysilicon layer on the third gate oxide layer, covering the resistor portion with a photoresist, removing respective first portions of the first and second polysilicon layers from the first and second gate stack portions, removing the photoresist from the resistor portion, and after removing the photoresist from the resistor portion, removing respective remaining portions of the first and second polysilicon layers from the first and second gate stack portions.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ju Youn Kim, Jedon Kim
  • Patent number: 8679932
    Abstract: A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the trench. A thin film resistor protection layer is then deposited to fill the trench. Then a chemical mechanical polishing process removes excess portions of the thin film resistor layer and the thin film resistor protection layer. An interconnect metal is then deposited and patterned to create an opening over the trench. A central portion of the thin film resistor protection material is removed down to the thin film resistor layer at the bottom of the trench. The resulting structure is immune to the effects of topography on the critical dimensions (CDs) of the thin film resistor.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: March 25, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Rodney Hill
  • Patent number: 8673727
    Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 18, 2014
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Yang-Shun Fan
  • Patent number: 8659085
    Abstract: The present disclosure is directed to an integrated circuit having a substrate and a first and a second interconnect structure over the substrate. Each interconnect structure has a first conductive layer over the substrate and a second conductive layer over the first conductive layer. The integrated circuit also includes a thin film resistor over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: February 25, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Hui Chong Vince Ng, Olivier Le Neel, Calvin Leung
  • Patent number: 8659122
    Abstract: To provide a semiconductor device having a structure free from variations in resistance even when a stress is applied thereto; and a manufacturing method of the device. The semiconductor device has a metal resistor layer in a region between a passivation film and an uppermost level aluminum interconnect. This makes it possible to realize a high-precision resistor having few variations in resistance due to a mold stress that occurs in a packaging step or thereafter and therefore, makes it possible to form a high-precision analog circuit.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Akira Matsumura
  • Patent number: 8652922
    Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph M. Lukaitis, Jed H. Rankin, Robert R. Robison, Dustin K. Slisher, Timothy D. Sullivan
  • Patent number: 8642439
    Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
  • Publication number: 20130341759
    Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 26, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, John Paul Campbell, Neal Thomas Murphy
  • Patent number: 8603886
    Abstract: A method for fabricating an epitaxial structure includes: (a) forming over a temporary substrate a patterned sacrificial layer that partially exposes the temporary substrate; (b) growing laterally and epitaxially a temporary epitaxial film over the patterned sacrificial layer and the temporary substrate; (c) forming over the temporary epitaxial film an etching-stop layer; (d) forming an epitaxial layer unit over the etching-stop layer; (e) removing the patterned sacrificial layer using a first etchant; and (f) removing the temporary epitaxial film using a second etchant.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 10, 2013
    Assignee: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Tsung-Yen Tsai
  • Patent number: 8597979
    Abstract: Three dimensional Panel-Level Packaging (3D-PLP) fabrication techniques for mass-production of small, simple three dimensional electronic component packages or units such as a DC-DC Converters are described where each package or unit consists of at least an active semiconductor die and a passive, two-terminal electrical circuit element (capacitor inductor and/or resistor).
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: December 3, 2013
    Inventor: Lajos Burgyan
  • Patent number: 8586443
    Abstract: A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: November 19, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jang Uk Lee
  • Patent number: 8581364
    Abstract: Provided are resistance memory devices and methods of forming the same. The resistance memory devices include a first electrode and a second electrode on a substrate, a transition metal oxide layer interposed between the first electrode and the second electrode, an electrolyte layer interposed between the second electrode and the transition metal oxide layer, and conductive bridges having one end that is electrically connected to the second electrode on the electrolyte.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: KyungTae Nam, Ingyu Baek
  • Patent number: 8581225
    Abstract: A manufacturing method includes forming, on a substrate, lower layer copper lines each being shaped into a strip, forming electrode seed layers each being shaped into a strip, on the respective lower layer copper lines using electroless plating, forming an interlayer insulating layer above the electrode seed layers, forming, in the interlayer insulating layer, memory cell holes, penetrating through the interlayer insulating layer and extending to the electrode seed layers, forming noble metal electrode layers on the electrode seed layers exposed in the respective memory cell holes using the electroless plating, forming, in the respective memory cell holes, variable resistance layers connected to the noble electrode layers, and forming, above the interlayer insulating layer and the variable resistance layers, upper layer copper lines each being shaped into a strip, connected to a corresponding one of the variable resistance layers, and crossing the lower layer copper lines.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Atsushi Himeno, Haruyuki Sorada, Takumi Mikawa
  • Patent number: 8563336
    Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, John C. Malinowski, Anthony K. Stamper