Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A method for forming a resistor includes causing a semiconductor layer to have a first resistance, forming a first mask on the semiconductor layer, causing portions of the semiconductor layer left exposed by the first mask to have a second resistance that is lower than the first resistance, forming a second mask on the first mask and on the semiconductor layer, removing portions of the first mask and the semiconductor layer left exposed by the second mask, removing the second mask, and causing portions of the semiconductor layer exposed by the removing of the second mask to have a third resistance that is lower than the second resistance. Because a resistor formed by such a process can include an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value.

Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.

Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.

Abstract: In one embodiment, an integrated circuit includes a thin film resistor, which includes a resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the resistor material having an initial width determined by a width of the channel. The stencil structure has been adapted to receive a planarizing material that protects against reduction of the initial width of the resistor material during subsequent process steps for removing the stencil structure. A head mask overlays an end portion of the thin film resistor and a dielectric overlays the head mask, the dielectric defining a via formed in the dielectric above a portion of the head mask. A conductive material has been deposited in the via, coupled to the portion of the head mask and electrically connecting the thin film resistor to other components of the integrated circuit.

Abstract: A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substrate; implanting dopant ions into the exposed vertical surfaces of the at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into the exposed vertical surfaces of the at least one semiconductor body without saturation; and forming contacts to the at least one semiconductor body. The present invention is directed to a Fin structure which includes a resistor present within the thin vertically oriented semiconductor body.

Abstract: The present invention relates to a method for forming a non-salicide p+ polysilicon resistor used to replace a N-well resistor. In the low power SRAM process whose window is lower than 0.15 &mgr;m, it is found that non-salicide p+ polysilicon resistor has minor temperature dependence and also has layout benefit. In addition, the non-salicide p+ polysilicon resistor is decreased at high temperature. Therefore, it is good benefit to reduce the RC timing delay, which would compensate the inherent MOS mobility deceleration at high temperature, when the non-salicide p+ polysilicon resistor of the present invention is used to replace the N-well resistor.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.

Abstract: A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.

Abstract: A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be applied to the fabrication of an adjustable resistor or a MOS transistor having an adjustable threshold.

Abstract: A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross-point is formed between the bottom word line and the bit line and a second cross-point is formed between the bit line and the top word line. A resistive memory material is provided at each cross-point above and below the bit line. A diode is formed at each cross-point between the resistive memory material and either the top word line or the bottom word line, respectively.

Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.

Abstract: Within both a micro fabrication and a method for fabricating the micro fabrication there is formed over a substrate a spirally patterned conductor layer spirally topographically tapered in a vortex shape. The spirally patterned conductor layer is particularly useful as a microelectronic inductor structure within a microelectronic fabrication.

Abstract: A shared bit line cross point memory array structure is provided, along with methods of manufacture and use. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross point is formed between the bottom word line and the bit line and a second cross point is formed between the bit line and the top word line. A material having a property, for example resistance, that can be changed in response to an input voltage is provided at each cross point above and below the bit line.

Abstract: A method of trimming for a semiconductor device comprising bolometers arranged in two-dimensional form corresponding to pixels for converting incoming infrared rays into electrical signals includes vertical switches, a vertical shift register, horizontal switches, and a horizontal shift register as means for selecting an arbitrary pixel. The semiconductor device is configured to allow an overcurrent to be supplied to a bolometer in a pixel selected by those means.

Abstract: A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.

Abstract: An apparatus and method for conditioning polysilicon circuit elements includes a supply source configured to impress a desired voltage or current upon a polysilicon circuit element including at least a polysilicon resistor for a desired signal duration. The desired voltage or current and signal duration are chosen to cause an irreversible decrease in the resistance of the polysilicon circuit element without generating enough heat to re-alloy the resistor contacts or fuse open the resistor. The process of the present invention may be selectively performed on desired ones of a number of polysilicon resistors forming an array or matrix to thereby program the array or matrix with a desired binary code. Alternatively, the process may be used to pre-condition all the resistors in an array or matrix to thereby facilitate subsequent programming thereof via conventional fusing techniques.

Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: An integrated resistor includes a resistor body region and a resistor contact region that is aligned with the body region. Because the resistor includes an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value. A method for forming such a resistor is also disclosed.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. An optical waveguide is formed in a monocrystalline layer grown on the semiconductor structure for distributing an optical signal to a selected portion of circuitry formed in the semiconductor structure. An optical source is formed in the semiconductor structure and coupled to the optical waveguide for generating the optical signal.

Abstract: A shared bit line cross point memory array structure is provided, along with methods of manufacture and use. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross point is formed between the bottom word line and the bit line and a second cross point is formed between the bit line and the top word line. A material having a property, for example resistance, that can be changed in response to an input voltage is provided at each cross point above and below the bit line.

Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: A resistor element has a ceramic body with a first outer electrode and a second outer electrode formed on its mutually opposite externally facing end surfaces and a plurality of mutually oppositely facing pairs of inner electrodes inside the ceramic body. Each of these pairs has a first inner electrode extending horizontally from the first outer electrode and a second inner electrode extending horizontally from the second outer electrode towards the first outer electrode and having a front end opposite and separated from the first inner electrode by a gap of a specified width, these plurality of pairs forming layers in a vertical direction. The gap of at least one of these plurality of pairs of inner electrodes is horizontally displaced from but overlapping with the gaps between the other pairs of inner electrodes. For producing such a resistor element, the distance of displacement is set according to a given target resistance value intended to be had by the resistor element.

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A semiconductor device comprising bolometers arranged in two-dimensional form corresponding to pixels for converting incoming infrared rays into electrical signals includes vertical switches, a vertical shift register, horizontal switches, and a horizontal shift register as means for selecting an arbitrary pixel. The semiconductor device is configured to allow an overcurrent to be supplied to a bolometer in a pixel selected by those means.

Abstract: A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor.

Abstract: In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate without doping the layer over the field oxide. A photoresist layer can be used as a barrier to implant doping, for example, to block N+ doping over the field oxide region. The entire layer is then doped, for example, with P type dopant after removal of the doping barrier. The second doping results in formation of a high resistivity resistor over the field oxide region, without affecting the transistor gate. Contact regions are then formed of a silicide, for example, for connecting the resistor to other devices.

Abstract: An integrated resistor includes a resistor body region and a resistor contact region that is aligned with the body region. Because the resistor includes an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value. A method for forming such a resistor is also disclosed.

Abstract: The present invention comprises an improved method of forming the source voltage lines, connection lines, and high load resistors for use in HLR SRAM devices. The source voltage lines, connection lines, and high load resistors are formed from a single polysilicon film that is selectively silicided to produce the low resistance structures while preserving the as-deposited polysilicon resistivity for formation of the high load resistor. The improved resistance control allows reduced feature size and increased pattern density.

Abstract: A thin film resistor fabrication method requires that an IC's active devices be fabricated on a substrate, and a dielectric layer be deposited over the devices to protect them from subsequent process steps. A layer of thin film material is deposited next, followed by a barrier layer and a first layer of metal. These three layers are patterned and etched to form isolated material stacks wherever a TFR is to be located, and a first level of metal interconnections. The first metal layer is removed from the TFR stacks, and the barrier layer is patterned and etched to provide respective openings which define the active areas of each TFR. In a preferred embodiment, a dielectric layer is deposited after the first metal layer is removed, to protect the interconnect metal from corrosion and as an adhesion layer for the patterning of the openings which define resistor length.

Abstract: A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

Abstract: A semiconductor fabrication method is provided for fabricating a resistor and a capacitor electrode in an integrated circuit, which can help enhance the quality of the resultant integrated circuit. In this method, the first step is to form a polysilicon layer. Then, optionally, a first oxide layer is formed over the polysilicon layer. Next, a first ion-implantation process is performed on the entire polysilicon layer so as to convert it into a lightly-doped polysilicon layer with a first predefined impurity concentration. After this, a second ion-implantation process is performed solely on the predefined electrode part of the polysilicon layer so as to convert this part into a heavily-doped polysilicon layer with a second predefined impurity concentration higher than the first impurity concentration. Subsequently, a selective removal process is performed to remove selected parts of the lightly-doped part and the heavily-doped part of the polysilicon layer.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: An aluminum wire is connected to a P-type layer of a polydiode element through a resistive element consisting of a barrier metal film and a tungsten plug. Another aluminum wire is connected to an N-type layer of the polydiode element through another resistive element consisting of another barrier metal film and another tungsten plug. Thus, a semiconductor device including a polydiode element which is resistant to surge or contamination is provided.

Abstract: The invention provides a method for forming a thin film resistor, which comprises the following steps: providing an insulator substrate; forming a patterned conductive layer over the insulator substrate by a non-photolithographic method; forming a thin film resistive layer on the patterned conductive layer and the insulator substrate; patterning the thin film resistive layer by photolithography. Using the method for forming a thin film resistor in accordance with the invention, the fabrication costs of the thin film resistor can be lowered.

Abstract: A method for stabilizing thin film structures fabricated on an I.C. wafer requires the performance of a rapid thermal annealing (RTA) step after the thin film material, preferably silicon-chromium (SiCr) or silicon chromium carbide (SiCrC), is sputtered onto the wafer. The RTA step stabilizes the TF and thereby increases the film's integrity. With the TF structures stabilized, the effect of subsequent high temperature process steps on the film is reduced. The stabilization method enables TF resistors thereby formed to attain a higher degree of accuracy, and thus to improve the ability with which resistors can be matched. Resistor TCR and sheet rho consistency are also improved, both within a given wafer and from wafer to wafer.

Abstract: A method of modifying a layer of thin film composite material to achieve one or more desired properties for the thin film layer which cannot be achieved by heat treatment at all practical temperatures of operation allowable by particular integrated circuit processes. In particular, the thin film composite material is subjected to an ion implantation process. Depending on the doping species, the doping concentration, the doping energy, and other ion implantation parameters, one or more properties of the deposited thin film resistive layer can be modified. Such properties may include electrical, optical, thermal and physical properties. For instance, the sheet resistance and/or the temperature coefficient of resistance of the thin film composite material may be increased or decreased by appropriately implanting ions into the material. The ion implantation can be applied globally in order to modify one or more properties of the entire deposited thin film composite layer.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate. A semiconductor film pattern is formed on the insulating film. A direct thermal nitriding method is performed to at least a portion of the semiconductor film pattern. The direct thermal nitriding method is performed by lamp annealing in a gas composed of nitrogen such that a thermally nitrided film has a film thickness of equal to or thicker than 1.5 nm. Thus, invasion of a hydrogen atom or ion into the semiconductor film pattern can be prevented.

Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

Abstract: A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor.

Abstract: A semiconductor fabrication method is provided for fabricating a resistor and a capacitor electrode in an integrated circuit, which can help enhance the quality of the resultant integrated circuit. In this method, the first step is to form a polysilicon layer. Then, optionally, a first oxide layer is formed over the polysilicon layer. Next, a first ion-implantation process is performed on the entire polysilicon layer so as to convert it into a lightly-doped polysilicon layer with a first predefined impurity concentration. After this, a second ion-implantation process is performed solely on the predefined electrode part of the polysilicon layer so as to convert this part into a heavily-doped polysilicon layer with a second predefined impurity concentration higher than the first impurity concentration. Subsequently, a selective removal process is performed to remove selected parts of the lightly-doped part and the heavily-doped part of the polysilicon layer.

Abstract: A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total thickness of the dielectric stack (60) between the silicon substrate and the top of the dielectric stack just prior to the formation of the thin film resistor (80). Then, the thickness of the dielectric stack (60) is adjusted (60+70) to be an odd integer number of laser quarter wavelengths. The thin film resistor (60) is then formed and overlying dielectric (120) is deposited. The thickness of the overlying dielectric (120) may likewise be adjusted (120+130) to be an odd integer number of laser quarter wavelengths.

Abstract: A polysilicon resistor is formed using a late implant process. Low dopant concentrations on the order of 6×1019 to 3.75×1020 have shown good results. with a reduced post anneal temperature. Both the first and second order temperature coefficients (TC1 and TC2) can then be adjusted. Using electrical trimming resistors can be produced with highly linear temperature characteristics. By varying the geometries of the resistors, low trimming threshold current densities and voltages can be used to produce good results.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.