Abstract: A method of fabricating a trench capacitor of a memory cell, includes providing a semiconductor substrate with a surface covered by a pad layer, forming a trench in the substrate, forming a first layer on the pad layer and on the surface of the trench, removing a portion of the first layer to form a residual first insulating layer, forming a first conductive layer on the residual first layer, removing a portion of the first conductive layer, removing a portion of the residual first layer, driving out charged elements from the first layer into the semiconductor substrate, to form a first doped substrate region, removing the first layer, forming a node nitride on the trench, forming a second conductive layer on the pad layer and on the trench, removing a portion of the second conductive layer to form a second doped substrate region in the trench.

Abstract: A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench. A mask layer is formed on the substrate, wherein the mask layercovers the periphery of the undoped semiconductor layer that is adjacent to the neighboring region, pre-defined for the active region of the deep trench. An ion implantation process is performed to implant dopants into the undoped semiconductor layer exposed by the mask layer so as to form a second conductive layer. The first and the second conductive layers constitute the upper electrode of the deep trench capacitor.

Abstract: A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combination of oxide and polysilicon are used to fabricate a composite trench fill. The trench bottom and a lower portion of the walls are covered with oxide. The remaining portion of the trench volume is filled with polysilicon. The method may be used for junction field effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

Abstract: A method for increasing the capacitance of deep trench capacitors. The method includes providing a substrate, forming a pad structure on the substrate, forming a photoresist defining the region of the deep trench on the pad structure, forming a deep trench in the substrate, removing the photoresist, forming a capacitor in the lower portion of the deep trench, forming a first insulation layer on the capacitor, forming an epitaxy layer on the sidewall of the deep trench above the first insulation layer as a liner to narrow the dimension of the deep trench, and removing the first insulation layer uncovered by the epitaxy layer.

Abstract: A trench capacitor includes an electrode having a first conductive area formed in a trench provided in a substrate, and a second conductive area extending from a bottom of the trench, the second conductive area being electrically coupled to the first conductive area and spaced apart from the first conductive area; a storage node having a first conductive extension extending into a first dielectric space provided between the first conductive area and the second conductive area of the electrode, and a second conductive extension extending into a second dielectric space provided within the second conductive area of the electrode; and a dielectric layer electrically insulating the electrode from the storage node.

Abstract: The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.

Abstract: A high temperature thermal annealing process creates a low resistance contact between a metal material and an organic material of an organic semiconductor device, which improves the efficiency of carrier injection. The process forms ohmic contacts and Schottky contacts. Additionally, the process may cause metal ions or atoms to migrate or diffuse into the organic material, cause the organic material to crystallize, or both. The resulting organic semiconductor device has enhanced operating characteristics such as faster speeds of operation. Instead of using heat, the process may use other forms of energy, such as voltage, current, electromagnetic radiation energy for localized heating, infrared energy and ultraviolet energy. An example enhanced organic diode comprising aluminum, carbon C60, and copper is described, as well as example insulated gate field effect transistors.

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

Abstract: A capacitive structure including single crystal silicon and an insulating layer in a semiconductor substrate. One embodiment of the present invention includes an optical switching device having one or more capacitive structures including single crystal silicon in a substrate such as a silicon-on-insulator (SOI) wafer and can be used in a variety of high bandwidth applications including multi-processor, telecommunications, networking or the like. In one embodiment, a capacitive structure includes single crystal silicon disposed in a first semiconductor material with an insulating layer disposed between the single crystal silicon and the semiconductor material. In one embodiment, a capacitive structure may be formed by laterally growing single crystal silicon through an opening in a trench adjacent to a trench where the capacitive structures is formed.

Abstract: A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Abstract: A damascene capacitor structure includes a recessed capacitor plate for preventing leakage and dielectric breakdown between the capacitor plates of the capacitor structure on the surface of the trenches and in the bottom corners of the trenches.

Abstract: The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust GC to vertical gate contact in all alignment scenarios. The conductive vertical gate contact of the present invention, in conjunction with any DT top isolation approach, allows for an aggressive post GC etch treatment to avoid gate to bit line shorts without compromising the contact between the GC and the vertical gate.

Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench.

Abstract: The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

Abstract: The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas.

Abstract: A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a buried insulating collar due to the widened trench. The insulating collar is removed in the vicinity of the surface of the substrate, through which the substrate is exposed in this region. Here, a selective epitaxial layer is subsequently grown in the trench, through which a subsequently formed selection transistor can be formed in perpendicular fashion over the trench, or very close to the trench. In addition, through the widened trench the electrode surface of the capacitor electrodes is enlarged, which ensures an increased storage capacity.

Abstract: A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is etched, another epitaxial film is formed on the substrate and in the trench. Accordingly, the trench can be filled with the epitaxial films completely. Then, the surface of the substrate is flattened.

Abstract: The present invention is directed to a method for manufacturing a substrate especially for SOI technologies. The new method includes the steps of: a) providing a semiconductor wafer having a front side where active devices ate to be located or are located and a back side opposite the front side; b) producing at least one trench in the back side of the wafer, the trench extending from the back side of the wafer to a level having a predetermined distance from the front side of the wafer; and c) producing an insulation structure in the trench so that vertical insulation for active devices located on the front side of the wafer is provided.

Abstract: A semiconductor device (10) has a substrate (20) with a surface (26) for defining a trench (34). A control electrode (45) is disposed at the surface to activate a conduction path (50) along a sidewall (36) of the trench with a control signal (VGATE). A dielectric layer (32, 35) is formed between the sidewall and the control electrode to have a first width (WGS) adjacent to the surface and a second width (WGC) smaller than the first width adjacent to the conduction path.

Abstract: The present invention includes a method of forming a capacitor on a semiconductor support wafer. The method comprises forming a diffusion area in the support wafer to provide a first electrode and a second electrode of the capacitor, implanting a first gas in the diffusion area to form a dielectric layer at a predetermined depth, wherein a first region of the diffusion area is formed below the dielectric layer as the first electrode of the capacitor and a second region of the diffusion area is formed above the dielectric layer as the second electrode of the capacitor, etching a trench in the support wafer to isolate laterally the dielectric layer, growing an epitaxial layer, and implanting a second gas to isolate the epitaxial layer from the second electrode. The capacitor is formed substantially subjacent a semiconductor device formed in the epitaxial layer.

Abstract: A microroughness on a surface is produced in a single process step by forming semiconductor grains directly from a process gas. The semiconductor grains are finely distributed on the surface. As a result of forming the microroughness in a single process step, time and costs are saved during fabrication.

Abstract: A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

Abstract: A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer.

Abstract: A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.

Abstract: A high surface area capacitor comprising a double metal layer (an electrode metal and barrier material) deposited on hemispherical grain (HSG) silicon, wherein a high dielectric constant (HDC) material is deposited over the double metal layer. The high surface area capacitor is complete with an upper cell plate electrode deposited over the HDC material. The double metal layer preferably comprises one noble metal, such as platinum or palladium, for the electrode metal and an oxidizable metal, such as ruthenium, iridium, or molybdenum, for the barrier material. The noble metal, such as platinum metal, alone would normally allow oxygen to diffuse into and oxidize any adhesion layer (making the adhesion layer less conductive) and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. Thus, the barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion.

Abstract: A technique for manufacturing memory devices which can easily manufacture ROM semiconductors having various write patterns at lower cost in a short period of time is disclosed. Since a simple matrix structure in which each memory cell is formed at a cross-point of an upper and a lower linear electrode is employed, and an insulating material is selectively ejected to surfaces of electrodes at predetermined memory cell positions by using an inkjet head, the surfaces of the electrode at the predetermined memory cell positions are covered with the insulating material. A state is stored in accordance with the presence or the absence of the covering insulating film on the surface of the electrode at each memory cell position.

Abstract: A method of making finger capacitors in an integrated circuit comprises forming a plurality of conductive strips in a substrate having a first dielectric constant, removing a portion of the substrate material between the conductive strips to define a space and then filling the space with a material having a second dielectric constant which is greater than the first dielectric constant. By selecting the proportion of the high and low dielectric constant materials, the capacitance of the finger capacitors can be selected to have any value from a minimum, in which very little of the original, first dielectric constant material is removed and replaced by the second dielectric constant material, to a maximum, in which all of the first dielectric constant material between the conductive strips is removed and replaced with the second dielectric constant material.

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.

Abstract: It is possible to obtain a semiconductor device in which a contact and a wiring provided on the contact can be electrically connected well even if a shift of superposition is caused. Sidewalls 5a, 5b, 5c and 5d formed of a conductive material are bonded to side faces of wirings 4a and 4b to be provided on contacts 3a and 3b. Consequently, the wirings 4a and 4b and the contacts 3a and 3b can be electrically connected well through the sidewalls 5a, 5b, 5c and 5d.

Abstract: The present invention provides a method for making the bottom electrode of a buried capacitor, which is characterized by protecting the non-bottom electrode region with a LPD oxide layer to prevent the impurities within the doped Si glass remaining in non-bottom electrode region from driving into the substrate during annealing, thus non-desired diffusing region connecting to the bottom electrode will be generated. Consequently, the leakage current existing in conventional buried capacitor will be effectively reduced according to the method of this present invention.

Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more.

Abstract: A method of fabricating a trench cell capacitor can be used in the formation of a DRAM cell. In one embodiment, a trench is formed within a semiconductor substrate. The trench is lined with a dielectric layer, e.g., an ONO layer. After lining the trench, a collar is formed in an upper portion of the trench by forming an oxide layer in the upper portion. A nitride layer on the oxide layer. The trench is then filled with semiconductor material. For example, a semiconductor region can be epitaxially grown to fill the trench.

Abstract: A monolithic semiconductor optical detector is formed on a substrate having a plurality of substantially parallel trenches etched therein. The trenches are further formed as a plurality of alternating N-type and P-type trench regions separated by pillar regions of the substrate which operate as an I region between the N and P trench regions. First and second contacts are formed on the surface of the substrate and interconnect the N-type trench regions and the P-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.

Abstract: A high Q inductor and its forming method is disclosed. In this forming method, a semiconductor substrate is first provided with a trench formed thereon. The trench is defined by dry etching and formed to a depth of 3˜5 &mgr;m. A material having a higher resistivity than that of the semiconductor is then provided to fill the trench. The material can be formed by first depositing an epitaxy layer with a lower dopant concentration than that of the semiconductor substrate by several orders of magnitude on the semiconductor substrate, then etching back the epitaxy layer to expose the surface of the semiconductor substrate. Thereafter, a dielectric layer is formed on the semiconductor substrate and the trench, and an inductor winding is formed on the dielectric layer above the trench to form the high Q inductor.

Abstract: A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.

Abstract: A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench. An oxide is formed in the isolation trench and the capacitor trench and the oxide so selectively removed in the capacitor trench. Portions of the substrate defining the base and sidewalls of the capacitor trench are then doped and a capacitor dielectric is formed in the capacitor trench, leaving a portion of the trench unfilled. A polysilicon layer is formed it the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.

Abstract: The present invention discloses a novel multiple fin-shaped capacitor for use in semiconductor memories. The capacitor has a plurality of horizontal fins and a crown shape. The capacitor structure comprises a bottom storage electrode. The bottom storage electrode comprises of a plurality of horizontal fins and a crown shape, wherein said crown shape includes two vertical pillars, and said plurality of horizontal fins extend outside from an external surface of said crown shape. A second dielectric layer is formed on the surface of the bottom storage electrode layer. A top storage electrode layer is formed along the surface of second dielectric layer. By including horizontal fins and vertical pillars, the surface area of the capacitor is significantly increased, resulting in increased capacitance.

Abstract: A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.

Abstract: Thin-film transistors (TFTs) having characteristics comparable to those of a single-crystal silicon wafer are provided. A buffer film made from silicon oxide is formed on a first amorphous silicon film. A nickel acetate solution containing a metal element such as nickel for promoting crystallization of silicon is applied to the first amorphous silicon film. The laminate is heat-treated to form a nickel silicide layer. The nickel silicide layer is then patterned. A second amorphous silicon film is formed and heat-treated to grow crystals. Thus, monodomain regions which can be regarded as single crystals are formed. Active layers of TFTs are formed from these monodomain regions.

Abstract: Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.

Abstract: A method of providing a predetermined level and state of stress in a film deposited on a surface of a substrate. In one embodiment, a layer of crystalline material is deposited on a surface of a substrate and then a layer of amorphous material is deposited on the layer of crystalline material. Then, the layers are heated, causing the amorphous material to crystallize. Such crystallization reduces, or even changes the state of, stress in the amorphous layer, which in turn alters the forces applied by the layer to adjacent regions of the substrate. The method may be used for filling a deep-trench capacitor of the type used in trench-storage DRAMs.