Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

Abstract: The present application relates to a capacitor device and a manufacturing method thereof, and a memory. forming a first capacitor structure on a substrate, includes: a first capacitor dielectric layer, a first upper electrode, a plurality of first lower electrodes arranged at intervals; the first capacitor dielectric layer at least covers sidewalls of the first lower electrodes, and the first upper electrode fills up gaps at an outer side of the first capacitor dielectric layer; forming a second capacitor structure on the first capacitor structure, the second capacitor structure includes a second capacitor dielectric layer, a second upper electrode, and a plurality of second lower electrodes arranged at intervals; the second lower electrodes are of a U-shaped structure, bottoms of the second lower electrodes are in contact with tops of the first lower electrodes, the second capacitor dielectric layer is at least located on surfaces of the second lower electrodes.

Abstract: Methods and systems for forming high aspect ratio features on a substrate are disclosed. Exemplary methods include forming a first carbon layer within a recess, etching a portion of the first carbon layer within the recess, and forming a second carbon layer within the recess. Structures formed using the methods or systems are also disclosed.

Abstract: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Abstract: An electronic device includes one or more capacitors adjacent to a base material. The one or more capacitors comprise at least one electrode extending horizontally within the base material, and additional electrodes extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Abstract: A method of manufacturing a semiconductor device includes providing a precursor structure including a first capacitor and a second capacitor on a substrate; forming a first vertical transistor and a second vertical transistor respectively over the first capacitor and the second capacitor, in which the first vertical transistor includes a first word line having a first top width and a first bottom width smaller than the first top width, the second vertical transistor includes a second word line having a second top width and a second bottom width smaller than the second top width; and forming an air gap between the first vertical transistor and the second vertical transistor.

Abstract: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

Abstract: A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug.

Abstract: Described herein is a technique capable of forming a film whose characteristics are uniform by discharging a residual component from a plurality of grooves before supplying a process gas. According to one aspect thereof, there is provided a substrate processing apparatus including: (a) loading a substrate on which a plurality of grooves are provided into a process chamber, wherein a residue is adhered to the plurality of the grooves; (b) desorbing the residue from the plurality of the grooves by heating the substrate; and (c) discharging the residue from the plurality of the grooves to a process space of the process chamber after (b) is performed by heating a surface of the substrate to a temperature higher than a temperature of the substrate in (b).

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes.

Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

Abstract: A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.

Abstract: A microfabricated structure includes a perforated stator; a first isolation layer on a first surface of the perforated stator; a second isolation layer on a second surface of the perforated stator; a first membrane on the first isolation layer; a second membrane on the second isolation layer; and a pillar coupled between the first membrane and the second membrane, wherein the first isolation layer includes a first tapered edge portion having a common surface with the first membrane, wherein the second isolation layer includes a first tapered edge portion having a common surface with the second membrane, and wherein an endpoint of the first tapered edge portion of the first isolation layer is laterally offset with respect to an endpoint of the first tapered edge portion of the second isolation layer.

Abstract: A semiconductor device includes a substrate, a gate insulating layer on the substrate, and a stacked semiconductor layer. The stacked semiconductor layer includes a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor, a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor. The semiconductor device further includes a metal layer on or above the stacked semiconductor layer. The third layer includes less phosphorus than the first layer or does not include phosphorus.

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed.

Abstract: The present disclosure discloses a method for manufacturing a capacitor, a capacitor array structure and a semiconductor memory. The method for manufacturing a capacitor includes: providing an underlayer; forming a substrate to be etched on the underlayer; enabling a wafer to include a central area and an edge area; forming a first hard mask layer having a first pattern in the central area on the substrate to be etched; using the first hard mask layer as a mask to etch the substrate to be etched, to form capacitor holes; depositing a lower electrode layer; and sequentially forming a capacitor dielectric layer and an upper electrode layer.

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Abstract: A manufacturing method for a deep trench, the method includes forming a first trench in a substrate and performing a first cycle and a second cycle. Each comprising performing a passivation operation forming a passivation film on a sidewall and a bottom surface of the first trench, performing a first etching with a first bias power to remove the passivation film formed on the bottom surface of the first trench to expose the bottom surface of the first trench, and performing a second etching with a second bias power etching the exposed bottom surface of the first trench to form a second trench disposed below the first trench. The first bias power and the second bias power in the second cycle is greater than the first bias power and the second bias power in the first cycle, respectively.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.

Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

Abstract: The present disclosure relates to a semiconductor device with tilted insulating layers and a method for fabricating the semiconductor device with the tilted insulating layers. The semiconductor device includes a substrate, two conductive pillars positioned above the substrate and extended along a vertical axis, a first set of tilted insulating layers parallel to each other and positioned between the two conductive pillars, and a second set of tilted insulating layers parallel to each other and positioned between the two conductive pillars. The first set of tilted insulating layers are extended along a first direction slanted with respect to the vertical axis, the second set of tilted insulating layers are extended along a second direction slanted with respect to the vertical axis, and the first direction and the second direction are crossed.

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

Abstract: A semiconductor includes a semiconductor substrate and pillar type capacitors. The semiconductor substrate includes first connecting pads and second connecting pads. The second connecting pads are disposed on the first connecting pads respectively, and the pillar type capacitors are disposed on the second connecting pads respectively. A first ends of the pillar type capacitors are connected to the second connecting pads respectively, and a second ends of the pillar type capacitors area at the opposite side of the first ends. The distance between the first end and the second end of each of the pillar type capacitors is from 1 micrometer to 1.8 micrometer. A manufacturing method is also provided.

Abstract: A semiconductor substrate includes a surface having a groove. The groove includes an inner bottom surface and an inner wall surface. The inner wall surface has a depression. The depression has a depth from a direction along a surface of the inner wall surface to a width direction of the groove. The substrate being exposed to the inner wall surface.

Abstract: The present application provides a memory cell, a memory array and a method for preparing the memory cell. The memory cell includes an active area, an isolation structure and a contact enhancement layer. The active area is a surface portion of a semiconductor substrate. A top surface of the active area has a slop part descending toward an edge of the active area within a peripheral region of the active area. The isolation structure is formed in a trench of the semiconductor substrate laterally surrounding the active area. The contact enhancement layer covers the edge of the active area and in lateral contact with the isolation structure. The slope part of the top surface of the active area is covered by the contact enhancement layer, and the contact enhancement layer is formed of a semiconductor material.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

Abstract: A microfabricated structure includes a perforated stator; a first isolation layer on a first surface of the perforated stator; a second isolation layer on a second surface of the perforated stator; a first membrane on the first isolation layer; a second membrane on the second isolation layer; and a pillar coupled between the first membrane and the second membrane, wherein the first isolation layer includes a first tapered edge portion having a common surface with the first membrane, wherein the second isolation layer includes a first tapered edge portion having a common surface with the second membrane, and wherein an endpoint of the first tapered edge portion of the first isolation layer is laterally offset with respect to an endpoint of the first tapered edge portion of the second isolation layer.

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

Abstract: A method for manufacturing a semiconductor device includes forming a trench in a semiconductor wafer; and forming a first insulating film by thermally oxidizing the semiconductor wafer. The first insulating film covers an inner surface of the trench so that a first space remains in the trench. The first insulating film has a recessed portion at the bottom of the trench. The method further includes forming a semiconductor layer on the first insulating film, the semiconductor layer filling the first space and the recessed portion; forming a second space in the trench by selectively removing the semiconductor layer so that a portion of the semiconductor layer remains in the recessed portion; forming a second insulating film in the recessed portion by thermally oxidizing the portion of the semiconductor layer; and forming a first conductive body in the trench, the first conductive body filling the second space.

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate comprising a first top surface; an isolation region disposed in the substrate; an active region surrounded by the isolation region; a gate trench disposed in the active region; a first barrier layer disposed on a portion of a sidewall of the gate trench; a first gate material disposed in the gate trench, wherein the first gate material comprises a first member surrounded by the first barrier layer and a second member extending from the first member toward the first top surface; a second barrier layer disposed on the first barrier layer and the first gate material; a second gate material disposed on the second barrier layer; and a gate insulating material disposed on the second gate material.

Abstract: The present application discloses a method for preparing a semiconductor device with an air gap structure between conductive structures. The method includes: forming a first bit line, a second bit line, a first capacitor contact and a second capacitor contact over a semiconductor substrate, wherein the first capacitor contact and the second capacitor contact are disposed between the first bit line and the second bit line; forming a first dielectric layer over a sidewall of the first bit line, a sidewall of the second bit line, a sidewall of the first capacitor contact and a sidewall of the second capacitor contact such that an opening is formed and surrounded by the first dielectric layer; filling the opening with a dielectric structure; and removing the first dielectric layer to form an opening structure surrounding the dielectric structure.

Abstract: Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process at a growth temperature less than 500 degrees Celsius on the vertical or tapered surface of the trench. A physically exposed side surface of the single crystalline semiconductor liner may have a second root-mean-square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film, which may be advantageously used to reduce dark current and white pixels.

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The solid state lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: Methods, apparatuses, and systems related to semiconductor processing (e.g., of a capacitor support structure) are described. An example method includes patterning a surface of a semiconductor substrate to have a first silicate material, a nitride material over the first silicate material, and a second silicate material over the nitride material. The method further includes removing the first silicate material and the second silicate material and leaving the nitride material as a support structure for a column formed from a capacitor material. The method further includes performing supercritical drying on the column, after removal of the first and second silicate materials, to reduce a probability of the column wobbling relative to otherwise drying the column after the removal of the first and second silicate materials.

Abstract: A capacitor is disclosed, including: a semiconductor substrate including opposite upper and lower surfaces; one first trench disposed in the semiconductor substrate and formed downward from the upper surface; one second trench disposed in the substrate and corresponding to the first trench, and formed upward from the lower surface; a first conductive layer disposed above the substrate and in the first trench; a first insulating layer disposed between the substrate and the first conductive layer; a second conductive layer disposed on the substrate and in the first trench, the second conductive layer being electrically connected to the substrate; a second insulating layer disposed between the second conductive layer and the first conductive layer; a third conductive layer disposed below the substrate and in the second trench; and a third insulating layer disposed between the third conductive layer and the substrate, which is electrically connected to the first conductive layer.

Abstract: A capacitor includes a first electrode having a substrate and a plurality of nanostructures physically and electrically coupled to the substrate. The capacitor also includes a solid, non-conductive interlayer deposited over the nanostructures to coat the nanostructures, and extending between the nanostructures, and a second electrode deposited over the interlayer and extending between the nanostructures. The interlayer insulates the first and second electrode layers from one another.

Abstract: The present application discloses a method for fabricating a semiconductor device including providing a substrate, forming a growing base film above the substrate, forming a plurality of doped segments and a plurality of undoped segments in the growing base film, selectively forming a plurality of insulating segments on the plurality of undoped segments, removing the plurality of doped segments, and forming a plurality of capacitor structures above the substrate.

Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.

Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.

Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.

Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.