Trench Capacitor Patents (Class 438/386)
  • Patent number: 10879233
    Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10756163
    Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10170616
    Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
  • Patent number: 10049922
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9859157
    Abstract: A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N2) and ammonia (NH3) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 9825118
    Abstract: A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung Chen, Shu Fang Fu, Chang-Sheng Liao
  • Patent number: 9728501
    Abstract: A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9673200
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chi Kuo, Tsung-Hsien Lee, Ta-Ching Wei
  • Patent number: 9653534
    Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Michael P. Chudzik, Aritra Dasgupta, Herbert L. Ho, Donghun Kang, Rishikesh Krishnan, Vijay Narayanan, Kern Rim
  • Patent number: 9478602
    Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Seidel, Torsten Huisinga
  • Patent number: 9452926
    Abstract: A method for selectively etching a substrate is provided. In one embodiment, an epilayer is grown on top of the substrate. A resistive element may be defined and etched into the epilayer. On the other side of the substrate, the substrate is selectively etched up to the resistive element, leaving a suspended resistive element.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 27, 2016
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Robert Okojie
  • Patent number: 9343527
    Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.
    Type: Grant
    Filed: December 2, 2012
    Date of Patent: May 17, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Jiro Yugami, Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama, Yasuo Inoue, Yoshiki Yamamoto
  • Patent number: 9293382
    Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Norbert Arnold, Jin Liu, Brian W. Messenger, Oliver D. Patterson
  • Patent number: 9293520
    Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Geng Wang, Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi
  • Patent number: 9276058
    Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ho Lee, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Hee-Dong Park, Tae-Jung Park
  • Patent number: 9269760
    Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer. The method further comprises filling the first trench with a conductive material. The method additionally comprises forming a second etch stop layer over the first etch stop layer. The method also comprises forming a second dielectric layer over the second etch stop layer. The method further comprises forming a second trench to expose the conductive material. The second trench is formed having a depth less than a total thickness of the first etch stop layer, the second etch stop layer and the second dielectric layer. The method additionally comprises depositing a first metal layer over sidewalls of the second trench and in contact with the conductive material.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Pai, Kuo-Chi Tu, Wen-Chuan Chiang, Chung-Yen Chou
  • Patent number: 9263536
    Abstract: Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Gun Kim, Young-Min Ko, Kwang-Tae Hwang
  • Patent number: 9236442
    Abstract: Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 12, 2016
    Assignee: Broadcom Corporation
    Inventors: Milind S. Bhagavat, Sampath Komarapalayam Velayudham Karikalan, Rezaur Rahman Khan
  • Patent number: 9207138
    Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: December 8, 2015
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiyang He, Chenglong Zhang
  • Patent number: 9196720
    Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ?90% and ?110% of the depth of the first concave portion. The thickness of LIL2 is ?95% and ?105% of the thickness of LIL1. The UIF is thicker than the GIF.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: November 24, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoru Tokuda
  • Patent number: 9190313
    Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber, Arvind Kumar, Shom Ponoth
  • Patent number: 9184041
    Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu
  • Patent number: 9184308
    Abstract: In one embodiment, devices, such as metal-insulator-metal tunneling diodes, are fabricated by forming a cavity in a substrate having a top surface, conformally depositing a thin film of material in the cavity so as to form a thin layer of material on walls of the cavity, and depositing a layer of material to fill the cavity, wherein a top edge of the thin film is exposed and is flush with the top surface of the substrate.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: November 10, 2015
    Assignee: Univerity of South Florida
    Inventors: I-Tsang Wu, Jing Wang
  • Patent number: 9183977
    Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Menath, Thomas Fischer, Hermann Wendt
  • Patent number: 9159572
    Abstract: A method of producing a semiconductor substrate product, the method containing: a step of preparing an aqueous solution containing 7% by mass or more and 25% by mass or less of a quaternary alkyl ammonium hydroxide; a step of preparing a semiconductor substrate having a silicon film comprising a polycrystalline silicon film or an amorphous silicon film; and a step of heating the aqueous solution at 80° C. or higher and applying the resultant aqueous solution onto the semiconductor substrate to etch at least a part of the silicon film.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 13, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Masashi Enokido, Tadashi Inaba, Atsushi Mizutani
  • Patent number: 9136331
    Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew King
  • Patent number: 9093386
    Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
  • Patent number: 9076848
    Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: David H. Allen, Douglas M Dewanz, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
  • Patent number: 9070751
    Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: David H. Allen, Douglas M Dewanz, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
  • Patent number: 9059320
    Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Carl J. Radens, Ravi M. Todi, Geng Wang
  • Patent number: 9054226
    Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ho Lee, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Hee-Dong Park, Tae-Jung Park
  • Publication number: 20150145102
    Abstract: An integrated circuit structure provides at least one metal-insulator-metal (MIM) capacitor and a moat isolation structure wherein the number of processes required is substantially minimized and the formation of the MIM capacitor and the moat isolation structure effectively decouple while the number of processes common to the moat isolation structure and the MIM capacitor are maximized. Additional required processes are non-critical and tolerant of overlay positioning error.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: Thomas Walter Dyer, Herbert Lei Ho, Jin Liu
  • Publication number: 20150130024
    Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Young Kyu Song, Kyu-Pyung Hwang, Dong Wook Kim, Changhan Hobie Yun
  • Publication number: 20150118821
    Abstract: A method of forming a semiconductor device structure comprises forming a mold template comprising trenches within a mold material. Structures are formed within the trenches of the mold template. A wet removal process is performed to remove the mold template, a liquid material of the wet removal process remaining at least in spaces between adjacent pairs of the structures following the wet removal process. A polymer material is formed at least in the spaces between the adjacent pairs of the structures. At least one dry removal process is performed to remove the polymer material from at least the spaces between the adjacent pairs of the structures. Additional methods of forming a semiconductor device structure, and methods of forming capacitor structures are also described.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Dan B. Millward, J. Neil Greeley
  • Patent number: 9012295
    Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
  • Patent number: 9006703
    Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
  • Patent number: 8999783
    Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Andreas Meiser
  • Patent number: 8993396
    Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Yong-Tae Cho
  • Patent number: 8987119
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 24, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Patent number: 8987086
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Kuo-Chi Tu, Chun-Yao Chen
  • Publication number: 20150076657
    Abstract: A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Yen CHOU, Po-Ken LIN, Chia-Shiung TSAI, Xiao-Meng CHEN
  • Publication number: 20150061069
    Abstract: In one aspect, an integrated circuit (IC) includes an isolation trench dividing the IC into a first section and a second section, an active electronic device disposed in the first section of the IC and a capacitor disposed in the second section of the IC and electrically isolated from the active electronic device.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 5, 2015
    Applicant: Allegro Microsystems, LLC
    Inventors: Andreas P. Friedrich, Harianto Wong
  • Publication number: 20150061075
    Abstract: A metal trench de-coupling capacitor structure includes a vertical trench disposed in a substrate, an insulating layer deposited on the sidewall of the vertical trench, an inter-layer dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the interlayer dielectric layer to fill up the vertical trench. The metal layer is electrically connected to a power source.
    Type: Application
    Filed: August 7, 2014
    Publication date: March 5, 2015
    Inventor: Ta-Hsun Yeh
  • Patent number: 8962423
    Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Publication number: 20150041949
    Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventor: Hartmud Terletzki
  • Publication number: 20150044853
    Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
  • Patent number: 8946043
    Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
  • Patent number: 8946046
    Abstract: A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Crossbar, Inc.
    Inventor: Sung Hyun Jo
  • Patent number: 8946802
    Abstract: The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sivananda Kanakasabapathy, Tenko Yamashita, Chun-Chen Yeb
  • Publication number: 20150028408
    Abstract: An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Inventors: Andreas Meiser, Markus Zundel, Till Schloesser